TWI345785B - Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders - Google Patents

Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders Download PDF

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Publication number
TWI345785B
TWI345785B TW096128079A TW96128079A TWI345785B TW I345785 B TWI345785 B TW I345785B TW 096128079 A TW096128079 A TW 096128079A TW 96128079 A TW96128079 A TW 96128079A TW I345785 B TWI345785 B TW I345785B
Authority
TW
Taiwan
Prior art keywords
line
mode
bit
word line
bit line
Prior art date
Application number
TW096128079A
Other languages
English (en)
Chinese (zh)
Other versions
TW200814067A (en
Inventor
Luca G Fasoli
Christopher J Petti
Roy E Scheuerlein
Original Assignee
Sandisk 3D Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,364 external-priority patent/US7463546B2/en
Priority claimed from US11/461,339 external-priority patent/US7554832B2/en
Application filed by Sandisk 3D Llc filed Critical Sandisk 3D Llc
Publication of TW200814067A publication Critical patent/TW200814067A/zh
Application granted granted Critical
Publication of TWI345785B publication Critical patent/TWI345785B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
TW096128079A 2006-07-31 2007-07-31 Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders TWI345785B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/461,364 US7463546B2 (en) 2006-07-31 2006-07-31 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
US11/461,339 US7554832B2 (en) 2006-07-31 2006-07-31 Passive element memory array incorporating reversible polarity word line and bit line decoders

Publications (2)

Publication Number Publication Date
TW200814067A TW200814067A (en) 2008-03-16
TWI345785B true TWI345785B (en) 2011-07-21

Family

ID=38997814

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096128079A TWI345785B (en) 2006-07-31 2007-07-31 Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders

Country Status (5)

Country Link
EP (1) EP2062262B1 (enExample)
JP (1) JP5252233B2 (enExample)
KR (1) KR101478193B1 (enExample)
TW (1) TWI345785B (enExample)
WO (1) WO2008016932A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI927280B (zh) 2023-09-15 2026-06-01 台灣積體電路製造股份有限公司 記憶體裝置、其操作方法及其形成方法
US12646543B2 (en) 2023-09-15 2026-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device having tracking word line with adjust circuit, method of operating same and method of manufacturing same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5322533B2 (ja) * 2008-08-13 2013-10-23 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
US9202533B2 (en) 2013-10-09 2015-12-01 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation
US9390792B2 (en) 2013-12-23 2016-07-12 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line
KR102480013B1 (ko) * 2018-11-26 2022-12-22 삼성전자 주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379250A (en) * 1993-08-20 1995-01-03 Micron Semiconductor, Inc. Zener programmable read only memory
US7157314B2 (en) * 1998-11-16 2007-01-02 Sandisk Corporation Vertically stacked field programmable nonvolatile memory and method of fabrication
US6314014B1 (en) * 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
US6631085B2 (en) * 2000-04-28 2003-10-07 Matrix Semiconductor, Inc. Three-dimensional memory array incorporating serial chain diode stack
US6618295B2 (en) * 2001-03-21 2003-09-09 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array
US6917539B2 (en) * 2002-08-02 2005-07-12 Unity Semiconductor Corporation High-density NVRAM
JP2004071023A (ja) * 2002-08-05 2004-03-04 Elpida Memory Inc 半導体記憶装置
US6847047B2 (en) * 2002-11-04 2005-01-25 Advanced Micro Devices, Inc. Methods that facilitate control of memory arrays utilizing zener diode-like devices
CN1977337A (zh) * 2004-05-03 2007-06-06 统一半导体公司 非易失性可编程存储器
JP4524455B2 (ja) * 2004-11-26 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI927280B (zh) 2023-09-15 2026-06-01 台灣積體電路製造股份有限公司 記憶體裝置、其操作方法及其形成方法
US12646543B2 (en) 2023-09-15 2026-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device having tracking word line with adjust circuit, method of operating same and method of manufacturing same

Also Published As

Publication number Publication date
KR20090057231A (ko) 2009-06-04
TW200814067A (en) 2008-03-16
JP5252233B2 (ja) 2013-07-31
WO2008016932A2 (en) 2008-02-07
EP2062262B1 (en) 2014-05-07
KR101478193B1 (ko) 2015-01-02
EP2062262A4 (en) 2009-09-02
WO2008016932A3 (en) 2008-09-18
JP2009545835A (ja) 2009-12-24
EP2062262A2 (en) 2009-05-27

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