TWI345787B - Method and apparatus for hierarchical bit line bias bus for block selectable memory array - Google Patents

Description

1345787 IX. Description of the Invention: [Technical Field] The present invention relates to a programmable memory array, and is related to a semiconductor integrated circuit memory array incorporated into a passive element memory cell, and In particular, it relates to a two-dimensional memory array incorporating such a memory mask. [Prior Art]

A particular passive component memory cell exhibits rewritable characteristics. For example, in a particular memory cell, the stylization can be forward biased by a voltage of approximately 6 乂 to 8 V (eg, reference to one or two of them) The polarity of the polar body is achieved, and erasing can be achieved by using a voltage of approximately 1 〇ν to 14 ν to reverse bias the memory cell. These high voltages require the use of special high voltage CM〇s transistors in the word line and bit line decoders. This is not exactly as the memory cell word line and bit line spacing are reduced. This is particularly problematic for three-dimensional memory technology, in which the exit array must be interfaced with a word line and the word line and the pureness of the bit line to provide a decoding that is compatible with ever-decreasing array line spacing. And I/O circuits (and in particular the word line and bit line driver circuits are selected to function as memory cells - the ability to be sufficiently high voltage is even more. 2. SUMMARY OF THE INVENTION The present invention relates to an incorporation The memory array of the hierarchical bit line bias bus bar of the n-hidden array can be selected in a block, and the method for using the hierarchical bit line bias U for the block selectable memory array 1 and 'the present invention is defined by the accompanying patent scope 123l78.doc 1345787, and therefore nothing in this section should be construed as limiting the scope of such patents. In the aspect of the invention, the invention provides a circuit comprising a memory array having a plurality of array blocks, each array block comprising a word line and a bit line. The integrated circuit includes a first global bus bar that generally spans the plurality of array blocks. Used for Sometimes lightly-selected to select the location line to the individual data circuit. The integrated circuit also includes a different first bus segment per array block for passing during the first mode of operation for the first The operating mode H selects the positioning element line bias condition to the unselected positioning element line of the selected block, and transmits a second unselected positioning element line bias condition suitable for the first operating mode to the unselected array block The unselected line. In another aspect, the present invention provides an integrated circuit including a pattern of a plurality of array blocks, each array block including a word line and two The integrated circuit includes a light fitting member for coupling in a first mode by means of a first global exhaust bus that generally spans the plurality of array blocks - a selected imitation of the selected block The convergence of the current selection of the 兀 line to the individual circuit includes the coupling member, the basin is used for the red man to go to the eve of the "unselected positioning element for the light-selected and unselected array block to a fish system Flute one @ ^ One associated with each array block L-segment segment. The integrated circuit includes a transfer member for transmitting an adaptive body circuit for the first operational mode 'grass & , the use of = yuan line bias condition. The associated (four) first - sink two 1: hand on: the unselected array block is applied to the first operation mode 123178.doc 1345787 type of a second unselected Bit line bias condition. In another aspect, the present invention provides - the use of the ancient - species for the distribution. A memory array... = the body array has a plurality of array blocks, each array = two: the element line The method includes - in the -first mode of operation -: two-phase - the global array of the plurality of array blocks to lighten. ^ Selecting the block to select the location line to the individual data circuit, μ selection and • Unselected locator elements of the unselected array blocks are linked to an individual first-bus segment associated with each array area, and individual first-bus bars associated with the selected array block The segment is passed on the first operation mode 1#. - the first unselected positioning element Conditions, and with the first array associated with an individual unselected - vine #I H # ... s brother sheet discharge stream is transmitted on one of the first slave applies to the second operating mode unselected bit line bias conditions. In another aspect, the invention provides a method for making a memory product. The method includes forming a memory array having a plurality of array blocks, each array block comprising a word line and a bit line. The method further includes forming a first-global busbar that generally spans the plurality of array blocks for temporarily combining the selected location lines of the selected block to the individual data circuits. The method also includes forming a different first busbar segment per array block for communicating unselected elements suitable for the first selected positioning meta-line bias condition to a selected block during the first mode of operation: The line hand is applied to a second unselected locating element line bias condition of the first mode of operation to an unselected locating element line of the unselected array block. The invention is applicable in several aspects to a memory circuit having an array of memory, a method for operating such an integrated circuit and a memory array, and a memory product of the same type. Methods and computer readable media encodings of such integrated circuits, products or memory arrays, as described in more detail herein and in the accompanying claims, the techniques, structures and methods described herein, individually or in combination Use it. The foregoing is an overview and thus necessarily includes simplification, generalization and simplification of the details. Therefore, it is to be understood by those skilled in the art that the foregoing description is merely illustrative and is not intended to limit the invention in any form. Other aspects, innovative features, and advantages of the present invention are defined by the scope of the appended claims. [Embodiment] FIG. 1 is a schematic diagram of an exemplary passive component memory array i00. A sub-line 1〇2, 104 and a two-bit line 1〇6, 1〇8 are displayed. Assume that word line 1 〇 2 is a selected word line (SWL) and that word line 104 is an unselected word line (UWL). Similarly, the pseudo-positioning line 1〇6 is a selected positioning element line (sbl), and the pseudo-positioning unit line 108 is an unselected positioning element line (UBL). Four passive ' component memory cells 101, 1〇3, 1〇5, 107 are shown, each coupled between an associated word line and an associated bit line. The sufficiency single 7C 101 system is associated with the selected word line 102 and the selected positioning element line 〇6, so it can be regarded as a "S" unit (ie, "selected" unit memory unit 103 system and unselected The word line 104 and the selected positioning element line 1〇6 are associated, so it can be regarded as a unit (ie, “cutoff” unit). The memory unit 1〇5 is associated with the selected word line 1〇2 and the unselected positioning element line 108. Linked, it can be regarded as a Ή ” unit (ie "half-selected, unit). Finally, the memory unit 107 is associated with the unselected word line 1〇4 and the unselected positioning element line 〇8, so it is visible It is a %" unit (ie "unselected" 123178.doc 1345787 unit.) An exemplary bias condition for a forward bias mode of operation is also illustrated in Figure 1. As described elsewhere herein, this is The bias mode can be used in a stylized mode, a block erase mode, and a read mode (but typically such different modes use different voltage levels or conditions). As shown, the bias conditions can be considered as Applicable to a stylized mode of operation for a selected array block, and will be said The selected word line 102 is biased at a VSX voltage (e.g., ground), the selected bit line 106 is biased at a VSB voltage (e.g., +8 volts), and the unselected word line 104 is tied to a VUX voltage (e.g., +7·3 volts) is biased, and the unselected locating element line 108 is biased at a VUB voltage (eg, +0'7 volts). The selected locating element line bias voltage VSB can be regarded as a stylized voltage νρρ, Since substantially the entire electrical system acts on the selected memory cell 1 (because the selected word line is biased at ground), there is less specific resistance drop in the bus and array lines themselves. The bit line bias voltage VUB is also preferably set in a forward bias direction of one of the memory cells to correspond to an apparent, threshold voltage value, thereby indicating that a voltage ντ is acting on Similarly, the unselected word line bias voltage ν υχ is preferably set to a value of VPP-VT. Under these bias conditions, s unit 101 receives a equal to VPP. (for example, +8 volts) forward bias voltage, F unit 1〇3 receives an equal to ντ ( For example, a forward bias voltage of + 〇 7 volts, Η unit 1 〇 5 receives a forward bias voltage equal to ντ (eg, 7 volts), and u unit 1 〇 7 receives a value equal to νρρ_2ντ (eg, -6.6 volts) Reverse bias voltage. There are several exemplary memory 123178.doc 1345787 cell techniques, when biased under these conditions, the selected cell will change to a lower resistance value, and the F, Η and U cells There is no resistance change at all. An exemplary unit is described below. Referring now to Figure 2, an exemplary bias condition 200 for a reverse bias mode of operation is shown. ^ As described elsewhere herein, this reverse bias mode can be used for one Stylized mode or a block erase mode (but usually such different modes use different conditions). As shown, these bias conditions can be considered to be suitable for one use.

The stylized mode of operation or the erase mode of operation of a selected array block will be described as such. The bias conditions for these bias conditions VSX, vux, VSB, and VUB are now redefined for values applicable to this mode of operation. The selected word line 102 is biased at a VSX voltage of VRR/2 (e.g., +5 volts) and the selected 4-ary line 106 is biased at a vsB voltage of -VRR/2 (e.g., -5 volts). The unselected dice line voltage ν υχ and the unselected locating element line voltage VUB are both grounded. Under these bias conditions, the s unit 1 〇 1 receives a reverse bias equal to vrr (eg, -10 volts). At the voltage, the F unit 1〇3 receives a reverse bias voltage equal to yRR/2 (e.g., _5 volts), and the η unit 105 receives a reverse bias voltage equal to VRR/2 (e.g., _5 volts). It should be noted that the unit 107 does not receive any bias across the unit. In the right-handed memory cell technology (see below), when biased under this condition, the selected ± ^ " early 7L will change from a lower resistance value to a more resistance value. However, the F, H & U unit resistance of the Rong ^ ^ _ fly did not change at all. It should also be such that unselected U memory cells do not have any bias voltage and therefore do not have any leakage current of 123178.doc -U · 1345787, which may additionally support when biased across such cells at a few volts - a considerable amount (four) Leakage current. As described in further detail, many useful memory array embodiments include a much larger number of u cells than H cells or F cells' and such arrays are in the array compared to other biasing schemes; I have a significantly lower leakage current and therefore a much lower power consumption. 'By splitting "VRR voltage in this reverse mode, and biasing SBL' at a negative voltage equal to half the voltage of program #4匕 and at a positive voltage equal to a stylized; calendar-half Voltage SWL, bit line decoder and word line decoder. The voltage requirements are significantly relaxed. Thus, the higher pitch transistors in the array line driver circuits occupy less area than the smaller pitches of the P train lines (e.g., word lines and bit lines) because It can be designed to achieve a relatively low "segment" voltage. Other memory technologies have been faced with similar problems with stylized and erase voltages (and the area required for such south voltage transistors) that do not scale with memory cell spacing at the same rate. For example, the effect of this problem in flash memory is sometimes slightly reduced by the fact that the flash memory is the larger fanout of the main memory array. More Space Consumption Design for High Dust-Electrical Crystals - (4) Can be Stabilized in Some Renewal Techniques by Increasing Memory Block Size However, In-Diode-Based Passive Component Memory Array The size of the block is at the expense of an increase in the leakage of the unselected ciphers 7G belonging to the selected array. By removing such unselected memory cells as shown in Figure 2, the leakage component can be reduced to almost zero and a larger block size can be obtained with little or no detrimental power consumption. 123178.doc -12 1345787 An exemplary word line decoder circuit is now shown with reference to FIG. 3', including bias conditions for display in a forward bias mode of operation (as shown in FIG. A column decoder circuit is shown on the left side of the page, which displays two decoded outputs 158, 162. The decoded output 158 corresponds to - the selected decoded output, and the decoded output 162 corresponds to the - unselected decoded output ... the column decipher 152 can be implemented using any of a variety of well known techniques to produce a plurality of decoded outputs, such as rounds 155, 159, It is composed of multiplexers 157, 161 and inverters 156, 16

Conditionally reversed. A reverse buffer is incorporated after the NAnd gate to drive node 155 due to the larger capacitive load on node 158 (i.e., the result 'as multiplexer 157 manipulates node 155 to output 158 here) beta column solution The drinker 152 operates in this mode of operation, i.e., equal to the upper supply voltage of νρρ, which is coupled to the power supply node 153 and the grounded lower supply voltage is coupled to the power supply node 154. In this mode of operation, the column decoder is a "high state valid decoder" that is intended to drive a selected output (or outputs) such as decode output node 158 to the highest of the two available voltage states, here situation

In the case of VPP. (4) The unselected decoding source code output node 162 months is driven to the lowest of the two available voltage states, in this case grounded. The following will initially assume that only one such decoded output node (e.g., "high state") is selected at a time (e.g., "four" is combined to - or a plurality of word line drivers urn, and the decoded output node 158 is coupled to - word line A driver circuit includes a PMOS transistor 171 and a facet 8 transistor 172. Individuals of the transistors i7i,m have no extreme sub-systems that are simultaneously compliant to the word line, in this case representing the selected word line center. Although a particular embodiment of the invention encompasses decoding of the multi-head decoder 123178.doc -13- 1345787 However, FIG. 3 depicts a second word line driver circuit that is also coupled to the decode output node US, which represents one or more other word line driver circuits associated with this particular decode wheel out node 158. The second word line driver circuit includes a PMOS transistor 173 and an NMOS transistor 174, the output driver line 181, and the word line 181 representing one or more semi-selected word lines. The individual source terminals of the NMOS transistors in the various circuits of the word line driver circuits are coupled to an individual bus line of a source select bus XSEL. In this mode of operation, the source select bus is decoded based on the address information to bias such bus bars in an active state suitable for the word line of the operating mode, and is suitable for this operation. The remaining bus lines are biased in the inactive mode of the mode word line. In a particular embodiment, a plurality of such source select busses may be active, but now assume that bus bar 167 is active and biased at ground and one or more remaining bus bars (represented as confluence) Cable 168) is inactive and driven to the unselected word line voltage VUX (shown as VPP-VT). Since the voltage (vpp) on the decoded output node 158 is higher than the voltage of the bus bars 167, 168, the transistors (172) 172, 174 are both turned "on", thereby driving the selected word line 102 to ground, and The semi-selected word lines i8i to VPP-VT are driven. The two conductive paths are indicated as open-ended arrow lines. The individual source terminals of the PM〇s transistors in the various circuits of the word line driver circuits are coupled to an unselected bias line UXL, also labeled as node 164. In this mode of operation, the UXL bias line passes the unselected word line voltage νυχ. Since the voltage (vpp) at the decoding wheeling node 158 is higher than the voltage of the UXL bias line, the two pM〇s transistors 171, 173 are turned off. 123178.doc -14- 1345787 The decode output node 162 is coupled to a word line driver circuit that includes a PMOS transistor 175 and a sink transistor 176. The transistor π, μ::汲 terminal is simultaneously coupled to a word line, in which case the unselected sub-line 104 is also consuming to one of the decoded output nodes 162, the second word line driver circuit representation and the decoded output. Node 16 2 is associated with one or more of the remaining word line driver circuits 'and includes a PMOS transistor 177 and an NM 〇 s transistor 178, the output of which drives an unselected word line "^. The individual source terminals of the NM〇s transistors in each of the pre-driver circuits are coupled to an individual bus bar of a source select bus xsel. The voltage (ground) at the decoded output node 162 is At or below the voltage of the bus bars 167, 168, the two NMOSs 176, 178 are both turned off. The individual source terminals of the PMOS transistors in each of the word line driver circuits are coupled to The bias line UXL node 164 is not selected. Since the voltage (ground) at the decoded output node 丨62 is lower than the voltage of the UXL bias line 164 (above the low pm 〇 S threshold voltage), the two PMOS transistors 175, 177 are Turning on, thereby driving the unselected word lines 104 183 to VUX (e.g., VPP-VT). The two conduction paths are indicated as open-ended arrow lines. Referring now to Figure 4, this same exemplary word line decoder circuit is shown, including for a reverse bias mode of operation. The bias condition (shown in Figure 2). The decoded output 158 of the column decode circuit still corresponds to a selected decoded output, and the decoded output 162 corresponds to an unselected decoded output. The column decoder 152 operates in this mode of operation. The upper supply voltage equal to VRR/2 is coupled to the power supply node 153 and a grounded lower supply voltage is coupled to the power supply node 123178.doc • 15· 1345787 1 54. In this mode of operation, the column decoder is “ The high state active "decoder' and the active (selected) decoded output 158 is driven to the lowest of the two available voltage states using inverter 156 and multiplexer 157, in which case it is GND (ground) . The unselected decoded outputs (e. g., decoded output node 162) are driven to the highest of the two available voltage states using inverter 160 and multiplexer 161, in this case VRR/2. In this mode of operation, for the exemplary embodiment, the individual bus bars of the source select bus XSEL are all driven to the same bias condition (ground), and the "unselected" The bias line UXL delivers a bias voltage equal to VRR/2 (e.g., +5 volts). In this reverse mode of operation, the bias line UXL actually passes an active state suitable for the word line, rather than an invalid or unselected partial condition. Since the voltage (GND) on the decoded output node 158 is relatively lower than the voltage of the bias line ux1 (ie, above the threshold voltage of the lower PM 〇s), the PMOS transistors 171, 173 are both turned on, thereby The selected word line 102 is driven to VRR/2 and also drives the half-selected sub-line (shown here as selected word line 181) to vrR/2. The two guided paths are indicated as open-ended arrow lines. In this mode of operation, the source select buss XSEL are not decoded, and each such bus bar is biased in an inactive state (e.g., ground) suitable for a word line. Since the voltage (ground) at the decode output node 158 is not higher than the voltage of the bus bars 167, 168, the 172 and 174 are both turned off. Decode output node 162 is an unselected output that is driven to VRR/2 by inverter 16 and multiplexer 161. Since the power 123178.doc 1345787 on the decoded output node 162 is pressed against the voltage of the bus bars 167, 168, the ones are connected, thereby unselecting the word lines. 1〇4, 183 drive to ground. The two conductive paths are indicated as open-ended arrow lines. Since the voltage on the decode output node 162 is the same as the voltage across the UXL bias line 164, the two PMOS transistors 175, 177 are turned off. Referring now to FIG. 5, an exemplary bit line decoder circuit is shown, including a bias condition that is not suitable for the forward bias mode of operation (as shown in FIG. 卜, a row of decoder circuits is displayed on the left side of the page, which displays two The decoded output 2〇8, 212. The decoded output 208 corresponds to a selected decoded output and the decoded output 212 corresponds to an unselected decoded output. A row of decoders 2〇2 can be implemented using any of a variety of well known techniques to generate a complex number The decoded outputs, such as outputs 205, 209 ' are conditionally inverted by multiplexers 207, 211 and the inverters 2, 6, 210. Unlike the column decoder, after the nand gate There is no inversion buffer to drive node 2〇5 because the capacitive load on node 2〇8 is much lower than that used for the column decoder outputs. Row decoder 202 is in this mode of operation. Operation, one equal to the upper supply of vpp is coupled to the power supply node 203 and a grounded lower supply voltage is coupled to the power supply node 204. In this mode of operation, the row decoder is a "low state active" decoder. Such The selected decoded output (e.g., decoded output node 212) is driven to the highest of the two available voltage states, in this case VPP. The following will initially assume that only one such decoding round-out node 208 is selected at a time (eg, , low state ") Each decoding wheel is coupled to one or more bit line driver circuits. For example, decoding output node 208 is coupled to a one bit line driver circuit 123178.doc 1345787 includes PMOS transistor 22 1 With the NMOS transistor 22:) electric a day hip 222. The individual 汲 extremes of the transistors 221, 2 are simultaneously coupled to the -70 line 'in this case the table below does not select the bit line 106. Although the invention m I The specific embodiment of the month covers the decoder outside the multi-head decoder, but the description of Figure 5 is also coupled to the decoded output: 'Please the second bit line driver circuit, which represents the specific solution to the point 208 associated with - or a plurality of remaining bit line driver circuits. This second word line driver circuit includes a PM 〇s transistor 223 and a 〇 8 transistor

Body 224, the output of the transistors is driven - bit line 231, which represents one or more semi-selected positioning elements. Comparing the word line decoder, such a semi-selected positioning line can indicate that the selected positioning element line is maintained in an inactive state. The individual source terminals of the pM〇s transistors in the various circuits of the bit line driver circuits are coupled to one of the source select busses selb individually = the bank lines. In this mode of operation, the source selects the busbar muscles (4) data dependent, and can be further decoded based on the address information, such that for this mode of operation, one or more such bus lines are applied to one

The bit 7L line is biased in an active state, and for this mode of operation, the remaining bus bar is biased in an inactive state suitable for the bit line. In a particular embodiment, one or more of such source selection bus bars may be active 'but now assume that bus bar 2 1 7 is active and biased at vpp, and one or more remaining confluences The cable (denoted as bus bar 2丨8) is invalid and is driven to the unselected location line voltage VUB (shown as VT). Since the voltage (ground) on the decoding output node 208 is lower than the voltage of the bus bars 217, 218, the 1 > 1 ^ 8 transistors 221, 223 are both turned "on" to drive the selected bit line 1 〇6 to Vpp and drive the semi-selected positioning element 123178.doc 1345787 line 23 1 to VT. The two conductive paths are indicated as open-ended arrow lines. The individual source terminals of the NMOS transistors in the various circuits of the bit line driver circuits are coupled to an unselected bias line UYL, also labeled as node 214. In this mode of operation, the UYL bias line delivers the unselected location line voltage VUB. Since the voltage (ground) at the decoded output node 208 is lower than the voltage of the UYL bias line, the two NMOS transistors 222, 224 are cut off. The decode output node 2 12 is coupled to a one bit line driver circuit that includes a PMOS transistor 225 and an NMOS transistor 226. The individual 汲 terminal sections of the transistors 225, 226 are simultaneously coupled to a single bit line, in this case the unselected locating element line 108. A second bit line driver circuit coupled to the decode output node 212 represents one or more remaining bit line driver circuits associated with the decode output node 212 and includes a PMOS transistor 227 and an NMOS transistor 228, such The output of the transistor drives an unselected positioning element line 233 °

As described above, the individual source terminals of the PMOS transistors in the various circuits of the bit line driver circuits are coupled to one of the individual bus bars of a source select bus SELB. Since the voltage (VPP) at the decoded output node 2 12 is at or above the voltage of the bus bars 217, 218, the PMOSs 225, 227 are both turned off. The individual source terminals of the NMOS transistors in the various circuits of the bit line driver circuits are coupled to unselected bias line UYL node 214. Since the voltage system VPP on the output node 212 is decoded, the two NMOS transistors 226, 228 are turned "on", thereby driving the unselected positioning elements 108, 233 to VUB (eg, VT). 123178.doc -19- 1345787 Open-Ended Arrow Line Referring now to Figure 6, the bit line decoder circuit is shown, including bias conditions suitable for the reverse bias mode of operation (shown in Figure 2). The decoded output 208 of the row decoder circuit still corresponds to a selected decoded output, and the decoded output 212 corresponds to an unselected decoded output. The row decoder 2〇2 operates in this mode of operation, with a supply voltage coupled to the power supply node 203 and a lower supply voltage _VRR/2 coupled to the power supply node 2〇4. In this mode of operation, the row decoder is a "high active" decoder, and the active (selected) decoded output 208 is driven to two available by inverter 206 and multiplexer 2〇7. The highest voltage state, in this case, is GND (ground). The unselected decoded outputs (eg, decoded output node 2 12) are driven to the two by inverter 210 and multiplexer 211. The lowest of the available voltage states, in this case -VRR/2. In this mode of operation, for the exemplary embodiment, the individual busbars of the source select bus SELB are all Driven to the same bias condition (ground), and the "unselected" bias line UYL delivers a bias voltage equal to -VRR/2 (eg, -5 volts). In this reverse mode of operation, the bias The voltage line UYL actually passes an active state suitable for the bit line' instead of an invalid or unselected bias condition. Since the voltage (ground) at the decoded output node 208 is considerably higher than the voltage of the bias line uyl (lower than NMOS threshold voltage), the NMOS transistors 222, 224 are both turned on, thereby driving the selected positioning element line 106 to -VRR/2, and driving the originally half-selected bit line (shown here as the selected positioning element line 231) to -VRR /2. The two conduction paths are indicated by an open-ended arrow line. 123178.doc -20. 1345787 In this mode of operation, the source selection bus SELB is non-data dependent or not decoded (at least in a given Within the block, and each such bus bar is biased in an inactive state (eg, ground) suitable for one bit line. Both PMOS transistors 221, 223 are turned off. Decoding output point 212 The output is unselected and driven to _vrr/2. The PMOS transistors 225, 227 are both turned "on" to drive the unselected positioning lines 108, 233 to ground. The two conductive paths are indicated as being on. Tail arrow line. The two NMOS transistors 226, 228 are cut off. It should be noted that in the forward mode, the row decoder is active low and the bit line high is active. However, in the reverse mode Next, the row decoder reverses its polarity and becomes active high, and the bit line itself is also reversed. In the forward mode, the column decoder is active and the word lines are active low. However, in the reverse mode, the column decoder reverses its polarity and becomes The low state is valid, and the word lines themselves are also reversed and become high. "It should also be noted that the output level of the decoder is in the forward mode (ie GND to VPP) and the reverse mode (ie -VRR/ Offset between the average voltages between 2 and GND. When viewed as a non-multi-head decoder (in Figures 3, 4, 5 and 6, only non-dashed array line driver circuits), this decoding can be described very simply The operation of the circuit. In the reverse mode, the word line decoder reverses its polarity and places a selected word line high (~5 V)' while maintaining all other selected word lines grounded. This reversal occurs on the bit line selection side where one bit line is selected and becomes -5 V and all other bit lines are grounded. The end result is a 10 V reverse bias across the selected memory cell and a zero reverse bias across the other cells. 123178.doc • 21 - 1^787 The transistors in these word lines and in the bit-dynamic circuit must only withstand the maximum voltage of J5 - half, not the entire voltage. When using a multi-head decoder (in Figures 3, 4, 5, and 6, including the virtual array 2 driver circuit), it should be noted that the circuit is at that °. (d) Solving the 32 source selection bus, which allows the selection of the array of the array line - (but simultaneously drives the remaining semi-selected array lines to the unselected bias condition). However, in the reverse mode, the selected decoded output from the 歹J and the row decoders combines the array lines to a single unselected partial I line (eg, UXL and UYL). The m(four) line is not available in the reverse mode. Semi-selected array line. Thus, the above described circuits and techniques are useful in configuring an array of line blocks (e.g., "block erase") to be selected in the reverse mode. As can be seen in Figures 4 and 6, a selected wordline block and a selected location line block are simultaneously selected in the reverse mode without any independently configurable semi-selected array lines. This type of block operation all avoids the need for any semi-selection lines. The decoding implications may be very similar to those described in U.S. Scheuerlein, U.S. Patent No. 6,879,5,5, entitled "Word Line Configuration for Multi-Dimensional Word Line Segments for Three-Dimensional Memory Arrays" Neigu is fully incorporated herein by reference. Whether this block operation can be configured (or how large a block can be configured) depends mainly on the number of cell reset currents, the number of cells that conduct such reset currents, and the word line driver circuit and bit lines. Whether the PMOS and NMOS transistors in the driver circuit can support such currents at an acceptable voltage drop. A semi-selected array line can be provided in this reverse mode by using other techniques (except in the forward mode). In a single such technique, 123178.doc -22- 1345787, the column and row decoders may be powered by an overvoltage such that the decoding turn-out nodes are above the PM0S source voltage and below the ^^1^ 〇8 source voltage and traverse. By doing so, the selected word line can be driven up to +VRR/2 voltage through the 1^he 8 transistor, and the positioning can be selected through the PM0S transistor, and the line driving can be as low as -VRR/2. This utilizes the same transistor as during the forward mode to drive the selected word line and bit line. Such techniques are illustrated in Figures 7 and 8. Referring initially to Figure 7, a word line decoder circuit is illustrated which utilizes an overdrive decode output to drive the array line drivers with their sources maintained under the bias conditions described above. In this column decoder circuit *, the column decoder 15 2 is powered by an 8 volt upper supply voltage and a negative i volt lower supply voltage. The polarities of the decoded output nodes 158, 162 are inversely relative to the polarity shown in Figure 4, and are now a high effective decoder that provides a selected output 158 at +8 volts and provides one at _ volts. Decoded output 162 is not selected. Source Select Bus XSE [Keep a decoding busbar unchanged. One (or more) of its individual bus bars are selected and driven to +5 volts, and the unselected wires are driven to ground. NMOS transistor 172 is turned "on" and conducts the selected word line 1 〇 2 to the associated xsel bus line voltage (+5 volts). The NM0S transistor 174 is also turned "on" and conducts the (etc.) half-selected word line 181 to ground. When the decoded output node - 162 is not selected at "1 volt", the PMOS transistors 175, 177 are simultaneously turned on and the unselected word lines 104, 183 are conducted to ground. In some embodiments utilizing this technique, the conditional output inverters 156, 16A and the multiplexers 157, 161 (shown here as "dashed lines,") are not used. Referring now to Figure 8, A bit line decoder circuit is illustrated which also drives the array line drivers using a 123178.doc • 23-1345787 overdrive decoding output. In this row decoder circuit, the row decoder 202 is comprised of a +1 volt. The high supply voltage is supplied with a negative 8 volt low supply voltage. The polarities of the decoded output nodes 2 〇 8, 212 are inversely opposite to the polarity shown in Figure 6, so now a low effective decoder is under volts. A selected output 208 is provided and an unselected decoded output 212 is provided at +1 volts ^ one of the individual SELB bus bars 217: (or more) selected and driven to _5 volts, and the unselected The SELB sink φ bus line 218 is driven to ground. The PMOS transistor 221 is turned "on" and conducts the select bit lines 106 to the associated SELB bus line voltage (_5 volts). The PMOS transistor 223 The system is also connected, and the (equal) semi-selected word line. 231 To ground. When the unselected decode output node 212 is at +1 volt, the NMOS transistors 226, 228 are simultaneously turned on and the unselected locating elements! 08, 233 are conducted to ground. In some embodiments of the technology, the conditional output inverters 2〇6, 2^〇 and the multiplexers 207, 211 are not used. In another technique, the semi-selected word lines and bit lines are semi-selected. The bus line can be provided in the reverse mode by replacing the single unselected bias lines UXL and UYL and the individual-inverted source selection bus. Referring now to Figure 9, a word line is illustrated: a circuit that utilizes a dual decoded source select bus. One of the PMOS transistors used for the word and line driver is replaced by the unselected bias shown in FIG. The remainder of the wordline decoder circuit operates as previously described. In this reverse mode, the selected decoder wheeling node 158 is active low and driven to ground. The reverse source selects the busbar. One of the individual sinks of xsELp 123178.doc -24· 1345787 To an effective bias condition suitable for the reverse mode of operation of a word line. In this case, the selected bus line 243 of the XSELP bus is driven to VRR/2, and the unselected bias of the XSELP bus is driven. Line 244 is driven to an inactive bias condition suitable for this mode of operation of a word line, in this case driven to ground. PM〇s transistor 171 is turned on by a low voltage coupled to its gate. Driving the selected word line 1〇2 to the VRR/2 potential. However, the PMOS transistor 173 in the half-selected word line driver circuit remains off because the voltage on its gate is not sufficiently low relative to its source. Because both are grounded. Since the NMOS transistor 174 is also turned off, none of the transistors in the half-selected word line driver circuit are turned "on". Therefore, the semi-selected word lines float at or near the ground potential. This obstacle occurs when the NMOS pull-down transistor 174 is larger than the PM 〇s pull-up transistor 173 in the case of an exemplary circuit. A larger transistor has a larger number of leaks than a smaller transistor than a smaller transistor. Therefore, since the transistor 174 has a substrate tied to the ground, the grounding, /3⁄4 leakage current dominates the substrate leakage current to vrr/2 generated by the PMos transistor 173, and this net current tends to be unselected. Word line 181 is maintained at or near ground potential. The dedicated sub-line driver circuit associated with the unselected decode output node 162 operates as previously described, and the transistors 176, 178 are turned "on" to conduct the unselected word lines 1 〇 4, ι 83 to ground. In an alternative embodiment, the low levels of the decoded output nodes 158, ι 62 can operate the column decoder 152, the inverters 156, 160, and by using a low power supply 154 equal to _VTP (or lower). Multiplexer 157, ι 61 drives 123178.doc -25-1345787 to move below ground (eg, to a voltage below PMOS threshold voltage below ground, or -VTP). Thus, the PMOS pull-up transistor 173 is turned "on" to effectively drive the (equal) half-selected word line 181 to ground.

A similar situation occurs in a row decoder circuit that incorporates a dual data dependent source select bus. Referring now to Figure 10, a one-bit line decoder circuit is illustrated which utilizes dual decoding (in this case data dependent) source selection bus. One of the NMOS transistors for the bit line driver circuit, the reverse source select bus SELN, has been incorporated in place of the unselected bias line UYL shown in FIG. The remainder of this bit line decoder circuit operates as previously described.

In this reverse mode, the selected decode output node 208 is active high and driven to ground. One of the individual bus bars of the reverse source select bus SELN is biased to an effective bias condition suitable for the reverse mode of operation of the one bit line. In this case, the selected bus bar 247 of the SELN bus is driven to -VRR/2, and the unselected bias line 248 of the SELN bus is driven to a bit line suitable for this mode of operation. The bias condition, in this case, is driven to ground. NMOS transistor 222 is turned "on" by a high voltage coupled to its gate and drives selected word line 106 to the -VRR/2 potential. However, the NMOS transistor 224 in the half-selected word line driver circuit remains off because the voltage across its gate is not sufficiently high relative to its source, since both are grounded. Since the PMOS transistor 223 is also turned off, any of the transistors in the half-selected locator driver circuit are not turned "on". Therefore, the semi-selected positioning elements float at or near the ground potential. As in the case of this exemplary circuit, 123178.doc -26- 1345787 'This occurs when the PMOS pull-up transistor 223 is larger than the NMOS pull-down transistor 224. Larger crystals have a much larger number of leaks than their smaller ones than smaller ones. Therefore, since the larger transistor 223 has a substrate that is tied to the ground, the ground leakage current dominates the substrate leakage current to -VRR/2 generated by the NMOS transistor 224, and the net current tends to be the same. The selected word line 231 is maintained at or near the ground potential. The bit line driver circuits associated with the unselected decode output node 212 are turned "on" to operate the PMOS transistors 225, 227 to conduct the unselected bit lines 108, 233 to ground. The operation of both of the decoder circuits in the forward operation is substantially as shown in Figures 4 and 6. Consider the column decoder case, in which the source select bus is decoded and all unselected word lines are driven to the unselected bias line UXL. In the positive mode using the dual decode column decoder, the reverse source select bus is not decoded and all of its individual bus lines are driven to the same voltage as the UXL bus. Thus, # the word line driver circuits operate unchanged with respect to FIG. Indeed, a single bias line UXL has been replaced by a plurality of "bias lines", each bias line is driven to the same voltage as the former UXL bias line, and each unselected word line drive: to The bias line " in the case of the row decoder, the source select bus SELB is decoded in the forward mode and all unselected bit lines are driven to the unselected bias line UYL. In the forward mode using the dual decoded row decoder, the reverse source select bus is not decoded and all of its individual bus bars are driven to the same voltage as the UYL bus. Thus, the bit line driver 123178.doc • 27-1345787 circuit operates unchanged with respect to FIG. Indeed, a single bias line UYL has been replaced by a plurality of "bias lines", each bias line is driven to the same voltage as the former UYL bias line, and each unselected positioning line is driven to the bias Pressure line. The decoder circuits described so far are used to implement a memory array in which the memory unit includes a reversible resistor plus a diode. Such a memory cell can be reset using a reverse bias applied across the cell, and for semi-selected word lines and bit lines allows individual word lines and bit lines to be placed under a reset bias condition 'Therefore providing the ability to reset individual memory cells without having to reset an entire block. The techniques described in Figures 7 and 8 have the advantage of having only a single decoded source select bus, but since the column and row decoders are powered by overvoltage, the voltage requirements for such decoder circuits are even greater. high. The techniques described in Figures 9 and 1 are at the expense of an additional decoding (and/or data dependent) reverse source select bus and the possible increased area of the array line driver incorporating the second decoded source select bus. These voltage requirements are reduced by not supplying overvoltages to the two decoder circuits. This bit line selection circuit is up to twice as large as the bus line and may have limited wiring. The word line select circuits may also be slightly larger and have limited wiring (ie, the word line driver circuits include six additional decode lines for a six-bit decoder, and the pM〇s device is slightly larger than the earlier circuit) . Nonetheless, either technique may be more useful than other techniques of the application. The forward mode is illustrated in the context of a simplification condition in which the voltage applied to the selected locating element is vpp. The forward mode is also applied to a 123178.doc • 28· 1345787 «sell mode, in which the selected bit line is mediated to a read voltage VRD, and the selected sub-line is driven again to ground. Such a read voltage may be a voltage that is much lower than the stylized voltage VPP, and the unselected word line bias voltage VUX and the unselected bit line bias voltage VUB are thus used in the stylized mode The value is reduced. A particular memory unit can be "programmed" using a forward bias mode and use the S-Hour reverse mode to erase blocks. Other units can be pre-conditioned using an initial forward bias programming technique (eg, during manufacturing), but then the reverse mode is used to "stylize" and use the forward mode to erase. Avoid confusion with historical usage in stylized techniques, and to fully understand the different memory technologies used in conjunction with the decoder circuits described so far, three different modes of operation are used to illustrate: reading, sighing And resetting. In the read mode, a read voltage VRD is applied across a selected memory cell. In the set mode, a set voltage VPP is applied across a selected memory cell. In the specific embodiment, 'the read voltage VRD and the set voltage vpp are both positive voltages' and this mode is implemented using a forward decoder mode of operation. In the reset mode, across a selected memory The cell applies a reset voltage VRR. In the exemplary embodiment described so far, the reset voltage VRR is applied as a reverse bias voltage and uses the reverse decoder The mode is implemented. The reset mode uses a split voltage technique to limit the voltage requirements for the decoder circuits and drive a selected bit line to a negative voltage (ie, using a triple well semiconductor structure). Alternatively, the reset mode can be implemented by 123178.doc • 29-1345787 with a completely non-negative voltage. In this case, the reset voltage VRR is passed to the selected word line and the ground is passed to the selected bit line. Preferably, the VUX and VUB voltages are set to approximately VRR/2. Many types of memory cells (described below) can be programmed using the reset mode. Among the specific techniques of the memory cell technology An antifuse in each memory cell initially jumps in the forward direction. Then, in the direction of the reverse bias, "tuning" the resistance of each memory cell to complete the stylization. The same is true for the second programmable unit. For the rewritable unit, the forward direction is used to erase the unit, which can be executed in blocks of various sizes, and then programmed using the reverse mode. The reverse bias is used to reset the selected memory unit. The stylized current is supplied by a diode collapse. In addition, the bias conditions associated with the stylization can be carefully controlled, including control. The voltage slope of the selected word line and/or the bit line. Additional insights into the use of the stylization technique can be found in U.S. Patent No. 6,952,030, the disclosure of which is incorporated herein by reference. And as described in more detail in the ΜΑ163-1 application, which is referred to below, a plurality of stylized operations can be used to program various resistance states. The use of the tilted stylized pulses is described in the SAND-01114US0 referenced below. The technique of fine-tuning the resistance of a plurality of cells in the SAND-01114US1 application is described in the SAND-01117US0 and SAND-01U7US1 applications referenced below. As described above (especially in the context of dual decoded source select lines), the use of reset programming to program a passive component memory cell incorporating a trimmable resistive element provides greater flexibility to allow for a larger array of blocks. Large hours are especially used for 123178.doc • 30-1345787. Even in a selected Chen Yujiu & block (as all of the above assumed), there is no bias across the memory in this reset mode. Therefore, there is no wasted power consumption. The reverse current through a unit (4) is independent of the block size. Therefore many blocks can be selected to increase the write bandwidth. In addition, the voltage across the selected memory cells is only half of the programmed voltage and is safely used for the cells. It should be noted that in the above, the reset mode illustrates selected and semi-selected word lines and bit lines. For example, in the context of column selection, a given address may not actually select such a semi-selected word line, and this term is an artifact of the multi-word line driver structure. However, in the context of the bit line, such a semi-selected 7G line may actually be selected as long as it relates to the row address, but may be biased to an inactive state for the bit line instead of Valid state, because the specific material used for the bit line does not require a "stylized" unit, or because the bit line is being "waiting" is programmed. This situation is programmed at the same time less than bit line decoding. The number of heads occurs. However, it should be noted that stylized bandwidth concerns suggest configuring a memory array to program the bit lines as much as possible at the same time. The dual well processing allows the (equal) selected bit lines to obtain a negative voltage, And the (equal) selected word line obtains a positive voltage. In the reset stylized (ie, reverse mode), the reference level for all unselected array lines (no bit lines and word lines) is grounded. Quickly decode and select both word lines and bit lines. Refer again to the description of the semi-selected word lines and bit lines floating at ground (due to the leakage current to the well potential of the largest of the two driver transistors) , the 4 § recall The resistive nature of the cell provides an additional shallow leakage current between such semi-selected array lines and the unselected 123178.doc -31 - ^45787 : array lines. The array line active dimensions are in the unselected partial wear position. This advancement step facilitates the floating of the unselected array lines at or near the unselected bias potential.

Two-dimensional memory arrays are covered, but it is believed that these decoder configurations are particularly useful for a three-dimensional memory array with multiple memory planes. In a particularly preferred embodiment, the memory array is configured such that each word line includes a word line @ on each memory plane of a plurality of memory planes, as described below. . 11 is a block diagram of an exemplary memory array 300. Dual column decoding ^ 02 304 produces column select lines for the array, with each column select line spanning array 300, as described herein below. In this embodiment, the word line driver circuits (not shown) are spatially distributed under the memory array and by alternating sides of individual memory array blocks (two blocks labeled 306, 3〇8) Vertical connections (one of which is labeled 31〇) are connected to the word lines. The non-remembered array includes two memories, a strip "3丨8, 32〇, and further includes four row decoders and bit lines at the top, middle, lower, middle, and bottom of the array, respectively. Circuit blocks 312, 314, 315, 316. Additional strips may also be incorporated as described herein, and each strip may include one or more memory shelves. The bit lines in each block are also 2:1 interleaved to relax the line-to-path spacing requirements. As an example, bit line 322 is associated with (i.e., driven and sensed by) upper row circuit block 312, and bit line 324 is associated with bottom row circuit block 314. In an exemplary embodiment, the memory array 3 is a three-dimensional memory array of passive element memory cells formed on the memory planes of the four memory planes. Such a memory cell is preferably incorporated into a fine tunable U3l78.doc -32. 1345787 resistor element (as described herein) and may also include an antifuse. Each logic sub-line is connected to a word line segment (each associated with a different memory plane) on each word line layer of the four word line layers. Each strip of memory array 300 is divided into a plurality of blocks, such as blocks 3〇8. In the particular exemplary embodiment described herein, each memory rack includes 16 array blocks, although other numbers of blocks may be implemented. In the illustrated example I"[0012], each block includes 288 bit lines on the bit line layers of the four φ bit line layers for the individual four memory planes, thus totaling each block 1,152 bit lines. The bit lines are 2:1 interleaved such that the row decoders and data I/O circuits are arranged at the top and bottom of the array block. Each circuit interfaces 576 bit lines. Other numbers and configurations of such bit lines and array blocks are also contemplated as including higher numbers. Within a selected memory array block, one of the source select bus lines - XSELN (or reverse source select bus XSELP) is decoded and driven by a column of bias circuits to - effectively depleted conditions, The remaining bus bars, (also referred to as bias lines), are driven to an inactive condition (ie, a voltage applied to an unselected. word line). Therefore, a single selected RSEL line (ie, column select line) , corresponding to the decoding output node 158 in FIG. 3, driving a word line in the selected memory block to a low state, and moving other N1 word lines in the selected block to the unselected partial Press level. In other non-selected memory blocks, any individual bus lines of the source and reverse source select bus bars are not driven to be active, so no valid word lines are selected for the active RSEL line. , the source and reverse source selection bus bars in the unselected array block can be floated 'in particular in the forward mode. 123178.doc -33. 1^4^/87. Column selection The line spans all memory blocks in the entire memory strip and drives each of the strips The block (and two or more of the two word lines between the two and the last block "external" are driven by the word line. These RSEL lines can also be called "global column lines" (d) may correspond to the column decoder output nodes referenced herein. Additional details of exemplary circuits, operations, bias conditions, floating conditions, modes of operation (including read and stylized modes), and the like are further described above. U.S. Patent No. 6,879,5,5, issued to U.S. Patent No. 7, s. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No. , the entire disclosure of which is hereby incorporated by reference in its entirety by reference in its entirety in its entirety in its entirety in its entirety in the the the the the the the the The decoding circuit of the line driver group " is issued as of US Patent Application Publication No. 2006-0221702 on October 5, 2006, the entire disclosure of which is incorporated herein by reference. Quickly select the time of the global column line, which is selected by the two-level column selection decoders 302, 304 (also referred to as "global class decoders 302, 304"), respectively on the left and right sides of the array strip Outside the array, it is driven at both ends. By using a hierarchical decoder structure, the size of the global column decoder 302 is reduced, thereby improving the efficiency of the array. Further, a reverse decoding mode can be conveniently provided to obtain Improved testing capabilities, as further illustrated on July 6, 2006 as US Patent Application Bulletin No. 2〇〇6_ 0145 193, US Application No. 11/026,493, December 30, 2004, Kenneth K. So et al.'s "Double-Mode Decoder Circuit, 123178.doc -34- 1345787 is incorporated into its Integrated Circuit Memory Array and Related Operation Methods", and the contents of the Dragon 8 are incorporated herein by reference. . Exemplary circuit for such hierarchical decoding can be found in U.S. Patent Application Publication No. _ 0146639 A1, by Luca G. Fas〇u et al., "Using a dense memory array using a multi-level multi-head decoder." Apparatus and method for hierarchical decoding, the entire disclosure of which is incorporated herein by reference. An exemplary four-head decoder circuit package in the specific materials described herein

m includes four "selected" bias lines and - single-unaccepted bias lines. The basic principle of this designation is because when selecting the input of a given decoder head (ie driving to a valid level), the decoding The head couples its output to the ""selected" bias line. However, this does not imply that all four of the heads shown drive their individual outputs to - reflecting the level at which the output is being selected Because, in general, only the selected bias lines are - are suitable for - the actual bias under the condition of the selected output, and the remaining three selected bias lines are biased to an unselected output. The "option" bias line used in a multi-head decoder is described herein as a "source selection bus", but similar to the operation, except for reminders. Some Particular embodiments also include a second such bus bar that is a "reverse source select bus" rather than a single unselected bias line. Conversely, 'if the input node for the multi-head decoder is invalid or unselected, then all such headers drive their individual outputs to an associated "unselected" bias line (or - reverse source select sink) Rows of individual bus lines). For a particular embodiment, such unselected bias lines can be combined into a single bias line shared by all of the heads of the multi-head decoder. 123178.doc •35- 1345787

Similar or related word line decoder structures and techniques, including additional levels of such decoding, bias circuit blocking and associated support circuits for such decoding busses (eg, XSELN and XSELP), further illustrated in R〇y E

U.S. Patent No. 6,856,572 to Scheuerlein and Matthew P. Crowley, entitled "Multi-head Decoder Structure Using a Memory Array Line Driver with Dual-Use Driver Device", the entire disclosure of which is incorporated herein by reference, U.S. Patent No. 6,859,410 to E. Scheuerlein and Matthew P. Crowle, entitled "Tag Decoder Structures Having Interfaces Having Very Small Layout Spacing", the entire disclosure of which is hereby incorporated by reference. Figure 12 is a top plan view showing one of a word line layer and a bit line layer of a three-dimensional memory array in accordance with a particular embodiment of the present invention. Other word line layers and bit lines can be implemented using the layers shown and share the same vertical connections in some embodiments. Display memory blocks 332, 334 include a plurality of bit lines 333, 335, respectively, and have 2: 1 interleaved word line segments. The vertical connection to one half of the word line segments for a block is to the left of the block (e.g., word line segment 337 and vertical connection 339), and to the other word line segments for the block Half of the vertical connections are to the right of the block (eg, sub-segment 336 and vertical connection 340). In addition, each vertical connection is used in a block of two adjacent blocks for a word line segment. For example, vertical connection 340 is coupled to word line segment 336 within array block 332 and to word line segment 338 within array block 334. In other words, each vertical connection (e.g., vertical connection 340) is shared by a word line segment within each of the two adjacent blocks. However, if desired, the individual "external" vertical connections for the first and last array blocks 123178.doc -36· 1345787 are only used for word lines within the first and last array blocks. Fragment ° For example, if block 334 forms the last block of a plurality of blocks of a memory array (or a single body frame), its external vertical connection (eg, vertical connection 344) may be used only for The word line segment 342 within block 334 is thus not shared by the second word line segments throughout the other portions of the array. By interleaving the word lines, the vertical connections are separated by an individual word: twice the distance between the line segments themselves. This is particularly advantageous because the word line spacing available for φ in many passive element memory cell arrays is significantly less than the distance between many channel structures that are known for use in forming vertical connections. Moreover, this also reduces the complexity of the word line driver circuit for implementation within the semiconductor substrate underneath the memory array. Referring now to Figure 13, a schematic diagram is shown showing a three-dimensional memory array column having a -fragmented word line configuration in accordance with a particular embodiment of the present invention. Each word line is formed by one or more word line segments of at least one (and advantageously a plurality of) word line layers of the memory array. For example, a first word line is formed by a word line segment 36 disposed on a word line layer of the memory array. The word line segment 362 is placed on the other word line layer. The word line segments 360, 362 are connected by a vertical connection 358 to form a first word line. The vertical connection also provides a connection path to driver means 171, 172 placed in another layer (e.g., within the semiconductor substrate). A decoded output 352 from a column decoder (not shown) is substantially traversed parallel to the word line segments 360, 362, and sometimes the device line 172 is coupled to the word line segments (10), 362 to - substantially Parallel to the word line segments traversing the decoding offset 167 (eg, the source selection bus bar), sometimes coupled by the device 171 123178.doc -37- / δ / the word line segments 360, 362 Man $铉π disaster. The decode bias line 203 is decoded (e.g., the reverse source select bus XSELP as shown). Also shown are word line segments 361, 363 which are connected by a vertical connection state-to-first word line and provide a connection path to the word line driver circuit. Another decoded output 353 from the column decoder is sometimes transmitted through the device. 176 coupling the words κ ～ 片 361, 363 to the decoded source select line (ie, "bias line 丨丨" 167, right 拄, wind at) sometimes through the device to the word line segment 361, 363 coupled to the decoding bias performance " ° s This illustration conceptually introduces an exemplary array configuration, but the following is also the beginning of the day. 1 ^ May Xu Hua specific embodiment, which includes the changes shown in the group ~ 'And including details that may be applicable to a particular embodiment, but not necessarily to all of the specific embodiments. In a particularly preferred embodiment, a six-word line driver is utilized. Six of the six word line driver circuits are associated with each other. The word line is composed of two adjacent memories, and the block is described in U.S. Patent No. 7,054,219. The terminating word line driver of the switch decodes and drives six word lines in each block of two adjacent blocks. The figure implies that the adjacent blocks can be regarded as The knives are to the left and to the right of the associated word line drivers. However, in a preferred embodiment, the multi-head sub-line drivers are placed substantially below the array blocks. And only such vertical connections to the word lines are fabricated between the blocks. Specific implementations with non-mirror arrays (eg, a word line layer associated with only a single bit line layer) are contemplated. For example, U.S. Patent Application Serial No. 1 1/095,907, filed on Jan. 31, 2005, to the entire disclosure of the entire disclosure of ;' now 123178.doc -38- 呀345787

The entire disclosure of U.S. Patent No. 7,142,471 is incorporated herein by reference. Specifically, Figure 15 shows a 4-bit line layer at the same time, and a 16-bit row decoder on the top and bottom sides of an array block. The β-picture shows the 4-bit line on each layer of the 4-bit line layer. It is coupled to the top data bus (description 4 〇 / 〇 layer) by a single 16-bit row decoder, and the 4-bit line on each layer of the same 4-bit line layer is solved by a single 16-bit row. The device is consuming to the bottom data bus (but in this description, the 16 selected positioning elements of the two groups are located in the same array block). Other embodiments, such as a two-bit line layer sharing a word line layer, are contemplated to form two memory arrays.

In the following figures, various specific embodiments utilizing reset stylization (i.e., reverse bias programming) are illustrated. Therefore, some definitions are used in turn for this part of the content. The term "set" shall be considered as forward biasing a single (or group) of memory cells 'to cause a lower electrical F through each memory cell" A memory cell block that causes a lower resistance through each of the memory cells. Finally, the term "reset" should be considered as reverse biasing a memory cell to cause a change through each such cell High power [(For other specific embodiments described herein, such definitions may not

Be applicable. The term "wipe " erase " can also refer to a reverse bias condition across a memory cell to increase the resistance of the cell. Referring now to Figure 14, the memory array 370 includes a first strip 37 丨 and a first strip 372.兮笛..必弟—Article 371 is also marked as a bar and the second 372 is also T. Bar 371 includes two memory racks BAY-〇〇 and 8-8¥_〇1. Each such frame has a plurality of array blocks (e.g., 16 such memory 123178.doc • 39-1345787 body array blocks). Although this exemplary memory array 370 is shown to include two memory strips each having two memory racks, other numbers of strips and racks are also contemplated. The first memory rack BΑΥ_〇〇 represents another memory rack. A total of 16 memory array blocks, two of which are labeled 374 and 375, each having a sense amplifier placed under the memory array (eg, within the 'semiconductor substrate layer, but one or more memories) The body plane can be formed on a dielectric layer formed on the substrate layers. A top row decoder circuit 380, a top data bus 373 and a top bit line selection block 381. Between the six array blocks of the rack and retreating from the top of each array block The bit lines are associated. A bottom row decoder circuit 379, a bottom data bus 378 and a bottom bit line selection block 382 span the 16 array blocks of the rack and exit with the bits from the bottom of each array block. Line associated. It should be understood that the top row decoder circuit 38 can be illustrated as being "above" in the array area, and the bottom row decoder circuit 379 can be illustrated as being under the array. Reflects the orientation of the circuit blocks shown in the diagram. Such locations may also be described as "on one side," and on the opposite side of the array of blocks (although this generally implies a horizontal substrate for the integrated circuit on which the electrical circuit is implemented). In addition, directional terminology "North, &"South" are convenient terms used to illustrate the positional relationship of various circuit blocks. In contrast, in certain embodiments, a memory array can be formed on a substrate "above" 'And the various circuit blocks are described as being in the memory array, below''. As used herein, in the substrate or a memory array block (all of which are 123178.doc 1345787 generally have a planar nature of the physical structure) The above "above" or "below" is relative to a surface perpendicular to such a substrate or memory plane. In Figure 14 'although the bottom row decoding can be described as being in the array block In the following, such a row decoder is not necessarily below the memory array (ie, closer to the substrate). In contrast, it can be assumed that it is within the array block boundary and is described as being below the array block " "or, Under " induction of such amplifier block (labeled SA), and the physical location to deliver such structural relationship. in

In the context of this specification and the various figures, it should be clear that the above "and, below," are used. In a particular exemplary embodiment, the bit line decoder is a 16-bit decoder that simultaneously selects a 16-bit line on the top side of a selected memory array block. This "select" involves row decoding, which does not imply that all 16-bit lines are actually stylized at the same time. Preferably, the sixteen selected bit lines are arranged on each of the four bit line layers to exit the four adjacent bit lines of the array at the top (or at the bottom of other decoders).

The sixteen 1/〇 lines of the top data bus 373 traverse all of the sixteen blocks horizontally. Such a bus bar corresponds to the above SELB bus bar. This data bus 373 is connected to each of the bus bars (4) of the individual bus bars to one of the sixteen sense amplifier circuits distributed in the sixteen blocks shown: otherwise. The data bus lines of the sixteen data bus lines can also be operated: two: a related bias circuit (ie, a reset circuit), which can be -specific, etc.; Etc. "Selected" The 16-bit line is based on the I-line. For example, 'for a reset operation mode, this reset circuit"; the data bits of the bit lines of the 16-bit lines, and also allows the simultaneous stylized bits according to 123178.doc 41 丄Μ)/87 The number of lines (which of course means that the programmatic unit that is lightly connected to a particular bit line) is appropriately biased to "select" the desired bit line in the 16-bit it line and the undesired stylized bits. The bias line can be deactivated and caused to exhibit during the read mode of operation when the selected bit line is lighted to the individual sense amplifier by means of the data bus 373 (ie, the SELB bus) A high impedance.

The sixteen 1/〇 lines of the bottom data bus 378 traverse all of the sixteen blocks horizontally. Such a bus bar corresponds to the other bus bar stream described above, which is used for the bit line exiting at the bottom of the array (it should be remembered that the bit line system is 2:1 interleaved). As described above, each of the bus bars of the individual bus bars of the data bus 378 is coupled to the _ individual of the ten sense amplifier circuits distributed in the sixteen blocks shown. In the group of blocks (ie, the machine wood), there are 32 inductive amplifications connected to 32 selected positioning elements. In the reading mode, all of the selected positioning elements can be configured to fall into such The N-blocks of the sixteen blocks can be additionally configured. As will be said here, a sense amplifier such as a moon can be conveniently implemented under the memory array block. However, the data bus lines 373, the claws, the sixteen header selection decoders (ie, the bit line selection blocks 381, 382), and a small portion of the row decoders 379 380 are preferably a preferred system. Implemented outside the array block. Additional details of the configuration of the splicing decoder can be found in U.S. Patent Application Serial No. U.S. Patent Application Serial No. U.S. Patent No. 7, s. In a stylized mode, the total number of stylized circuits can limit the number of simultaneous hidden units. In addition, the number of stylized currents flowing in the line can also limit the number of memory cells, which can be reliably programmed at the same time. In the exemplary architecture shown, if two row decoders select bit lines within the same array block, then an array block selects a total of 32 bit lines. Suppose each decoder selects four bit lines (ie, four bits from each memory plane) from each of the four bit line layers'. The selected word line segment on each memory plane is required. Supports stylized currents for ~ eight selected memory cells. (See Figure 13 to show individual wordline segments for each layer.) The four memory banks of the selected memory cells are associated with the northbound exit bitline, while the other four selected memory cells are oriented. The south exit bit line is associated. All 32 cells of the selected memory cells will be driven by the same word line driver circuit, but each memory cell of the selected memory cells is driven by its own bit line driver circuit. As the above is dark, even if the total stylized current for 32 cells can be supplied by the integrated circuit, the programmed current for the 8 selected memory cells can cause the selected word line segments on each layer to cause a Unacceptable Voltage Drop In addition, the s-selected word line driver circuit may not be able to drive this type of current using a receivable voltage drop. In the reset stylized mode, a reverse bias is applied to each of the selected passive memory cells, thereby resetting the modifiable resistive material to a high resistance state to program the user data. One or more bit lines within the block may be selected for simultaneous programming, and flow from the selected bit line to the bit as some bits of the bit are reset to a more resistive state The electrical μ of the selected word line is significantly reduced, and the remaining bits see a significantly higher voltage of 123178.doc -43 - 1345787 due to the reduced word line drop. Thus, it is easier to stylize the bits to change state first, so that the more "stubborn" bits see a slightly higher voltage to help stylize such bits. Nonetheless, having 32 selected memory cells residing within the same array block may be unacceptable for any of the above reasons. Therefore, two different array blocks can be selected for stylization, each using one of the two data busses. In the figure, array block 374 is cross-hatched to indicate its choice to reset the stylization. One of the outputs of the top row decoder 380 for block 374 is active, thereby coupling the 16 selected positioning element lines to the top data bus 373 (indicated by the arrows from array block 374 to data bus 373) The array block 375 is cross-hatched to indicate its selection for resetting the stylization. One of the output of the bottom row decoder 3 79 for block 3 75 is also valid, thereby selecting 16 The bit lines are coupled to a bottom data bus 378 (represented by arrows from array block 375 to data bus 378.) A single column 377 is by the global column decoders on either side of the memory array. (not shown) is selected which drives a global column select line across the entire strip 371. Such a global column select line corresponds to the decode wheel 1 58 of the column decoder circuit shown in Figure 9. A multi-word line The driver circuit is enabled (by appropriate bias conditions on its source select bus and reverse source select bus) to drive a selected word line 3 76 within block 374 and within block 3 75 Selecting the scorpion line ° due to sharing in this exemplary embodiment The sub-lines are such that the selected word line driver circuit drives the word lines in the two blocks 374, 3 75. The entire programmed current is still driven through the selected word line.

The peak current will be approximately half. By selecting to configure the data page in a more complex block configuration corresponding to an odd or even sub-line, the duplexer circuit can be completely avoided and initiated, but now the current along each selected word line segment is halved to each word line. The clip now only supports 4 selected memory units. The word line driver should be noted. For example, assume that an even word line is driven from the left side of a given array block and an odd word line is driven from the right side of a given array block. When an even word line is selected within a given array block, the block to its left can be selected at the same time, and when an odd word line is selected within a given array block, the block to the right can be selected at the same time. In this case, no selected word lines appear in an unselected array block. In an alternate embodiment, the data page to be written can be configured to avoid sharing the word line driver. In the dual data bus example described above, each memory block is associated with two data bus bars 373, 378. In a different memory loop, other bit lines associated with array block 374 will be coupled to bottom data bus 378' and other bit lines associated with array block 375 will be coupled to the top data bus 373 » In this and other embodiments, to optimize performance, the blocks selected for reading in a given rack are different than the blocks selected for reset. A single block is selected for reading at a time, but two blocks are selected for reset. Both data busses are valid for reading, but accessing a single block is different from resetting the above. There are various other dual data bus configurations that offer similar benefits. Figure 15 shows a memory rack 400 in which the odd-numbered memory blocks are only associated with a first data bus of 123178.doc • 45· 1345787, and the even-numbered memory blocks are only one The second data bus is associated. The odd array block 4〇6 is associated with the first data bus bar 402, which is represented as a bit line selection block 4〇8, and the even array block block 407 is associated with the second data bus bar 4〇4. Union. The two memory array blocks (e.g., array blocks 406, 407) are simultaneously selected, each coupling its selected location line to one of the data bus bars (denoted as individual bold arrows 410, 412). Figure 16 shows a memory rack 420 in which each memory block is associated with a first data bus 422 and a second data bus 424. In a memory cycle, the first array block 426 is selected and its selected bit line is lightly coupled (bold arrow 430) to the first data bus 422, while the second array block 427 is simultaneously selected. The selected meta-line coupling (bold arrow 43 2) is selected to the second data bus 424. In another memory loop, the first array block 426 can be selected and its selected positional line coupled to the second data bus 424, while the second array block 427 is simultaneously selected and positioned to locate the element line The first data bus 422 is connected. Figure 17 shows a memory rack 440' in which each memory block is associated with a first data bus 442 and a second data bus 444, all located on the same side of the array block. . The first array block 446 is associated with the first data bus 442 by a first bit line selection block 449 and is also associated with the second data bus by a second bit line selection block 448. 444. In the exemplary memory cycle shown, two memory array blocks (e.g., array blocks 447, 446) are simultaneously selected, each coupling its selected location line to the first and second data streams. Rows 442, 123178.doc -46· 1345787 444 (represented as individual bold arrows 450, 454). Referring now to Figure 18, a memory bay 460 is illustrated which is similar to the memory bay BAY described above, except that in this exemplary embodiment, two simultaneous select array blocks 462, 4 64 are not Adjacent. In an array of memory blocks, the array block 462 is selected and positioned to be coupled by a meta-line (ie, bold arrow) to the upper data bus 466, while the array block 464 is simultaneously selected and positioned. The meta-line is coupled to the lower data bus 468. This organization is particularly useful when the word lines are not shared between adjacent memory array blocks, but can be used even if such word lines are shared. In this case, a selected word line within a selected block will also extend into the adjacent memory block. In the specific embodiments of the illustrated embodiments, more than one block is selected for resetting the stylization. A reverse bias is applied to the passive component cells within the selected array block (ie, selected "sub-array"), thereby resetting the modifiable resistive material to a high resistance state to Stylized within the array. This can be done at high bandwidth for several reasons. First, by selecting more than one block for stylization, the number of simultaneous programmed memory cells can be increased beyond what is imposed by a given wordline segment or even imposed by a given wordline driver circuit. More than two selected array blocks can be selected as long as the data bus arrives at each such block. In addition, this stylized orientation helps to program a larger number of cells. In other words, since some bits of the stylized bits are reset to a higher resistance state, the amount of current flowing from the bit line to the word line is significantly reduced, so the winning residual bit is due to the decreasing word line voltage drop. And see a slightly higher voltage. For 123178.doc •47– 1345787, the maximum stylized current at σ疋 may reliably program more bits from low to high resistance than high to low resistance. It also contributes to the high bandwidth programming of these bias conditions on a large number of unselected word lines and bit lines. Since the lines are all kept grounded, there is no large delay associated with boosting the unselected array arrays when selecting and deselecting the array blocks, nor is there an array that must accommodate the rising and falling biases. Large current transient current of the block. It should be noted that in this reset stylized configuration, even in the selected memory block (4), the (4) word line and bit line dust are grounded (ie, float to the left when using a specific exemplary decoder structure) In a specific embodiment, a memory chip can be organized such that each rack has its own read write circuit group and at least one data bus that connects the read/write circuit to the bit 7L line select circuit. This bus bar extends across the width of the rack, or in other words, a "crossover" block group. There may be a row of decoders on the top side of the blocks and a number on the bottom side of the blocks. Two rows of decoders, so there are two data buss. In a particular embodiment, there may be two sets of read write circuits associated with individual data busses. Preferably, a particular data page is spread to All racks achieve the highest bandwidth. This is described in the exemplary embodiment shown in Figure 14 by a pair of selected array blocks within each memory bay.疋 疋 系 is distributed in a rack The two blocks have '-blocks with bit lines selected by the row decoders and associated with one of the data bus banks, and the second block is composed of another row of decoders and data busses To select 'Make bandwidth per rack' but the current flowing in any of the wordline segments is the same. In addition, at the same row position, the 123178.doc • 48-1345787 兀 line - or many of them simultaneously Selected for resetting the stylization. At the same time, the number of stylized may be limited by the current flowing from the selected bit line to the common word line from the block (4). However, this limitation is mitigated in the method, Some bits of the bit are reset to a higher resistance state, and the current reduction by 'reset " cell decreases' decreases along the ir of the common word line segment, and the remaining bits get more voltage Promote its resetting. In each selected block (4), the word lines are better (4) all on the same column, so 4 is divided by the decoding implication, because the global column decoder current does not need to change to support this point. Etc. simultaneously select the adjacent blocks, especially adjacent The word lines are shared between the blocks. The decoding is configurable such that for any selected word line shared between two adjacent blocks, the two adjacent array blocks can be configured to simultaneously select the array A block, for example, a given word line driver placed between the second and second blocks drives a common word line within the first and second blocks (both simultaneously selected). The lines (assuming they are in the 2: 丨 interleaved form on the left and right sides of the array blocks) will be driven by an array of line drivers between the second and third array blocks, which may also be The array block is selected. This avoids processing the selected word line into the adjacent non-selected array block. When using the reset stylization, each memory unit is set back to one by the "set" operating mode. Low resistance state, this set mode of operation can be used to rewrite new data' or erase a group by applying forward bias to one bit at a time, or by arranging many bits in a data page or a erase block Bit. High performance erasure can be obtained by selecting a plurality of bit lines or a plurality of word lines in a block and setting the cells to a low resistance. Within the bit driver path 123178.doc •49- 丄:545787 (4): The circuit limits the total current flowing to the common word line. Depends on the selected record

Recall that the body level 7C technology, and the relative number of set currents and reset currents, and the number of shallow leakage currents in the U unit can be used to set or erase operations by selecting fewer blocks for reset (ie, stylized). The choice of the resistive material is to form a diode polycrystalline germanium material. An anti-fuse ("AF") can be serialized with a polycrystalline dipole, and the anti-fault is hopped prior to the stylization event during the manufacturing-formatting step. This inverse (4) is used to limit the maximum current that the cell conducts when it is set. Preferably, the memory array comprises a segmented word line architecture (as shown in Figures 12 and 13), and preferably a three-dimensional array. In a particular embodiment, the word line system is associated with a bit line on a single bit π line layer, and in a particular embodiment, in a particular embodiment, In a semi-mirror configuration, the word lines on a given word line layer are between two 7L line layers (ie, a single word line layer and a two bit line layer defining two memory planes). The sharing of such a memory array structure is further described in the aforementioned U.S. Patent No. 6,879,505. At this point, the description of the various decoder circuits has focused primarily on a single array block. It should be recalled that each decoder has a background selection bus and, for some embodiments, a reverse source selection bus. Explain below. The word line decoding level can be considered relatively straightforward. The source select bus and the unselected bias line or the reverse source select bus are decoded based on the address information and driven according to which array block is active. References to similar column decoding circuits have been made elsewhere herein. The (etc.) individual source select bus and/or unselected bias line i23178.doc • 50· 1345787 for the word line associated with the unselected array block may be floated to the left. With respect to the row decoder configurations, a hierarchical bus configuration can be used to provide efficient routing of read/write data and effective biasing of bit lines within selected and unselected array blocks. A useful hierarchical bus configuration will be described in the context of the dual source select bus decoder shown in Figures 9 and 10, but these configurations are applicable to other decoder embodiments.

In the forward operation (read and set), an exemplary hierarchical bus arrangement provides an appropriate bias voltage on the SELN bus for a selected array block and SELN of the unselected array block. The bus bar floats. This helps to reduce the undesirable power consumption in the array blocks within a selected one of the selected array blocks. The unselected word lines in the selected array block are biased at a relatively high voltage VUX (e.g., VPP_VT), and under a common word line, the $# unselected word lines also extend to adjacent The array blocks are not selected (i.e., the half of the word lines in the unselected column block are shared with the selected array.. block). Preferably, the unselected locating elements within the adjacent array block are offset by the unselected locating element line VUB (e.g., ντ). This is a waste of power due to leakage current through unselected memory cells. The other half of the word lines in the adjacent unselected column blocks cause the leakage to the voltage, so the leakage power is minimized for half of the word lines. Early in the reset mode of operation to reach in the array area The exemplary hierarchical bus configuration is also a longer SELN path that spans the reset data drivers distributed under the plurality of block blocks. The four exemplary hierarchical bus configuration are described in the next four figures. Now, 123178.doc 51 1345787, a busbar configuration 500 is described with reference to FIG. 1, which includes three memory array blocks 502, 504, 506 that represent all of the array blocks within a rack. Although only three array blocks are shown, the incremental nature of the configuration and its extensibility to the number of any array block should be clear. A separate SELN bus segment for each of the array blocks is displayed. As used herein, a busbar segment is only one busbar that is smaller than other such busbars, while in other embodiments (described below), multiple busbar segments can be coupled together to form a single larger confluence. row.

In the set mode, the SELN busbar segments for a selected array block are coupled to a longer GSELN busbar that spans the entire memory bank by a coupling circuit 508. This coupling circuit 508 can be as simple as 16 transistors, each coupling a different SELN bus line to an individual GSELN bus line. This coupling circuit 508 is enabled by a control signal EN_GSELN which is active for the selected array block (described below) in the set mode or in the reset mode. During this set mode, the GSELN busbar is coupled to the unselected location line voltage VUB (i.e., the busbar lines of the GSELN bus are coupled to this voltage). The individual EN_GSELN control signals for the unselected array blocks are active, and the individual coupling circuits 508 are turned off, thereby allowing individual SELN bus segments to float as needed. In the reset mode, individual EN_GSELN control signals for all of the array blocks are active, and individual coupling circuits 508 are turned on to couple individual SELN bus bars to the GSELN bus. This point provides write data to all array blocks, regardless of which block is selected. The SELB bus is driven to the VUX voltage (e.g., ground) to provide an unselected positioning element bias condition 123178.doc -52- 1345787 to reset the stylization.

This is a relatively simple circuit configuration, requiring only an additional 16 global lines (GSELN) and 16 additional transistors per array block (coupling circuit 508). Disadvantages (at least with respect to other embodiments described below) include a relatively high capacitance on both the SELB and SELN busbars. The capacitance on the SELB bus is always present, but only during a read cycle, and when all of the SELN bus segments are coupled to the global bus GSELN, the combined bus transfers are reset during this time. Data information, the higher capacitance on the SELN bus has 0 during the reset mode. In certain other embodiments, the reset mode can be configured with the entire non-negative voltage without dividing the reset voltage VRR into -VRR/2 and + VRR/2. In this case, the unselected word lines and bit lines are biased at the midpoint (now VRR/2). Therefore, when coming out of the reset mode, the discharge rate of the lines should be carefully controlled to avoid excessive current surges during discharge.

Referring now to Figure 20, another embodiment is described in which the individual SELN busbar segments are coupled together to form a single larger busbar that spans the entire memory bay. In the set mode, the SELN bus for a selected array block is coupled to a single bias line VUB by a coupling circuit 532 that spans the entire memory frame. The coupling circuit 532 can be as simple as 16 transistors, each coupling a different SELN bus bar to the VUB bias line (which is coupled to a suitable bias circuit, as shown). The coupling circuit 532 is enabled by a control signal BLATVUB that is active for the selected array block when in the set mode. For the unselected array regions 123178.doc -53 - 1345787, the individual BLATVUB control signals are disabled and the individual coupling circuits 532 are turned off, thus allowing individual SELN bus segments to float as needed.

In the reset mode, the SELB bus is driven to the VUB voltage (e.g., ground) to provide an unselected positioning element bias condition for resetting the stylization. Moreover, the individual SELN busbar segments are coupled by a coupling circuit 533 to form a single busbar spanning the entire memory frame, the memory chassis being coupled to the reset circuit for the combination The bus provides reset information. One of the SELN busbar segments can be coupled to the reset circuit by busbar 536. In a particular embodiment, a coupling circuit 535 can be used to provide a connection to the reset block in RESET mode. This is a relatively simple circuit configuration in which only one additional bias line (VUB) and 32 additional transistors are required per array block (the coupling circuits 532, 53 3). Similar to the previous embodiment, there is still a relatively high capacitance on the two SELB and SELN busbars.

Referring now to Figure 21, a bus arrangement 550 is described which incorporates features from two prior embodiments. In SET mode, the SELN bus segment for a selected array block is coupled to a VUB bias line across the entire memory frame by a coupling circuit 554, which is coupled to a control signal BLATVUB. Come to enable. The individual BLATVUB control signals for the unselected array blocks are invalid, and the individual coupling circuits 554 are turned off, thus floating individual SELN bus segments as needed (since the EN_GSELN signal is also inactive in SET mode). In the reset mode, the individual EN_GSELN control signals for a selected array block are active, so a separate coupling circuit 552 is turned on to couple the individual 123178.doc - 54 - 1345787 SELN bus segments to the GSELN bus. The individual EN_GSELN control signals for the unselected array blocks are invalid, and the individual coupling circuits 552 are turned off, thereby causing individual SELN bus segments to float. This configuration only provides write data to this (etc.) unselected array block, which significantly reduces the total capacitance. The SELB bus is driven to the VUX voltage (e. g., ground) to provide unselected positioning element bias conditions for reset stylization.

This circuit configuration requires 17 additional lines (VUB bus and GSELN bus) and 32 additional transistors for each array block (the coupling circuits 552, 554). Unlike these prior embodiments, this configuration provides for significantly reducing the capacitance on the SELN bus, since the individual SELN bus segments for unselected array blocks are not coupled to the GSELN bus. There is still a fairly high capacitance on the SELB bus.

Figure 22 depicts another hierarchical bus arrangement, this time using only a single global selection bus GSEL across the memory frame and dividing the SELB bus into a separate SELB bus segment for each array block. For a selected array block, individual SELB busses or individual SELN bus segments are coupled to the GSEL bus. During the SET mode, the selected block SELB busbar segment is coupled to the GSEL busbar, and the selected block SELN busbar segment is coupled to the VDSEL. bias line (which delivers an appropriate bias during SET) The unselected positioning element line bias condition VUB generated by the path, as shown). The unselected block SELN bus is floated to the left. During the RESET mode, the selected block SELN busbar segment is coupled to the GSEL busbar, and the selected block SELB busbar segment is coupled to the VDSEL bias line (at RESET) It passes the unselected positioning element line bias condition VUX). The unselected block SELN bus is again floated to the left.

This configuration is the most complex of the described configurations, requiring 17 global lines per array block (ie, spanning the memory rack) and 64 additional transistors, and may require more in some embodiments. Layout area. However, it also provides low capacitance on the SELB and SELN busbars because it allows for higher efficiency and provides a one-pole modular block design. Moreover, larger memory racks can be implemented without significantly increasing the capacitance on the SELB and SELN busbars. In another embodiment, the row decoder circuits can be modified to provide a separate row decode output for the NMOS and PMOS transistors of the bit line driver circuit, so that the bit line selector can be set at In high impedance state. However, this configuration will significantly increase the bit line selector area as well as its own row decoder.

Referring now to Figure 23, a data circuit is illustrated that includes separate blocks for the set, reset, and read modes. It will be recalled that in the reverse bias mode (i.e., reset mode), the selected positioning elements are coupled to a different SELN bus line (i.e., the reverse source select bus). Here, a reset driver 615 is found coupled to the SELN bus 617 (which indicates that the path to the SELN bus can be used using any of the four hierarchical bus configurations). Essentially, this represents the path that is ultimately coupled to the SELN bus segment for a selected array block. The information to be written is received by the I/O logic 601, passed on the bus 602 to a write latch block 604, and 123178.doc -56-1345787 is passed on the bus 607 to the control logic 608. Control logic then controls reset driver 615 by means of control line 612. It should be remembered that in this forward mode, the selected positioning elements are coupled to an individual SELB bus line. Since the two SET and READ modes utilize the forward bias mode, the set driver 614 and the read sense amplifier 613 are simultaneously coupled to the SELB bus 616 (which is representative of any of the above four hierarchical bus configurations). Or any other configuration to the path of the SELB bus). The sensing data is passed from bus 609 to a read latch 605' which is passed from bus 603 to I/O logic 601. Various bus bars 606, 610, and 611 are provided for a stylized control loop, sometimes referred to as a smart write, which turns off the programmed current when a one-element system successfully transitions or sets. The bus banks also provide a pre-write read capability to determine, for example, any previous stylized states (e.g., LSB data bits) that should be retained prior to a subsequent stylized operation. Such capabilities are further described in the 023-0049 and 023-0055 references below. One representation of a simplified exemplary reset driver 615 and a word line and bit line select path to a selected memory cell 638 is depicted in FIG. A word line select path 639 represents the path through the word line driver circuit (i.e., the decoder head) to the circuitry used to generate the decoded source select bus XSELN. A one π line select path 636 represents the path through the bit line driver circuit and through any of the coupling circuits (e.g., the circuits described in the various hierarchical bus arrangement embodiments) to the individual SELN bus bars 635. A preferred reset method and associated reset driver are described in the sand-〇i114USO and SAND_01114USlf references below, with particular reference to Figure 13 of 123178.doc • 57·. The capacitance of the bit line selection path is precharged before attempting to program a new address selection location line. This can be performed using a higher current than the amount required to actually reset the selected memory cell, but at the appropriate timing, such higher amounts of pre-charging can speed up the pre-charge time without a decisive influence on the memory cells. This precharge is controlled by a precharge line signal PCHGCOL that is passed on control signal 637 to bit line select path 636. A one-line precharge (BLP) current limit circuit 633 and a reset limit circuit 634 are simultaneously provided to control the number of upper bits of the individual bit line precharge and reset current. If the data is such that no reset operation is required, both are stopped by signal 632 and the SELN bus bar 635 floats. Conversely, if the data causes the memory cell to be reset, the disable line 632 is inactive and the BLp current limit circuit 633 is enabled temporarily (e.g., 200 ns to 500 ns) to provide a higher level of control current for such a Pre-charging, which is then disabled (by a control signal not shown), causes reset current limiting circuit 634 to supply a lower amount of current for resetting the selected memory cell. Since resetting a memory cell causes its m resistance state to become a higher resistance state, it is rarely necessary to perform the inductive reset operation and disable the reset limit. Since the cell automatically turns off when it reaches the reset state. As with the various embodiments described above, many types of memory cells can be programmed using a reverse bias (e.g., the reset mode described above). Such a unit includes a passive component unit having a metal oxide (e.g., a transition metal oxide) and a ?-tano A? Other suitable units include a resistor material in a two-body matrix. Examples include a programmable 123178.doc • 58-1345787 metallized connection, a phase change resistor (eg GST material), an organic material variable resistor, a composite metal oxide, a carbon polymer film, a The doped sulfide glass and a Schottky barrier diode containing a migrating atom to change the electrical resistance. The selected resistive material can provide one-time programmable (OTP) memory cells or multiple: under write memory cells. In addition, it is possible to use a day-to-day polar body with a reverse bias stress modified conduction. A useful memory unit for the reverse reset operation is described in U.S. Patent No. 6,952, 3, issued to s. U.S. Application No. U/237,167, filed on Jan. 5, 1989, to the name of &quot;Using a Memory Unit with Switchable Semiconductor Memory Element with Trimmer Resistors&quot; U.S. Patent Application Publication No. 2007-0090425, issued April 26, 2007. A suitable metal oxide memory cell system is shown on March 31, 2006. Brad Hernert, U.S. Application Serial No. 11/394,903 No., entitled "Multilayer Non-Volatile Memory Cell with Resistivity Switching Oxide or Nitride and Anti-Refined Wire". A suitable memory cell system using a phase change material that provides multiple resistance states is shown in R U.S. Patent Application Publication No. 2,5,158,950 issued to Scheuedein et al., entitled &quot;Non-volatile memory cells comprising a dielectric layer and a phase change material. The entire contents of each of the above-referenced publications are hereby incorporated by reference. Other exemplary memory cells having a transition metal oxide (eg, including such oxides having junctions) and exemplary cells in which the polysilicon material of the steering element itself comprises a switchable resistive material are described below. In the 163-1 application. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A unit of a useful rewritable memory unit incorporating a tantalum oxide (nickel oxide) incorporated into a diode, published as US Patent Application Publication No. 2006-0250836, issued Dec. 9, 2006. The resistance of the memory cell can be switched from low to high and from high to low resistance. S. Brad Herner et al., U.S. Application Serial No. 11/395,995, filed on March 31, 2006, A non-volatile memory unit of a diode and a resistor-switching material is disclosed in US Patent Application Publication No. 2006-0250837, issued on Nov. 9, 2006, which discloses the use of a multi-layer memory unit. Forward bias is set and reset using a reverse bias. The entire contents of each of the above-referenced publications are hereby incorporated by reference. In many of the embodiments described herein, the precise bias conditions imposed on each individual bus bar within the data path are independently controlled. The specific voltage and current settings for each of these drivers for setting and resetting the drive can be adjusted for each element of the data path. Thus, a particular memory unit (i.e., "multi-layer" memory unit) having more than two states is contemplated for use with the many structures described herein. Exemplary multi-layer memory cells are described in the aforementioned U.S. Application Serial Nos. 11/23,167, and MA-163-1. Exemplary passive element memory cells and associated non-volatile memory structures that can be used in the practice of the present invention are described in the following documents, the entire contents of each of which are hereby incorporated herein by reference: Titled "Vertical Stacking Fields, Programmable Non-Volatile Memory and Manufacturing Methods," awarded Mark GJ〇hns〇n et al; US Patent No. 6,420,215, entitled &quot;Three-Dimensional Memory Arrays and Manufacturing Methods&quot; N. Johan Knall et al.; U.S. Patent No. 6,525,953, entitled &quot;Vertical Stacking Field Programmable Non-Volatile Memory and Manufacturing Method&quot;, to Mark J〇hns〇n et al; U.S. Patent No. 6,490,218, Titled &quot;Su will be a memory method and system&quot; for storing multi-bit digital data, awarded to Michael Vyv〇da et al; US Patent No. 6,952,043, entitled 'Electrical Insulation Columns in Active Devices&quot;; 'given to Michael Vyvoda et al; and US Patent Application Bulletin No. US 2005-0052915, entitled ', with 13⁄4 and the first resistive state without dielectric reverse dissolution The non-volatile memory unit &quot;, filed by S · Brad Herner et al. The following applications (each filed during the same period) describe the memory cell structures, circuits, systems, and methods that can be used to implement the present invention, and the entire contents of each application are hereby incorporated by reference: U.S. Application No. 11/496,985 (Attorney) File No. 10519_141), titled &quot;Multipurpose Memory Unit and Memory Array&quot;, by R〇y

Application by Scheuerlein and Tanmay Kumar (&quot;10519-141&quot;Application); US Application No. 11/496,984 (Attorney Docket No. 10519-1 50), titled • Multi-Purpose Memory Units and Methods of Using Memory Arrays &quot;, by

Roy Scheuerlein and Tanmay Kumar apply (&quot;10519-150&quot; application 123178.doc -61 - 1345787 case); US application No. 11/496,874 (lawyer file number 10519-142), labeled &quot; mixed use memory early "" applied by Roy Scheuerlein (&quot;10519-142&quot;application); US application No. 11/496,983 (attorney file number 1〇519-151), titled &quot;How to use mixed-use memory unit&quot; Application by R〇y Scheuerlein (&quot;105 19-151&quot;Application); US Application No. 11/496,870 (Attorney Docket No. 10519-149), titled &quot; Mixed-use memory with different data status Unit &quot;, by R〇y

Scheuerlein and Christopher Petti apply (&quot;i〇519-149&quot;application); US application No. 11M97,021 (lawyer file number 1〇519-152), titled &quot; mixed-use memory with different data status How to use the unit &quot;'Application by Roy Scheuerlein and Christopher Petti (&quot;105 19· 152&quot;Application); US Application No. 11/461,393 (Attorney File No. SAND-01114US0), titled &quot;Non-volatile Controlled Pulse Operation in Sexual Memory&quot;, filed by R〇y Scheuerlein (&quot;SAND-01114US0&quot;Application); US Application No. 11/461,399 (Lawyer File No. Lv Baxian - 01114US1) 'Title For &quot;System for Controlled Pulse Operation in Non-Volatile Memory?' Application by Roy Scheuerlein (&quot;SAND-01114US 1&quot;Application); US Application No. 11/461,410 (Attorney File No. 8 8 rib) -01115US0) 'Title is &quot;High-bandwidth primary field programmable memory' ' 123178.doc -62- 1345787 Requested by Roy Scheuerlein and Christopher J. Petti (&quot;SAND- O1115US0&quot; Application) US Application No. 11/461,419 (Lawyer's Case No. Lv8 (10)-0111 5US 1) 'Title for &quot;System for High-Bandwidth One-Time Programmable Memory&quot;, by Roy Scheuerlein and Christopher J. Petti Application (&quot;SAND-01115US1" Application); US Application No. 11/461,424 (Attorney File No. Lv8-01-01US0) 'Title for &quot; Reverse bias in non-volatile memory Pressure fine-tuning operation &quot; 'Apply by Roy Scheuerlein and Tanmay Kumar (&quot;SAND-01117US0&quot;application); US application No. 11/461,431 (lawyer file number 3·8-1111 7US 1), entitled " A system for reverse bias trimming 4 in non-volatile memory' application by Roy Scheuerlein and Tanmay Kumar (&quot;SAND-01117US1&quot;application); US application No. 11/496,986 (lawyer file number ΜΑ -163-1), titled "Using Method for Having a Switchable Semiconductor Memory Component with Trimmerable Resistor", by "Tanmay Kumar, S. Brad"

Application by Herner, Roy E. Scheuerlein and Christopher J. Petti (&quot;MA-163-1&quot;Application); US Application No. 11/461,339 (Attorney Docket No. 023-0048), titled Inverse Passive component memory array for polar word lines and bit line decimators, applied by Luca G. Fasoli, Christopher J. Petti and Roy E. Scheuerlein (&quot;023-0048&quot;application); US application II/461,364 (Attorney Docket No. 023-0054), Title 123178.doc -63 · 1345787 is a method of using a passive element memory array incorporating a reverse polarity word line and a bit line decoder &quot; , applied by Luca G. Fasoli, Christopher J. Petti and Roy E. Scheuerlein (&quot;023-0054&quot;application); US application No. 1 l/46i, 343 (lawyer file number 〇〇23_〇〇49 ), titled &quot;Device for reading a multi-layer passive element memory cell array, by Roy E. Scheuerlein, Tyler Thorp, and Luca G. Fasoli (&quot;023-0049&quot;application); US application Case No. 11/461,367 (Attorney File No. 023-0055), Title For &quot;method for reading a multi-layer passive element memory cell array&quot;, applied by Roy E. Scheuerlein, Tyler Thorp, and Luca G. Fasoli (&quot;023-0055&quot;application); US application 11/461, 352 (attorney file number 023-0051), entitled "Double Data Dependent Buss for Coupling Read/Write Circuits to Memory Arrays" by Roy E. Scheuerlein and Luca G. Fasoli application (&quot;023-0051&quot; in the case); US application No. 11/461,369 (attorney file number 023-0056), titled &quot; for coupling read/write circuits to memory arrays The application of the double data-dependent busbars, applied by Roy E. Scheuerlein and Luca G. Fasoli (&quot;023-0056&quot;application); US application No. 11/461, 3 59 (lawyer file number 023) -0052), titled &quot;Memory Array&quot; incorporated into the data bus block selection for memory array block selection, by Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti (&quot;023 -0052&quot;Applications; US Application No. 11/46, 37 No. 2 (Attorney Docket No. 023-0057), heading 123178.doc -64- 1345787 is "How to use the data bus for memory array block selection", by Roy E. Scheuerlein, Luca G. Fasoli and

Christopher J. Petti Application (&quot;023-0057&quot;Application); US Application No. 11/461,362 (Attorney Docket No. 023-0053), titled &quot; Hierarchical Position for Block Selectable Memory Array Yuan Line Biashui # &quot; » Application by Roy E. Scheuerlein and Luca G. Fasoli (&quot;023- 0〇53&quot;Application);

US Application No. 11/461,376 (Attorney File No. 023-0058), Title

For &quot;Method of using a hierarchical bit line bias bus for block selectable memory arrays&quot;, by Roy E. Scheuerlein &amp; Luca G

Fasoli applies (&quot;023-0058&quot; application). Personal r / r does not pay for example _ only redundant π - and the number of oysters

In the context of a bit example, for example, the number of decoded outputs, the number of decoder heads, the sum of the bus bars, the number of f-bus bars, the number of array blocks in a memory frame, and the memory bank The number. Other teachings that meet other design goals can be implemented using the teachings of this disclosure. It is clear that 'all of the conventional features of the embodiments described herein are not shown and described. Most memory array designs have a relatively high mean sentence. For example, 'usually every bit line includes the same number of memory unit lines, word lines, array blocks, and even memory plane ==2 - integer sub-screen (for example, 2V for decoding: and efficiency. But this Regularity or consistency: Of course, it is not required in the application. For example, on different layers of the heart = a different number of memory cells, the memory array can include _: 匕 』 』 0 dry two memories 123178.doc -65 - 1345787 Body plane, word line segments in the first and last array blocks may vary in memory cell number or bit line configuration and many other irregular changes in the general consistency of the memory array design It is different, unless expressly stated otherwise in the scope of the patent application, even if it is not described in the specific embodiments as described herein, such general rules should not be included in the meaning of any patent independent item. It should be understood that the indication is on the top, left, The bottom and right sides are only convenient explanatory terms for the four sides of a memory. The word line segments for a block can be implemented as a horizontally oriented inter-finger word line segment group for one area. Block The equipotential lines can be implemented as vertically oriented inter-finger bit line groups. Each word line or bit line group can be served by a different decoder/driver circuit and a different sensing circuit on the four sides of the array. As used herein, a column extends across the entire memory frame (if not across the entire strip) and includes a number of word lines. As used herein, &quot;generally spans multiple array blocks&quot; one bus or The line includes almost all of the array blocks 'e.g., spanning all but except the last block (for example, a given bus bar does not lightly match one of the last blocks). Such bus bars or lines can be placed on the array block side. Or can be placed above or below such a memory block (ie, in a direction perpendicular to a semiconductor substrate). As used herein, the selected positioning element is coupled to a first bus, meaning that Each such selected positioning element line is coupled to one of the first bus bars corresponding to the bus bar. As used herein, a word line (eg, including word line segments) and a bit line generally represent an orthogonal array line, and generally conforms to this One of the techniques Assume that the word line is driven at least during a read operation cycle and senses the bits 123I78.doc • 66 - 1345787. Also, as used herein, a &quot;global line, (e.g., a global selection line) is crossed Array lines of one of a plurality of memory blocks, but no specific inference should be drawn to imply that such global lines must span an entire memory array or substantially span an entire integrated circuit.

As used herein, a read/write circuit (eg, a set and read circuit) can be used for one or more data bits, and thus can be coupled to a single wire, or can include coupling to separate data. One of the bits of the data bus is separated from each of the bus lines by such a read/write circuit.

As used herein, a &quot;data bus&quot; or data bus&quot;fragment&quot; transmits information dependent information at least multiple times, but this need not always be the case. For example, such a-border bus can be used for a particular mode of operation. This type of data bus has the same partial information on the IL line. As used in this article, a &quot;global&quot; bus can span multiple array blocks, but does not have to span (or span) the entire Memory array. For example, such a global bus can span a memory rack without crossing an entire memory strip. When appropriate, a &quot;data circuit&quot; can include a read/write circuit, One or more or any combination of a set circuit, a reset circuit, a read circuit, or a stylized circuit. As used herein, a "line" (eg, a selected location line within an array block) is selected. Corresponding to such bit lines that are simultaneously selected by a multi-head decoder circuit and each coupled to a corresponding bus bar. Such bit lines may or may not be selected by the data or I/O circuitry to actually perform a given read, programmatic "•reset or erase operation. For example, if a 16-bit row decoder simultaneously selects and couples a 16-bit line to a given bus (eg, a seln bus), it covers no bit lines, one bit line, more than one 123178.doc • The 67. 1345787 bit line or all of the bit lines of the 16-bit line group can actually receive a quotient for the selected ambiguity of the given mode of operation, - no erroneous condition is selected. This piece, while the remaining bit line can receive 1... The row can be described as - "data dependent" in the other specific implementation, there may be more than one such, selected "bias condition" in a macro The secret t oil is late ^ w ,, ° 疋 疋 上 传递 , , , , , , , , , , , , , , , , , , , , , , , , , , As used herein, a passive array of memory devices includes a plurality of 2 terminals. The memory cells 7L' are each connected between an associated ( line (e.g., word line) disk and an associated Υ line (e.g., a bit line). Such a memory array can be a two dimensional (planar) array or can be a three dimensional array having more than one memory cell plane. Such memory cells have a non-linear conductivity in which the current in a reverse direction (e.g., from the cathode to the anode) is lower than the current in a forward direction. A passive component memory array can be a one-time programmable (i.e., write-once) memory array or a read/write (i.e., multiple write) memory array. Such a passive component memory array can be generally viewed as having a current steering element that directs current in a direction and another component capable of changing its state (eg, a fuse, an antifuse, a capacitor, a resistive component, etc.) ). When a memory component is selected, the stylized state of the memory component can be read by inductive current or voltage drop. The directionality of the various array lines in the various figures is only convenient for simplifying the description of the quadratic and parallel groups in the array. As used herein, an integrated circuit memory array is a single-slab integrated circuit structure rather than one or more integrated circuits packaged together or closely adjacent. The block diagram in the text can be used in the terminology of a single node connecting blocks. 123178.doc -68-1345787. Nonetheless, it should be understood that such &quot;node&quot; may actually represent one of the nodes used to convey a differential signal, or may be used to carry a number of related signals or for carrier formation when required by the background. A plurality of separate wires (eg, bus bars) of a plurality of signals of a digital word or other multi-bit signal. The system and physical structure are generally assumed, but it should be fully recognized that in modern semiconductor design and manufacturing, the physical structure and circuit can be used in subsequent design, test or manufacturing stages and the resulting computer-made integrated circuit can be used. Read the descriptive form to materialize. Thus, the assertion of a conventional circuit or structure conforms to its specific language 'can be understood as its computer readable code and representation, whether embedded in the medium or combined with a suitable reader to allow the manufacture and testing of the corresponding circuit and/or structure. Or the design is refined. The present invention also encompasses systems including circuits, package modules including such circuits, systems utilizing such circuits and/or modules and/or other memory devices, associated methods of operation, and methods for fabricating such circuits And computer-readable media codes for such circuits and methods, as described herein and as accompanying patent applications

The foregoing detailed description has only described many possible embodiments of the present invention.

system. 123178.doc -69- 1345787 Variations and modifications of this example without departing from the scope and spirit of the invention. It is only intended that the scope of the invention is defined by the scope of the claims, including all equivalents. Moreover, the above specific embodiments are explicitly intended to be used individually and in various combinations. Therefore, other specific embodiments, changes, and improvements described herein do not depart from the scope of the invention. [Simple description of the map]

The present invention will be understood by those skilled in the art, and many of its objects, features and advantages are apparent. 1 is a schematic diagram of a memory array illustrating selected and unselected word lines and bit lines, and exemplary bias conditions in a forward bias mode of operation. Figure 2 is a diagram showing an exemplary bias condition in a bias mode of operation of one of the memory arrays shown in Figure 1.

3 is an exemplary condition of a word line decoder circuit under voltage operating conditions. FIG. 4 is a schematic diagram of an exemplary condition of a word line decoder circuit under voltage operating conditions, including a schematic diagram in one Offset bias: Two include in the forward direction including a reverse direction including specific paradigm conditions for it. Excluding, for one of the specific 咏 decoder circuits, an exemplary condition under partial operating conditions. Figure 7 is a diagram of a word line decanter circuit illustrating his specific embodiment in one and Figure 8 is a one-line decoder circuit under-bias bias operating conditions open 123178.doc 1345787 other eight body examples An exemplary condition under a reverse bias operating condition. Figure 9 is a schematic diagram of a word line decoder circuit having dual decoded source select busses, including exemplary conditions for resetting the stylized reverse bias operating conditions. Figure 1 is a schematic diagram of a bit line decoder circuit having data dependent source select busses, including exemplary conditions for resetting stylized reverse bias operating conditions. Figure 11 is a block diagram depicting an exemplary integrated circuit including a three-dimensional memory array, and the integrated circuit includes a global column decoder on one side of the array and a pair at the top and bottom of the array simultaneously Line decoder. Figure 12 is a top plan view of a word (four) and a bit line layer of a three dimensional memory array in accordance with a particular embodiment of the present invention, showing a 2:1 interleaved word line &amp; The vertical connection of one half of the word line segments of the block is to the left of the block, and the vertical connection to the other half of the word line segments for the block is to the right of the block. In addition, word line segments from one of the two adjacent blocks share the vertical connections. Figure 13 is a three-dimensional diagram depicting a portion of a three-dimensional memory array in accordance with a particular embodiment of the embodiment of Figure 12, and illustrating the use of; adjacent word lines within each block of adjacent array blocks The segment-vertical junction box merges a word line driver circuit on each of the layers of the eclipse layer. Figure 14 is a block diagram of a memory array illustrating two memory banks each having two (or more) memory banks' and each of which houses a plurality of memory array blocks. Second, the column blocks are shown as being selected simultaneously, each of which individually couples its individual bit lines to one of the two data busses associated with the memory frame, 123178.doc .71 · 1345787. Figure 15 is a block diagram of a memory rack. Figure 1 shows that the other array blocks are selected simultaneously, each of which has its individual bit line (4) to the data bus associated with the memory rack. - Figure 16 is a block diagram of a memory rack illustrating another configuration: wherein two array blocks are displayed for simultaneous selection, each individually associated with the delta recall frame The second data bus - individual. Figure 17 is a block diagram of a frame of the memory frame to make another configuration, where - the array block system, shown as simultaneous selection, each of its individual bit line To the individual of the memory banks associated with the memory rack, the busbars are placed on the same side of the memory array block. / Figure 18 is a memory rack A block diagram illustrating another configuration in which two non-adjacent array blocks are shown as being simultaneously selected, each coupling its individual bit lines to a data bus associated with the memory rack - an individual 0 '

Figure 19 is a block diagram of a portion of a memory rack illustrating an exemplary hierarchical decoding configuration for providing appropriate conditions for selected and unselected array blocks on the source select busses. Figure 20 is a block diagram of one portion of a memory rack illustrating another exemplary hierarchical decoding configuration for providing suitable conditions on the source select busses for selected and unselected array blocks. Figure 21 is a block diagram of one portion of a memory rack illustrating another exemplary hierarchical decoding configuration for providing suitable conditions on the source select busses for selected and unselected array blocks. 123178.doc -72· 1345787 Figure 22 is a block diagram of one portion of a memory rack illustrating another exemplary hierarchical decoding configuration for providing appropriate conditions for selection and non-selection on the source select busses The array block is selected. Figure 23 is a block diagram of a data circuit including a read sense amplifier, a set driver, and a reset driver for various embodiments described herein. ^ Figure 24 is a block diagram of an exemplary reset circuit, including through a selection

«The reset path of the body unit and one of the word line and bit line selection paths Description D The same reference symbols are used in different drawings to indicate similar or identical items. [Main component symbol description] Example passive component memory array Passive component memory cell Word line

1〇〇101 102 103 104 105 106 107 108 152 153 154 155 Passive component memory cell word line passive component memory cell bit line passive component memory cell bit line column decoder power node power node output / node 123178. Doc -73- 1345787

156 Inverter 157 Multiplexer 158 Decode Output 159 Output 160 Inverter 161 Multiplexer 162 Decode Output 164 Node 167 Bus 168 Bus Bar 171 PMOS Transistor 172 NMOS Transistor 173 PMOS Transistor 174 NMOS Transistor 175 PMOS transistor 176 NMOS transistor 177 PMOS transistor 178 NMOS transistor 181 unselected word line 183 unselected word line 200 exemplary bias condition 202 row decoder 203 power node 204 power node -74- 123178.doc 1345787 205 output 206 Inverter 207 Multiplexer 208 Decode Output 209 Output 210 Inverter 211 Multiplexer 212 Decode Output 214 Node 217 Bus 218 Bus Bar 221 PMOS Transistor 222 PMOS Transistor 223 PMOS Transistor 224 NMOS Transistor 225 PMOS transistor 226 NMOS transistor 227 PMOS transistor 228 NMOS transistor 231 bit line 233 unselected location line 300 exemplary memory array 302 dual column decoder 304 dual column decoder -75- 123178.doc 1345787

306 Memory Array Block 308 Memory Array Block 310 Vertical Connection 312 Bit Line Circuit Block 314 Bit Line Circuit Block 315 Bit Line Circuit Block 316 Bit Line Circuit Block 318 Memory "Bar" 320 Memory "Bar" &quot; 322 bit line 324 bit line 332 memory block 333 bit line 334 memory block 335 bit line 336 word line segment 337 word line segment 338 word line segment 339 vertical connection 340 vertical connection 342 words Line segment 344 Vertical connection 352 Solution output 353 Decode output -76- 123178.doc 1345787 358 Vertical connection 359 Vertical connection 360 Word line segment 361 Word line segment 362 Word line segment 363 Word line segment 370 Memory array 371 First 372 Second strip 373 top data bus 374 memory array block 375 memory array block 376 selected word line 377 column 378 bottom data bus 379 bottom row decoder circuit 380 top row decoder circuit 381 top bit line selection region Block 382 bottom bit line selection block 400 memory rack 402 first data bus 404 second data sink Row 406 odd array block 407 even array block 123178.doc · 77· 1345787 408 bit line selection block 410 bold arrow 412 bold arrow 420 memory rack 422 data bus 424 second data bus 426 First Array Block 427 Second Array Block 430 Bold Arrow 432 Bold Arrow 440 Memory Rack 442 First Data Bus 444 Second Data Bus 446 First Array Block 447 Array Block 448 Second Place Element selection block 449 First bit line selection block 450 Bold arrow 454 Bold arrow 460 Memory frame 462 Array block 464 Array block 466 Upper data bus 468 Lower data bus 123178.doc -78 - 1345787

500 bus arrangement 502 memory array block 504 memory array block 506 memory array block 508 coupling circuit 532 coupling circuit 533 coupling circuit 535 coupling circuit 536 bus bar 550 bus bar configuration 552 coupling circuit 554 coupling circuit 601 I / O Logic 602 Bus 603 Bus 604 Write Latch Block 605 Read Latch 606 Bus 607 Bus 608 Control 609 Bus 610 Bus 611 Bus 612 Control Line 123178.doc -79· 1345787 613 Read Induction Amplifier Is 614 Set Driver 615 Reset Driver 616 SELB Bus 617 SELN Bus 632 Signal 633 Bit Line Precharge (BLP) Current Limit Circuit 634 Reset Limit Circuit 635 SELN Bus 636 Bit Line Selection Path 637 control signal 638 selected memory unit 639 word line selection path

123178.doc -80-

Claims (1)

1345787 ^月日修正换换页号 096128078 Patent application Chinese patent application scope replacement (March 1st) X. Patent application scope: 1* An integrated circuit comprising: a memory array having a plurality of array blocks, each of the array blocks comprising a word line and a bit line; - a first-global bus bar, which generally spans the plurality of array blocks, and is used for positioning the meta-line of the block Compatible with an individual data circuit; and a different first bus segment of each array block for biasing a first unselected positioning element line suitable for the first mode of operation during a first mode of operation The condition is passed to an unselected location line of a selected block, and a second unselected location line bias condition suitable for the first mode of operation is coupled to an unselected location line of the unselected array block. 2. The integrated circuit of claim 1, wherein: the first mode of operation comprises a set mode of operation; the first unselected bit line bias condition suitable for the first mode of operation comprises an unselected bit line a voltage; and the second unselected positioning element line bias condition suitable for the first mode of operation comprises a floating condition. 3. The integrated circuit of claim 1, wherein: in the second mode of operation, a selection </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> Bit line. 4. For the integrated circuit of Item 3, where: 123178-1000310.doc 1 曰Correct Replacement f The first global bus includes a coupling to one end of your/office 1 - item fetch / write circuit read Take/write bus. 5. The integrated circuit of claim 4, further comprising: - a second global bus that is coupled to the second data circuit; wherein each of the blocks includes - an individual consumable circuit for sometimes the individual A bus bar segment is lightly coupled to the second full king bus bar and sometimes floated. 6. The integrated circuit of claim 5, wherein: in the first mode of operation, the second global bus bar The sink line is biased under a first unselected positioning element line bias condition suitable for the first mode of operation; and in the second mode of operation, each bus line of the first-global bus bar is - Suitable for biasing the positioning mode under the bias condition of the second mode of operation. 7. The integrated circuit of claim 3, further comprising: a global bias line 'faced to a bias circuit; wherein each block includes a separate coupling circuit for sometimes the individual Each bus bar of a bus segment is coupled to the global bias line during which the global bias line delivers an unselected positioning element bias voltage suitable for the first mode of operation. 8. The integrated circuit of claim 7, further comprising: a plurality of stealing circuits for sometimes consuming the # individual first bus stop segments for the respective array blocks to form A single logical bus bar spanning one of the plurality of array blocks, the 123178-1000310.doc -2- first bus bar segment coupled together, ^. 9. The integrated circuit of claim 8, wherein: for each of the array blocks, the second operation of the chess period is combined with one individual first bus segment segment at 10. The integration of claim 8 a circuit, wherein: in the second mode of operation, each bus line of the first-to-global bus bar is biased at a voltage suitable for the second component; and the unselected positioning element line voltage At the same time, the first and second hands are adapted to the first operating mode bias line transmission !, , ^ fly unselected bit voltage.积. The integrated circuit of claim 7, wherein: a m-series coupling circuit is used to sometimes lightly couple the individual first bus segment to the second global bus. 12. The integrated circuit of claim 11, wherein: in the second mode of operation, each of the bus lines of the younger family bus is adapted to the second operation. The bias voltage in the domain voltage condition; and the second mode of operation, the global bias line transfer - the unselected locator bias electric dust suitable for the first mode of operation. 13. The integrated circuit of claim 7, wherein: the first global bus includes a coupling, a 3 coupling 13 to one of the individual data circuits, and a global selection bus; and the S memory array further includes The s丨r mother array block has a second bus bar segment, which is used during the first operation mode, and is adapted to the 123178-1000310.doc U45787 C/V-day correction replacement, the first - Operation mode data dependent bit line block selection positioning element line condition (4) to - selected - suitable for the second operation ==: = mode period, unselected array (four) block unselected positioning untwisted line read rainbow (10) Piece Transfer 14. The integrated circuit of claim 13 is: Each block includes a (four) combining circuit for sometimes coupling individual second busbar segments to the global selection busbar and, at certain other times, to the global bias line and at other times Floating, in the first mode of operation, the global bias line transmits an unselected locator bias voltage suitable for the first mode of operation; and in the first mode of operation, the global bias line An unselected locator bias voltage suitable for the second mode of operation is passed. 15. The integrated circuit of claim 1 wherein: the memory array comprises a three dimensional memory array having bit lines on a two bit line layer; and a two bit line in a different array block The bit line on the layer is simultaneously coupled to the individual bus segment. 16. The integrated circuit of claim 15, wherein: each memory cell comprises a reversible resistor element. 17. The integrated circuit of claim 16, wherein: the reversible resistor element comprises a transition metal oxide. 18. The integrated circuit of claim 5, wherein: each memory cell comprises a reversible resistor element in series with a diode. 123178-1000310.doc S -4- 1345787 ^3月换贡 19. The integrated circuit of claim 1, wherein the first global bus is traversed by the parent in the direction of the bit line Block. 20. A package module comprising the integrated circuit of claim 1. 21. An integrated circuit comprising: a memory array having a plurality of array blocks, each array block comprising word lines and bit lines; a first coupling member for coupling a selected location element of a selected block to an individual data circuit in a first mode of operation by generally crossing a first global bus bar of the plurality of array blocks; a second coupling member for coupling unselected positioning element lines of both selected and unselected array blocks to a first bus bar segment associated with each of the individual array blocks; a first-passing member for Passing on the first array block associated with the selected array block: a first unselected locating element line bias condition suitable for the first mode of operation; and a second transfer member 'for The unselected array block is associated: not passed on the first bus segment - a first unselected positioning element line bias condition suitable for the first mode of operation. 22. The integrated circuit of claim 21, wherein the protection mode comprises a set operation mode; the one-piece suitable for the first operation mode comprises a ··登'&quot; The line biasing bar does not k clamp the 7C line voltage; and is adapted to include the first floating mode condition. First-unselected...line bias strip 123178-1000310.doc -5. 1345787 23. As in the integrated circuit of claim 21: the advance step includes a page swapping operation on the first free month cold swapping mode An individual first to third coupling member associated with one or more column blocks for coupling a selected positioning element line to the selected array bus segment; a third transfer member for use in /, the selected array block is associated with the individual first bus segment segment, and the other data is adapted to the second operating mode dependent bias condition; and - the fourth light component, And combining the unselected positioning element handles of the selected array block to the first global bus bar. 24. The integrated circuit of claim 23, further comprising: in the second mode of operation, coupling the individual first busbar segment associated with the selected array block to a data circuit The components. 25. The integrated circuit of claim 23, wherein: the first mode of operation comprises a reset mode of operation; the individual data coupled to the selected location line of the selected array block suitable for the second mode of operation The dependent bias condition includes a first value that causes a selected positioning 7G line to be reset and a second value that causes a selected positioning element line to not change. 26. The integrated circuit of claim 23, wherein: the first global bus includes a read/write bus coupled to a read/write circuit. 27. The integrated circuit of claim 26, further comprising: a fifth wheel assembly for use in an individual 123178-1000310.doc c -6 - 1345787 heart month/^ day Correcting the replacement page The first bus segment segment is coupled to a second global bus bar, the second global domain bar is itself coupled to the second data circuit and is sometimes used to float the individual first bus segment . 28. The integrated circuit of claim 23, further comprising: a sixth coupling member for coupling each busbar segment of the individual first busbar segment to a global bias line; and a fourth pass And means for transmitting an unselected positioning element line bias voltage in the first mode of operation, sometimes on the global bias line. 29. The integrated circuit of claim 28, further comprising: a seventh coupling member for coupling the individual first bus-sink segments for the respective array blocks to form a span a single logic bus of the plurality of array blocks; and an eighth coupling member for coupling the first busses coupled together to a second data circuit. 30. The integrated circuit of claim 28, further comprising: a seventh coupling member </ RTI> for coupling the individual first busbar segments to a second global busbar. 31. The integrated circuit of claim 28, wherein: the first global bus includes a global selection bus coupled to one of the individual data circuits; and the integrated circuit further includes a fifth transfer component for use Passing a second bus bar segment of each array block, during the first mode of operation, 'transferring the (4)-operation m-substance dependent bit line bias condition to the 敎 bit of the 敎 block Line, and used during the second mode of operation of the 123178-1000310.doc 1345787 3#曰 correction search page, will be - suitable for the second operation: the bit line bias condition is passed to the unselected - no == A. The integrated circuit of claim 21, wherein the first cross is in the direction of the bit line traversing the array blocks. ^W一正33. - A method for mate-memory array use, the memory _ = block, each array block includes a word line and a bit line, in the first mode of operation, the method comprises:排=二: ^ ^ ^ H area convergence, 疋 之 之 π π 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻Block-associated-individual first-bus-segment segments; transmitting on respective first bus-segment segments associated with the selected array block--first unselected positioning element line bias conditions suitable for the first mode of operation; And transmitting on the individual first bus segment associated with the unselected array block - a second unselected positioning element line bias condition suitable for the first mode of operation. 34. The method of claim 33, wherein The second unselected positioning element line bias condition of the first operation panel includes a floating condition. • The method of claim 33, wherein the first global buffer is orthogonal to the The direction of the bit line traverses the array blocks. 3 6. As requested in item 34 Method, wherein: J23178-10003I0.doc 1345787 mouth/3⁄4 correction replacement, the first mode of operation includes a set mode of operation; and = the first unselected location element in the first mode of operation comprises an unselected Bit line voltage. 3 persons as in the method of claim 33, which further enters a second operation mode, and: one or more selected array elements of the selected array block are consumed to the L疋 array area An individual first-bus bar segment associated with the block. ^ is passed to an individual first-stream segment associated with the selected array block, and is adapted to the first-grip; and (iv) a fourth (four) material-dependent partial bar The selected array block is spliced to the bus. The method of transferring the block to the first global domain 38. The method of claim 37, further comprising: in the second mode of operation, The method of claim 38, wherein the method of claim 38 further comprises, in the second mode of operation, an individual first-bus bar (four) person: a bus bar associated with the array block.排片(四)合到-跨40. The method of claim 37, wherein: the second mode of operation comprises a reset mode of operation; wherein the selected bit of the selected array block is adapted to the read bit of the selected bit line - The value and the individual data dependent bias conditions for an operation mode that does not change the selected positioning element line include: the two-bit line is 罟 & & & & & &&;; Doc Day Correction Replacement Page Value 41. The method of claim 37, wherein: 2: The global bus includes a read/write bus coupled to one of the read/write circuits. 42. The method of claim 41, further comprising: ―: coupling an individual first-bus bar segment for an array block to a first-global bus bar, &gt;&gt; ΛΛ g __ one, the second The global busbar is itself coupled to a lean circuit, sometimes used to float the individual first busbar segments. The method of claim 42, further comprising: in the first mode of operation, each of the second global bus bars is biased under the condition of the first unselected positioning element line bias condition; And in the second mode of operation, the cable is biased at a suitable one for the first member. The method of the unselected locating element line biasing bar of the first two global bus modes of the first global bus bar. The method of claim 37, further comprising: sometimes each bus bar of the individual first bus bar segment The line is coupled to a global bias line, and at that time an unselected positioning element line bias voltage suitable for the first mode of operation is transmitted over the global bias line. 45. The method of claim 44, further comprising: arbitrarily coupling the individual sigma-bus slabs for the respective array blocks to form a single across the plurality of array blocks 123178-I〇〇〇3i〇.doc 1345787/3⁄4 modified replacement lean logic bus; and electricity: the first-to-second second data that is combined together. 46. The method of claim 45 further includes : The individual first sink-segment segments for the respective array blocks are coupled together during the pattern mode. 47. The method of claim 45, further comprising: in the second mode of operation, arranging the bus lines of the first-global bus bar in the Pan-person to be biased under the second operating device. And the unselected clamps of the line bias strips are transmitted on the first and second modes of operation - suitable for the first operation to bias the line voltage at the global direction. The unselected locating element bias power 48. The method of claim 44, further comprising: arranging the individual first bus. The slave is coupled to a second global convergence 49. The method of claim 48, wherein the step further comprises: in the second mode of operation, the cable is at - each of the manifolds suitable for the second money bus The lower bias voltage; and the unselected positioning element line bias strips are transmitted on the first and second operations Hi - suitable for the first operating mode - under the global dust line pressure. The unselected positioning element bias voltage 50_, as in the method of claim 44, wherein: 123178-1000310.doc 1345787 The first global bus bar includes a light-weighted connection to the individual asset-wide selection buss; and the method further includes a second channel segment segment by each array block, during which the first mode of operation will be adapted In the first: off: the individual data of the mode depends on the bit line partial (4) to _ selected area selected position read 'and used in (4) two operation mode _ unselected positioning element line offset in the second mode of operation : The unselected positioning element of the selected array block. The method of claim 50, wherein the selection of the individual data dependent to the selected array block during the first mode of operation comprises: - selecting - = The method of claim 50, wherein the method of claim 50 further comprises: ??? All = select bus bar 'and at some other time (four) join line, and at other times make individual second bus bar segment float; £ operating mode, pass on the global bias line - suitable for the first mode of operation The locating element is not selected for the dust voltage; and in the second mode of operation, the unselected locating element in the second mode of operation is partial. suitable. 53' method for manufacturing a memory product, the method comprising: "=:! memory array, having a plurality of array blocks, each array block comprising word lines and bit lines; + single 歹 J 123178 -1000310.doc •12· 1345787 fYj's 'Nongken's replacement page j forms a first global bus, which generally spans the plurality of array blocks for the selection of the selected blocks. a bit-axis-to-feed circuit; forming an individual-bus-strip segment of each array block for using a first unselected locating element line (4) suitable for the first mode of operation during the -first mode of operation The condition is passed to the unselected location element t of the selected block and is adapted to the first of the first mode of operation: the untwisted bit line bias condition is passed to the unselected location line of the unselected array block. The method of claim 53, wherein: the first operation mode comprises: setting an operation mode; and is suitable for the younger one to make a grip 4 «Jr # &amp; 株人", #作模式的第一-unselected positioning element Line biased cattle l 3 unselected bit line voltage; and suitable for the first mode of operation Contains - floating conditions. The first-unselected bit line bias strip 55. The method of claim 53, wherein: · sink: slice: in the operation mode, the individual first-first: light combination of a selected array block is suitable The individual bias conditions on the individual bus block H stream lines in the second mode of operation are passed to the selected location line of the selected block. 56. The method of claim 53, wherein the first global bus is traversed by the first global bus in a direction orthogonal to 疋. 57. The method of claim 55, wherein the step comprises: forming a dedicated read/write bus of the first global bus. To a read/write circuit 123178-I000310.doc • 13- Laughter "Month / ^ Correction Replacement Page 58. The method of claim 57, wherein the step _ includes: consuming a second data to a thunder For the long-term "&amp; _ circuit brothers two global bus; individual first - two sergeant "cause 0 circuit, which is used to sometimes couple the squall bus segment to the floating of the 坌 - people. The method of claim 55, further comprising: the method of claim 55, further comprising: forming a global bias line to a bias circuit; forming a single stem w 祸 σ circuit for each block, For sometimes arranging the respective busses of the bus bar segment, the melon cable is coupled to the global bias; = the global bias line transmission - suitable for the first operation mode fly unselected The bit line bias voltage. The method of claim 59, wherein the step further comprises: forming a plurality of coupling circuits for use in the respective first confluences The rows are coupled together to form a single-logic logic bus that spans one of the plurality of array blocks The coupling-bus-bus segment is consumed to the second data circuit. 61. The method of claim 59, wherein the step further comprises: forming, for each block, an individual light-splicing circuit, The method of claim 59, wherein the method of claim 59, wherein: the first-global bus includes a face-to-face data circuit a global selection bus; and the method further forms an individual:_segment segment of each array block for use during the first mode of operation, one suitable for the first 123178-1000310.doc • 14- 1345787 ζΟ 〇 ' &quot;ΊΛΙΓ·year&gt; month~correct replacement page, mode selection locating element line bias condition is passed to the second line of the selected block, and is used in the first: operation mode Lang--the unselected positioning element line suitable for the second mode of operation is passed to the unselected positioning element of the un-arranged block. 63. The method of claim 53, further comprising · forming - three-dimensional Memory array, which has a two-dimensional line layer 64. The method of claim 63, wherein: the method of claim 63, wherein: forming a memory single opening, 甘 λ 70 comprising a reversible resistor element. 65. The method of claim 62, the first global domain The busbars are orthogonal to the square of the bit lines and the array blocks are used. 123178-1000310.doc 15·