TW200826114A - Method and apparatus for hierarchical bit line BIAS bus for block selectable memory array - Google Patents

Abstract

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Description

200826114 IX. Description of the Invention: Technical Field of the Invention The present invention relates to a programmable memory array, and more particularly to a semiconductor integrated circuit memory array incorporating a passive element memory cell, and more particularly It relates to an array of bodies incorporating such memory cells. & [Prior Art] A specific passive element memory unit exhibits rewritable characteristics. For example, in a particular memory cell, stylization can be achieved by using a voltage of __about 6 w 8 v to positively bias the memory cell (10), such as referring to the polarity of a diode within it, and erasing can be performed. This is achieved by using a voltage of approximately 10 ν to 14 ν to reverse the memory cell. These high voltages require the use of special high-dust CMOS transistors in the word line and bit line decoders. The high voltage transistors are not fully scaled as the memory cell word lines and bit line pitches decrease. This is particularly problematic for three-dimensional memory technology, where the pure density of the word lines and bit lines that must exit the array and must interface with a word line and bit line drivers to provide a decoder that is compatible with ever-decreasing array line spacing. And the ι/〇 circuit (and especially the word line and bit line driver circuits) can still be more important across the ability of a selective memory cell to operate at a sufficiently high voltage. SUMMARY OF THE INVENTION The present invention generally relates to a memory array incorporating a hierarchical bit line bias bus for a block selectable memory array, and a use for one block selectable A method of a hierarchical bit line bias busbar of a memory array. However, the present invention is defined by the accompanying patent application number 123178.doc 200826114, and nothing in this section should be construed as limiting the scope of the claims. In one aspect, the present invention provides an integrated circuit including a memory array having a plurality of array blocks, each array block including a word line and a bit 70 line beta accumulation circuit including - generally spanning the complex number A global bus, used for the bit line of the _he-敎 block = individual data circuit. The integrated circuit further includes an additional first money collecting segment per array block for transmitting a first-unselected positioning element line bias condition suitable for the first operating mode during the first operating mode to - selected (4) positioning the element line of the block, and transmitting a second unselected positioning element line bias condition suitable for the first mode of operation to an unselected positioning element line of the unselected array block. In another example, the present invention provides an integrated circuit including an A It column having a plurality of array blocks, each array block including a word line disk bit line. The integrated circuit includes a light-fitting component for facilitating a first global busbar that generally spans the plurality of array blocks in a first (four) mode, and selects a selected location line from the selected block to Individual data circuits. The integrated circuit includes a light-construction component, a ..., a component, a positioning element for the face-selecting and unselected array blocks, and a different one associated with each of the array blocks. Bus segment. & g "The integrated circuit includes a transfer member for transmitting the appropriate condition of the second unselected positioning element on the individual first-bus bar segment associated with ..._P. The individual number -= of the phase combination is used to pass a second unselected positioning element line depletion condition applicable to the first operating mode 123l78.doc 200826114 on the unselected array block/machine segment. In another aspect, the invention provides a method for use with a memory array having a plurality of array blocks, each array block comprising word lines and bit lines. The method includes, in a first mode of operation, coupling a selected location line to a plurality of data circuits, coupling selected and unselected array regions by means of a first global bus bar that generally spans the plurality of array blocks An unselected positioning element line of the block to an individual first bus bar segment associated with each of the individual array blocks, and an individual first bus bar segment associated with the selected array block uploading_for the first Transmitting a first unselected positioning line bias condition of the operating mode and transmitting an individual unselected positioning line offset for the first operating mode on the individual first bus segment associated with the unselected array block Pressure conditions. In another aspect, the invention provides a method for making a memory product. The method includes forming a memory array I array block having a plurality of array blocks including word lines and bit lines. The method also includes forming a first global busbar that generally spans the plurality of array blocks for use in selecting the location lines of the time-selected-selected blocks to the individual data circuits. The method also includes forming a different first busbar segment per array block for transmitting a first selected positioning s-wire bias condition suitable for the first mode of operation to a selected block during a first mode of operation The unselected positioning element line, the second unselected positioning element line of the first operation mode is biased to the unselected positioning element line of the unselected array block. The invention of the invention is applicable to a method for operating such an integrated circuit and a memory array in a plurality of aspects: 123178.doc 200826114 A method for entering a memory product of such an array and such a product The body code, product or memory array computer can read the media code, as described in more detail in this article and attached to the towel (4). The techniques, structures and methods can be used individually or in combination with one another. The foregoing is a summary of the invention, and is therefore intended to be in the Other aspects, innovative features, and advantages of the invention will be apparent from the scope of the appended claims. [Embodiment] FIG. 1 is a schematic diagram of an exemplary passive component memory array 100. Two word lines 102, 1 〇 4 and two bit lines 106, 1 〇 8 are displayed. Assume that word line 1 〇 2 is a selected word line (SWL) and that word line 1 〇 4 is an unselected word line (UWL). Similarly, the pseudo-positioning line 1〇6 is a selected positioning element line (sbl), and the pseudo-positioning unit line 108 is an unselected positioning element line (UBL). Four passive = piece memory cells 101, 103, 105, 1 〇 7 are shown, each coupled between an associated word line and an associated bit line. The memory unit 101 is associated with the selected word line 〇2 and the selected locating element line 〇6, and thus can be regarded as an "S" unit (i.e., "selected" unit). The memory unit 1〇3 is associated with the unselected word line 104 and the selected positioning element line 106, so it can be regarded as a 'F' unit (ie, "off" unit). The memory unit 1〇5 is connected to the selected word line. 1〇2 and unselected positioning element line 108 are associated, so it can be regarded as one, H" unit (ie, semi-selected ''unit). Finally, memory unit 1〇7 is connected with unselected word line 1〇4 And the unselected bit line 1 〇 8 is associated, so it can be regarded as one, U,, unit (ie, not selected) 123178.doc 200826114 unit). Figure! Exemplary bias conditions for the -forward bias mode of operation are also described. As described elsewhere herein, this forward bias mode can be used in a stylized mode, a block erase mode, and a read mode (but typically such different modes use different levels or conditions). As shown, these bias conditions; r are considered to be suitable for a stylized mode of operation for a selected array block and will be described as such. The selected word line 102 is biased at a VSX voltage (e.g., ground), the selected bit line 106 is biased at a VSB voltage (e.g., +8 volts), and the unselected word line 104 is tied to a VUX voltage (e.g., + The 7.3 volts are biased, while the unselected location lines 108 are biased at a VUB voltage (e.g., +0-7 volts). The selected positioning element line bias voltage VSB can be regarded as a stylized voltage νρρ, since substantially the entire voltage is applied to the selected § memory unit 1 〇i (since the selected word line is biased at ground), There is less specific resistance drop in the bus and array lines themselves. The unselected positioning element line bias voltage VUB is also preferably set in a forward bias direction of one of the memory cells to correspond to an apparent, threshold voltage '' value, thus being displayed as a voltage VT Acting on the unselected positioning element line 108. Similarly, the unselected word line bias voltage ν υχ is preferably set to a value of VPP-VT. Under these bias conditions, S unit 101 receives a forward bias voltage equal to VPP (e.g., +8 volts) and F unit 103 receives a forward bias voltage equal to VT (e.g., +〇7 volts). Unit 105 receives a forward bias voltage equal to VT (e.g., +〇7 volts), and U unit 107 receives a reverse bias voltage equal to νρρ·2ντ (e.g., -6.6 volts). There are several exemplary memories. 123178.doc 10 200826114 Unit technology, when biased under these conditions, the selected cells will change to a lower resistance value, while the F, Η and U cells have no resistance change. Exemplary units are described below. Referring now to Figure 2, an exemplary bias condition 200 for a reverse bias mode of operation is shown. As described elsewhere herein, this reverse bias mode can be used in either a stylized mode or a block erase mode (although typically different modes use different conditions). As shown, these bias conditions can be considered to be suitable for one use.

The stylized mode of operation or the erase mode of operation of a selected array block will be described as such. The bias conditions of these bias conditions VSX, Vux, VSB and VUB will now be redefined for values suitable for this mode of operation. The selected word line 102 is biased at a Vsx voltage of VRR/2 (e.g., +5 volts) and the selected bit line 106 is biased at a VSB voltage of -VRR/2 (e.g., _5 volts). The unselected sputum line voltage VUX and the unselected locating element line voltage vub are both grounded to 0, bite, ▼ Αν XV1 jyfi under the bias conditions, S unit ιοί receives a number such as - ίο volts To the bias voltage, F unit 1〇3 receives a reverse bias voltage equal to ^ΚΚ/2 (eg, 5 volts), and unit 1G5 receives a reverse bias equal to VRR/2 (eg, _5 volts). Voltage. It should be noted that 1〇7 does not receive any bias voltage across the unit. In the right-handed exemplary memory cell technology (see below), when biased under these conditions, the selection of a & early will change from a lower resistance value to a more specific resistance value, while green back There is no slight change in the resistance of the vertical qu unit. It should also be noted that 'there are no biases in the body, and there is no leakage current, which is any voltage leakage across several volts across such cells. In addition, a considerable amount of leakage current can be supported by the monthly b. As described in further detail, many useful memory array embodiments include a much larger number of U-singles 70 than H cells or F cells, and such arrays have in the unselected memory cells of the array compared to other biasing schemes Significantly lower leakage current and therefore much lower power consumption. By splitting the "VRR voltage" in this reverse mode and biasing the hunger at a negative voltage equal to the programmed voltage - half, and biasing SWL at a positive f-voltage equal to the programmed voltage - half, The voltage requirements of the bit line decoder and the word line decoder are significantly relaxed. Therefore, consistent with the smaller spacing of the array lines (eg, word lines and bit TL lines), within the array line driver circuits The high voltage transistors occupy less (4) because they can be designed to achieve a relatively low "divided" voltage. Other memory technologies - straightforward about stylized and erase voltages (and such high voltages) The area required for the crystal does not scale at the same rate as the memory cell spacing. For example, the effect of this problem in flash memory is sometimes due to the fact that flash memory is the main memory array. Large fanouts are slightly reduced. More design rules for high-voltage transistors can be achieved by increasing the memory block size in some newer technologies. Polar body-based passive component memory array The size of the larger block is at the cost of the unselected note belonging to the selected array: (4) the leakage of the body unit. ################# 'This leakage component can be reduced to almost zero and obtained - larger block size' with almost no harmful power consumption. " 123178.doc 200826114 Referring now to Figure 3, an exemplary word line decoder circuit is shown, including A bias condition suitable for the forward bias mode of operation is shown (as shown in Figure 1). A column of decoder circuits is shown on the left side of the page that displays two decoded outputs 15 8 and 162. The decoded output 158 corresponds to a selected decoded output. The decoded output 162 corresponds to an unselected decoded output. A column of decoders 152 can be implemented using any of a variety of well known techniques to produce a plurality of decoded outputs, such as outputs 155, 159, which are multiplexers 157, 161 and Inverters 156, 16 are conditionally inverted. An inverting buffer is incorporated after the NAND gate to drive node 155 due to the large capacitive load on node 158 (i.e., as herein, Multiplexer 157 manipulation Node 155 to output 158). Column decoder 152 operates in this mode of operation ... equal to vpp upper supply voltage is coupled to power supply node 153 and a grounded lower supply voltage is coupled to power supply node 154. In this mode of operation Next, the column decoder is a "high state efficient decoding", meaning that the selected output (or outputs), such as the decoded output node 158, is driven to the highest of the two available voltage states, in which case it is tied. The unselected decoded outputs (e.g., the decoded output node is driven to the lowest of the two available voltage states, in which case the grounded pair will be most determined - only selected - such decoded input points (eg "High state") Each decoding output _ is connected to - one word line driver circuit. For example, the decoding output node (5) is consuming to a word line driver circuit including: a transistor 171 and a transistor s. 171: 172, the individual 汲 extremes are simultaneously coupled to a word line heart. Although the invention is specific: 眚 in this case indicates that the selected embodiment covers the multi-head decoder 123178.doc •13-200826114 The decoder, but Figure 3 depicts a second word line driver circuit also coupled to the decoded output node i58, which represents one or more other word line driver circuits associated with this particular decoded output node 158. This second word line The driver circuit includes a PMOS transistor 173 and an NMOS transistor 174, the output of which drives a word line 181, and the word line 181 represents one or more semi-selected word lines. Within each circuit of the word line driver circuits NM0S electric crystal The individual source terminal is coupled to an individual bus line of one of the source select busses XSEL. In this mode of operation, the source select bus is decoded based on the address information to make it suitable for this mode of operation. The word line is active; the bus bar is biased in the state, and the remaining bus bars are biased in an inactive mode of operation suitable for the operating mode word line. In a particular embodiment, 'a plurality of such The source select bus can be active, but now assume that the bus bar 167 is active and biased at ground, and one or more of the remaining bus bars (denoted as bus bar 168) are invalid and driven to The word line voltage VUX (shown as VPP-VT) is not selected. Since the voltage (VPP) on the decoded output node 158 is higher than the voltage of the bus bars 167, 168, the NMOS transistors 172, 174 are connected. Passing, thereby driving the selected word line 102 to ground, and driving the semi-selected word lines 181 to VPP-VT. The two conductive paths are indicated as open-ended arrow lines. PM〇 in each circuit of the word line driver circuits s individual source terminal of the transistor The unselected bias line UXL is also labeled as node 1 64. In this mode of operation, the UXL bias line passes the unselected word line voltage VUX. Because the voltage (vpp) at the decoded output node 158 is high. The voltage of the UXL bias line is such that the two pm 〇S transistors 171, 173 are turned off. 123178.doc -14- 200826114 The decoded output, point 162, is coupled to a word line driver circuit, which includes a PMOS transistor 175 and The operating transistor 8 transistor, the individual terminal of the transistor, is simultaneously coupled to a word line, in which case the unselected word line 104 is shown. Also coupled to one of the decoded output nodes 162, the second word line driver circuit represents one or more remaining word line driver circuits associated with the decoded output node 162 and includes a PMOS transistor 177 and an NMOS transistor 178, such The output of the crystal drives an unselected word line 183. The individual source terminals of the Nm〇s transistors in each of the circuits of the word line driver circuits are coupled to an other bus bar of a source select bus xsel. Since the voltage (ground) at the decode output node 162 is at or below the voltage of the bus bar 167 ' 168, both NM 〇 s , 178 are off. The individual source terminals of the PMOS transistors in the various circuits of the word line driver circuits are coupled to unselected bias line UXL node 164. Since the voltage (ground) at the decode output node 162 is lower than the voltage of the UXL bias line 164 (above the low PMOS threshold voltage), the two PMOS transistors 175, 177 are turned "on", thereby driving the unselected word lines 104. , 1 83 to VUX (for example, VPP-VT). The two conduction paths are indicated by an open-ended arrow line. Referring now to Figure 4, this same exemplary word line decoder circuit is shown, including bias conditions suitable for the reverse bias mode of operation (shown in Figure 2). The decoded output 158 of the column decode circuit still corresponds to a selected decoded output, and the decoded output 162 corresponds to an unselected decoded output. The column decoder ι52 operates in this mode of operation, with a supply voltage equal to the upper portion of VRR/2 coupled to the power supply node 153 and a lower ground supply voltage coupled to the power supply node 123178.doc 200826114 154. In this mode of operation, the column decoder is one, the high state is active, and the decoder 'and the active (selected) decoded output 158 is driven to two available voltages using inverter 156 and multiplexer 157. The lowest of the states, in this case it is GND (ground). The unselected decoded outputs (e. g., decoded output node 162) are driven to the highest of the two available voltage states using inverter 16 and multiplexer 161, in this case VRR/2. In this mode of operation, for the exemplary embodiment, the individual bus bars of the source select bus XSEL are all driven to the same bias condition (ground), and the "unselected, biased" The voltage line 11 further transmits a bias voltage Q equal to VRR/2 (e.g., +5 volts). In this reverse mode of operation, the bias line UXL actually delivers an active state suitable for the word line, instead of An invalid or unselected bias condition. Since the voltage (GND) on the decoded output node 158 is relatively lower than the voltage of the bias line UXL (i.e., above a pM s s threshold voltage), the PMOS transistors 171, 173 is both turned "on" to drive the selected word line 102 to VRR/2, and also drives the originally half-selected word line (shown here as selected word line 181) to VRR/2. The path is indicated by an open-ended arrow line. In this mode of operation, the source select bus xsel is not decoded, and each such bus line is in an inactive state (eg, ground) that is applied to a word line. Voltage because the voltage (ground) at the decoded output node 158 is not higher than The voltages of the bus bars 167, 168 are such that the 1^1^8 172, 174 are both turned off. The decoded output node 162 is an unselected output, driven by the inverter 16 and the multiplexer 161. Up to VRR/2. Since the voltage 123178.doc -16-200826114 on the output node 丨62 is pressed against the voltage of the bus bars 167, 168, the NMOS 176, 178 is turned "on" The unselected word line 丨〇4, ί 83 is driven to ground 0. The path is indicated as an open-ended arrow line. Due to the voltage on the decoded output node 162 and the voltage transmitted on the UXL bias line 164 The same, so the two PMOS transistors 175, 177 are cut off.

Referring now to Figure 5, an exemplary bit line decoder circuit is shown including display of bias conditions suitable for a forward bias mode of operation (shown in Figure 1). A row of decoder circuits is displayed on the left side of the page, which displays two decoded outputs 2〇8, 212. Decoded output 208 corresponds to a selected decoded output and decoded output 212 corresponds to an unselected decoded output. A row of decoders 2 〇 2 can be implemented using any of a variety of well known techniques to produce a plurality of decoded outputs, such as outputs 205, 209, which are multiplexers 207, 211 and the inverters 2 〇 6, 210 To conditionally reverse. Unlike the column decoder, there is no inversion buffer to drive node 2〇5 after the gate, because the capacitive load on node 2〇8 is greater than the output for the column decoders. It is much lower. The row decoder 202 operates in this mode of operation, i.e., the upper supply voltage is coupled to the power supply node 203 and a grounded lower supply voltage is coupled to the power supply node 204. In this mode of operation, the row decoder is a low state / effect & decoder. The unselected decoded outputs (e. g., decoded output node 212) are driven to the highest of the two available voltage states, in this case VPP. The following will initially assume that only &lt;RTIgt; such decoding output node 208 (e.g., "low state") is selected. Each decoded output is coupled to - or a plurality of bit line driver circuits. For example, the decode output node 208 is coupled to a one-bit line driver circuit, which includes a PMOS transistor 221 and an NMOS transistor 222. The individual 汲 terminal sections of the transistors 221, 222 are simultaneously coupled to a single bit line, in this case the selected locating element line 106. Although a particular embodiment of the present invention encompasses a decoder other than a multi-head decoder, FIG. 5 depicts a second bit line driver circuit that is also coupled to the decode output node 208, which is associated with this particular decode output node 208. One or more remaining bit line driver circuits. The second word line driver circuit includes a PM 〇s transistor 223 & nm 〇s OLED 224. The output of the NMOS transistor is driven by a bit line 23 1 which represents a plurality of semi-selected positions it and a line. Comparing the word line decoder, the & class semi-selected positioning line can represent a selected positioning element line, which is maintained in an inactive state. The individual source terminals of the pM〇s transistors in each of the bit line driver circuits are coupled to a source select bus selB2 and a different bus bar. In this mode of operation, the source selection bus (3) is data dependent and can be further decoded based on the address information such that one or more such bus lines are suitable for this mode of operation. A bit line is biased in an active state, and for this mode of operation, the remaining bus bar is biased in an inactive state suitable for the bit line. In a particular embodiment, one or more of such source select bus bars may be active, but now assume that bus bar 217 is active and biased at vpp, and one or more remaining bus bars (It is indicated that the bus bar 2 is invalid and driven to the unselected positioning element line voltage VUB (shown as VT). Since the voltage (ground) on the decoded output node 208 is lower than the voltage of the bus bar lines 217, 218, Therefore, the ?? 8 transistors 221, 223 are both turned on, thereby driving the selected positioning element line 106 to VPP, and driving the semi-selected positioning elements 123178.doc -18-200826114 lines 23 1 to VT. The two conduction paths are indicated as open-ended arrow lines. The individual source terminals of the NMOS transistors in the various circuits of the bit line driver circuits are coupled to an unselected bias line UYL, also labeled as node 214. In this mode of operation, the UYL bias line passes the unselected positioning element line voltage VUB. Since the voltage (ground) on the decoded output node 208 is lower than the voltage of the UYL bias line, the second NMOS transistor 222, 224 is cut off. Decode output node 212 is coupled to a bit element A driver circuit comprising a PMOS transistor 225 and an NMOS transistor 226. The individual 汲 terminal sections of the transistors 225, 226 are simultaneously coupled to a bit line, in this case representing the unselected bit line 108. Also coupled to decoding A second bit line driver circuit of output node 212 represents one or more remaining bit line driver circuits associated with decode output node 212 and includes PMOS transistor 227 and NMOS transistor 228, the output of the transistors Driving an unselected positioning element line 233 ° As described above, the individual source terminals of the PMOS transistors in the respective circuits of the bit line driver circuits are coupled to one of the individual bus bars of a source selection bus line SELB. Since the voltage (VPP) on the decoded output node 212 is at or above the voltage of the bus bars 217, 218, the PMOSs 225, 227 are both turned off. Within the circuits of the bit line driver circuits. The individual source terminal of the NMOS transistor is coupled to the unselected bias line UYL node 214. Since the voltage on the decoded output node 212 is VPP, the two NMOS transistors 226, 228 are turned "on", thereby unselected positioning. The lines 108, 233 are driven to VUB (eg, VT). The two conductive paths are indicated by the 123178.doc -19-200826114 open-ended arrow line. Referring now to Figure 6, the bit line decoder circuit is shown, including The bias condition of the reverse dust operation mode (shown in Figure 2). The decoded output 208 of the row decoder circuit still corresponds to a selected decoded output, and the decoded output 2 12 corresponds to an unselected decoded output. The decoder 2〇2 operates in this mode of operation, with a supply voltage equal to the upper GND coupled to the power supply node 203 and a lower supply voltage _Vrr/2 coupled to the power supply node 2〇4. In this mode of operation, the row decoder is a &quot;high state valid&quot; decoder, and the active (selected) decoded output 208 is driven to two available voltage states by inverter 206 and multiplexer 207. The highest one, in this case, is GND (ground). The unselected decoded outputs (eg, decoded output node 212) are driven to the two available voltage states by inverter 210 and multiplexer 211. The lowest, in this case, is -VRR/2. In this mode of operation, for the exemplary embodiment, the individual busbars of the source select bus SELB are all driven to the same The bias condition (ground), and the "unselected" bias line UYL delivers a bias voltage equal to -VRR/2 (e.g., -5 volts). In this reverse mode of operation, the bias line UYL actually delivers an active state suitable for the bit line, rather than an invalid or unselected bias condition. Since the voltage (ground) on the decoded output node 208 is considerably higher than the voltage of the bias line uyL (below the NMOS threshold voltage), the NMOS transistors 222, 224 are both turned "on" to select the selected The bit line 106 is driven to -VRR/2 and also drives the half-selected bit line (shown here as the selected bit line 23A) to -VRR/2. The two conductive paths are indicated as open-ended arrow lines. 123178.doc -20- 200826114 In this mode of operation, the source select bus SELB is non-data dependent or not decoded (at least in a given block), and each such bus line is suitable for A bias of a bit line in an inactive state (eg, ground). Both of the PMOS transistors 221, 223 are turned off. Decode output node 212 is an unselected output and is driven to -VRR/2. The PMOS transistors 225, 227 are both turned "on" to drive the unselected clamp lines 108, 233 to ground. The two conduction paths are indicated as open-ended arrow lines. The two NMOS transistors 220, 228 are turned off. It should be noted that 'in this forward mode' the row decoder is active low and the bit το line is active high. However, in the reverse mode, the row decoder becomes active in the high state against its polarity, and the bit line itself is also inverted and becomes active in the low state. Conversely, in this forward mode, the column decoder is active high and the word lines are active low. However, in the reverse mode, the column decodes H to reverse its polarity and becomes active low, and the word lines themselves are reversed to be polar and become active. It should also be noted that the row decoder output level is offset above the average voltage between the forward mode (i.e., GND to VPP) and the reverse mode (i.e., _VRR/2 to GND). When viewed as a non-multi-head decoder (in Figures 3, 4, 5 and 6, only non-dashed array line driver circuits), the operation of the decoder circuit can be explained very simply. In the reverse mode, the word line decoder reverses its polarity and places a selected word line high (~5 V) while leaving all other selected word lines grounded. This reversal occurs on the bit field selection side, where the 敎-bit line is -5 V and all other bit lines are grounded. The end result is a 10 V reverse bias across the selected memory cell and a zero reverse bias across the other cells. 123178.doc -21 - 200826114 These transistors in the sub-line and bit line drive II circuits only have to withstand 5 V, or half the maximum voltage, not the entire voltage. When considering the use of a multi-headed stone device (in Figures 3, 4, 5 and 6, including the virtual array line driver circuit), it should be noted that the circuit thus far uses the -decoding source in the forward direction. A bus is selected that allows selection of the single group of array lines (but simultaneously drives the remaining semi-selected array lines to an unselected (four) condition). However, in the reverse mode, the selected decoded output from the column and row decoders couples the array lines to a single unselected bias line (e.g., UXL and UYL). Semi-selected array lines are not known under this inverse weight using the m-line. Thus, the above described circuits and techniques are useful in configuring an array of line blocks (e.g., block erase,) to be selected in the reverse mode. As can be seen in Figures 4 and 6, a selected wordline block and a selected locating meta-line block are simultaneously selected in the reverse mode without any independently configurable semi-selected array lines. This type of block operation avoids the need for any semi-selected lines. The decoding implication may be very similar to the word line configuration having a multi-layer word line segment for a three-dimensional memory array, as described in U.S. Patent No. 6,879,5,5, issued to </RTI> &lt;heUerlein, which is incorporated herein by reference. Reveal the inner valley king.并入 is incorporated herein by reference. Whether this block operation can be configured (or how large a block can be configured) depends mainly on the number of cell reset currents, the number of cells that conduct such reset currents, and the word line driver circuit and bit lines. Whether the PM〇s and NMOS transistors in the driver circuit can support such currents at an acceptable voltage drop. A semi-selected array line can be provided in this reverse mode by using other techniques (except in the forward mode). In a single such technique, 123178.doc -22-200826114, the column and row decoders may be powered by an overvoltage such that the decoded output nodes are above the PMOS source voltage and below the NM0S source voltage. across. By doing so, the selected word line can be driven to the south by +NVR/2 voltage through the NM〇s transistor, and the selected positioning line can be driven down to the -VRR/2 voltage through the PM〇s transistor. This utilizes the same transistor as during the forward mode to drive the selected word line and bit line. Such techniques are illustrated in Figures 7 and 8. Referring initially to Figure 7, a word line decoding is illustrated as a circuit that utilizes an overdrive decode output to drive the array line drivers with their sources maintained under the bias conditions described above. In this column decoder circuit, column decoder 152 is powered by an 8 volt upper supply voltage and a negative i volt lower supply voltage. The polarities of the decoded output nodes 158, 162 are inversely reversed with respect to the polarity shown in Figure 4, and are now a high effective decoder that provides a selected output 158 at +8 volts and provides one at _ volts. Decoded output 162 is not selected. The source select bus xsel keeps a decoding busbar unchanged. The (or more) of its individual flow lines are selected and driven to +5 volts, and the unselected lines are driven to ground. The nm〇s transistor 172 is turned "on" and conducts the selected word line 1〇2 to the associated bus line voltage (+5 volts). The NM〇s transistor m is also turned "on" and conducts the (equal) half-selected word line 181 to ground. When the decoded output node is not selected, the PMOS transistors 175, 177 are simultaneously turned on, and the unselected W lines πμ, 183 are conducted to ground. In some specific implementations using this technique, the conditions (4) and the like are not output to the inverters 156, 160 and the multiplexers 157, 161 (shown here as "dotted lines"). Referring now to Figure 8, a description is made. A bit line decoder circuit that also drives the array line drivers using a 123178.doc -23 - 200826114 overdrive decoding output. In this row decoder circuit, the row decoder 202 is powered by a +1 volt power supply. The voltage is supplied with a negative supply voltage of minus 8 volts. The polarities of the decoded output nodes 2 〇 8, 212 are inversely opposite to the polarity shown in Figure 6, and are now a low effective decoder at _8 volts. A selected output 208 is provided and an unselected decoded output 212 is provided at +1 volt. One (or more) of the individual 8 £1^6 bus bars 217 are selected and driven to _5 volts. The unselected 16 bus bars 218 are driven to ground. The PM〇s transistor 221 is turned "on" and conducts the nominal select bit line 1 〇 6 to the associated SELB bus line voltage (_5 volts). The PMOS transistor 223 is also turned "on" and conducts the (equal) semi-selected word line 23 1 to When the unselected decode output node 212 is at +1 volt, the NMOS transistors 226, 228 are simultaneously turned on and the unselected locating elements 108, 233 are conducted to ground. In some embodiments, the conditional output inverters 2〇6, 21〇 and the multiplexers 207, 211 are not used. In another technique, the semi-selected word lines and bit lines can be replaced by The single unselected bias lines UXL and UYL are combined into a different reverse source select bus to be provided in the reverse mode. Referring now to Figure 9, a word line decoder circuit is utilized which utilizes a dual decoding source. A pole selection bus. One of the PMOS transistors for the word line driver circuits, the reverse source select bus XSELP has been incorporated in place of the unselected bias line UXL shown in FIG. The remainder of the line decoder circuit operates as previously described. In this reverse mode, the selected decode output node 158 is active low and driven to ground. The individual sources of the reverse source select bus XSELp are 123178.doc - 24-200826114

One of the streamlines is selected to be biased to an effective bias condition suitable for the reverse mode of operation of a word line. In this case, the selected bus bar 243 of the XSELP bus is driven to VRR/2, and the unselected bias line 244 of the XSELP bus is driven to an invalid bias for this mode of operation for a word line. The pressure condition, in this case, is driven to ground. The PM〇s transistor 171 is turned on by the low voltage that is turned to its gate, and drives the selected word line 1〇2 to the VRR/2 potential. However, the PMOS transistor 173 within the half-selected wordline driver circuit remains off because the voltage on its gate is not sufficiently low relative to its source, since both are grounded. Since the NMOS transistor 174 is also turned off, none of the transistors in the half-selected word line driver circuit are turned "on". Therefore, the semi-selected word lines float at or near the ground potential. As in the case of the exemplary circuit, this occurs when the NMOS pull-down transistor 174 is larger than the pM 〇s pull-up transistor 173. Larger transistors have a larger number of leaks than their smaller ones. Therefore, since the transistor 174 has a substrate tied to the ground, the ground leakage current dominates the substrate leakage current to the VRR/2 generated by the pM〇s transistor 173, and this net current tends to place the unselected word lines. (8) Maintain at or near the ground potential. The word line (four) circuits associated with the unselected decode output node 162 operate as previously described, and the nm 〇s transistors 176, 178 are turned "on" to conduct the unselected word lines 104, 183 to ground. The low level in an alternative embodiment can be achieved by using a low power supply equal to the column decoder 152, the inverter i56 'the dedicated decoding output node 1 5 8 , 1 6 2 -ντρ (or lower). 154, 160, and multiplexers 157, ι 61 drive 123178.doc -25- 200826114 move to below ground (for example, to a voltage below the ground PMOS threshold voltage or below 'that is -VTP). Thus, the PMOS pull-up transistor 173 is turned "on" to effectively drive the (equal) half-selected word line 181 to ground. A similar situation occurs in a row decoder circuit that incorporates a dual data dependent source select bus. Referring now to Figure 丨〇, a bit line decoder circuit is illustrated which utilizes dual decoding (in this case data dependent) source selection bus. One of the NMOS transistors for the bit line driver circuit, the reverse source select bus SELN, has been incorporated in place of the unselected bias line UYL shown in FIG. The remainder of this bit line decoder circuit operates as previously described. In this reverse mode, the selected decode output node 208 is active high and driven to ground. One of the individual bus bars of the reverse source select bus SELN is biased to an effective bias condition suitable for the reverse mode of operation of the one bit line. In this case, the selected bus bar 247 of the SELN bus is driven to -VRR/2, and the unselected bias line 248 of the SELN bus is driven to a bit line suitable for this mode of operation. The bias condition, in this case, is driven to ground. NMOS transistor 222 is turned "on" by a high voltage coupled to its gate and drives selected word line 1 〇6 to the -VRR/2 potential. However, the NMOS transistor 224 in the half-selected word line driver circuit remains off because the voltage across its gate is not sufficiently high relative to its source, since both are grounded. Since the PMOS transistor 223 is also turned off, any of the transistors in the half-selected locator driver circuit are not turned "on". Therefore, the semi-selected positioning lines float at or near the ground potential. As in the case of this exemplary circuit, 123178.doc -26-200826114, this occurs when the PMOS pull-up transistor 223 is larger than the NMOS pull-down transistor 224. Larger crystals have a much larger number of leaks than their smaller ones than smaller ones. Therefore, since the larger transistor 223 has a substrate tied to the ground, the ground leakage current dominates the substrate leakage current to _vrr/2 generated by the NMOS transistor 224, and the net current tends to be such a semi-selected word. Line 23 1 is maintained at or near the ground potential. The bit line driver circuits associated with the unselected decode output node 212 operate as described above, and the PMOS transistors 225, 227 are turned "on" to conduct the unselected bit lines 108, 233 to ground. For both decoder circuits, the operation under this forward operation is substantially performed as shown in Figures 4 and 6. Consider the column decoder case, in which the source select bus is decoded and all unselected word lines are driven to the unselected bias line UXL. In the forward mode using the dual decode column decoder, the reverse source select bus is not decoded and all of its individual bus bars are driven to the same voltage as the UXL bus. Thus, the word line driver circuits operate unchanged with respect to FIG. Indeed, a single bias line UXL has been replaced by a plurality of "bias lines" that are driven to the former UXL. line phase (four) voltage and each unselected word line is driven to the bias line. In the case of the row decoder, the source select bus SELB&apos; is decoded in the forward mode and all unselected bit lines are driven to the unselected off-line UYL. In the forward mode of the (four) double decoding row decoder, the reverse source selection (four) row is not decoded, and all of its respective bus lines are driven to the same electrical frequency as the UYL bus line. Thus, the bit line driver 123178.doc •27- 200826114

The circuit operates unchanged with respect to Figure 6. Indeed, a single bias line UYL

Already replaced by a plurality of "bias lines", each bias line is driven to the same voltage as the former UYL bias line and each unselected bit line is driven to the bias line. The decoder circuits described so far are used to implement a memory array in which the memory unit includes a reversible resistor plus a diode. Such a memory cell can be reset using a reverse bias applied across the cell, and for semi-selected word lines and bit lines allows individual word lines and bit lines to be placed under a reset bias condition To provide the ability to reset individual memory cells without having to reset an entire block. The techniques described in Figures 7 and 8 have the advantage of having only a single decoded source select bus, but since the column and row decoders are powered by overvoltage, the voltage requirements for such decoder circuits are even greater. high. The techniques described in Figures 9 and 1B are at the expense of an additional decoding (and/or data dependent) reverse source select bus and a possible add-on area incorporating an array line driver using two decoded source select buses. These voltage requirements are reduced by not supplying overvoltages to the two decoder circuits. This bit line selection circuit is up to twice as large as the bus bar and may be limited in wiring. The word line select circuits may also be slightly larger and have limited wiring (i.e., the word line driver circuits include six additional decoding line poems - six header decoders, and the pM (four) is slightly larger than the earlier circuits). This is the case, but the technology may be more useful than other techniques for a particular embodiment. Above the above-mentioned stylized conditions, you can't explain the forward mode, where the voltage applied to the selected location line is #vp _ ^ and the battery is VPP. The forward mode is also applied to a read mode of 123178.doc -28-200826114, wherein the selected bit line is driven to a read voltage Vrd and the selected word line is driven again to ground. Such a read voltage may be a voltage that is much lower than the stylized voltage VPP, and the unselected word line bias voltage VUX and the unselected bit line bias voltage VUB are thus used in the stylized mode The value is reduced. A particular memory cell can be "programmed" using a forward bias mode, and the reverse mode is used to erase the block. Other cells can be pre-conditioned using an initial forward bias programming technique (eg, During manufacturing, but then use the reverse mode to "stylize" and use the forward mode to &quot;wipe π. To avoid confusion with historical usage in stylized techniques, and to fully understand The decoder circuits described so far use the different memory technologies conceived, and three different modes of operation are used to illustrate: read, set, and reset. In this read mode, across a selected memory The cell applies a read voltage VRD. In the set mode, a set voltage VPP is applied across a selected memory cell. In the exemplary embodiment described so far, the read voltage VRD and the set voltage Vpp are Both are positive voltage' and this mode is implemented using a forward decoder mode of operation. In this reset mode, a reset voltage VRR is applied across a selected memory cell. In the exemplary embodiment, the reset voltage VRR is applied as a reverse bias voltage and implemented using the reverse decoder mode of operation. The reset mode is limited using a split voltage technique. The voltage requirements of the decoder circuits drive a selected positioning line to a negative voltage (ie, using a triple well semiconductor structure). Alternatively, the reset mode can be used for 123178.doc -29-200826114 The reset voltage Vrr is transmitted to the selected word line, and the ground is transmitted to the selected bit line. The VUX and VUB voltages are preferably set to approximately VRR/. 2. Many types of memory cells (described below) can be programmed using this reset mode. In the particular technique of memory cell technology, an antifuse in each memory cell is initially in the forward direction. The direction jumps. Then, in the reverse bias direction, "tuning, the resistance of each memory cell to complete the stylization. This will be the case for a once programmable unit. For rewritable cells, the forward direction is used to erase the cells, which can be executed within blocks of various sizes, and then programmed using the reverse mode. The reverse bias is used to reset the selected memory unit. The stylized motor is supplied by a diode collapse. In addition, the bias conditions associated with the programming can be carefully controlled, including controlling the voltage ramp of the selected word line and/or bit line. Additional insights into useful stylization techniques can be found in U.S. Patent No. 6,952,030, which is incorporated herein by reference. A number of stylized operations can be used to program various resistance states, as described in more detail in the applications of the pp. 23- 0049 and 023-0055, the disclosure of which is incorporated herein by reference. The use of tilted stylized pulses is described in the SAND-OimuSO and SAND-01114US1 applications referenced below, and the techniques for fine-tuning the resistance of a plurality of cells are described in the SAND-01117US0 and SAND-01117US1 applications referenced below. . As described above (especially in the context of dual decoded source select lines), the use of reset programming to program a passive component memory cell incorporating a trimmable resistive element provides greater flexibility to allow for a larger array of blocks. Large hours are especially for 123178.doc •30- 200826114. Even within a selected array block (as all have been assumed above), there is no bias in the reset memory mode for the unselected memory cells, so there is no wasted power consumption. The reverse current (Irev) through a cell is independent of the block size. Therefore many blocks can be selected to increase the write bandwidth. In addition, the voltage across the selected memory cells is only half of the programmed voltage' and is safely used for the cells.

It should be noted that in the above, the reset mode illustrates selected and semi-selected word lines and bit lines. For example, in the context of column selection, a given address may not actually be such a semi-selected word line, and this term is an artifact of the multi-headline driver structure. However, in the context of the bit line, such a half-selected 70 line may actually be selected as long as it relates to the row address, but may be biased to an inactive state for the bit line. Instead of the valid state, the port does not need to be "programmed," for the specific data used for the bit line, or because the beta bit 7L line is 'waiting' to be stylized. This happens when the number of bit line decoder headers is less than programmed at the same time. It should be noted, however, that stylized bandwidth concerns suggest configuring a memory array to simultaneously program as many bits as possible to allow the (equivalent) bit to depend on the negative voltage, and the (equal) selected sub-wires are obtained. A positive voltage. In reset stylization (ie, reverse mode), the reference bits for all unselected array lines (no bit lines and word lines) are grounded 1 and quickly solved and both word lines and bit lines are selected. . Again: test the semi-敎 word line and bit line system (4) in the grounding (because of the current: the driver's largest crystal well potential (four) leakage current) said two: the Z it body early electricity (four) f here An additional leakage current is provided between the semi-selected array lines and the unselected array lines, and the array lines are actively maintained at the unselected bias level. This further facilitates that the unselected array lines remain floating at or near the unselected bias potential. Two-dimensional memory arrays are covered, but it is believed that these decoder configurations are particularly useful for a three-dimensional memory array with multiple memory planes. In a particularly preferred embodiment, the memory array is configured such that each word line includes word line segments on respective memory planes of a plurality of memory planes, as described below. Figure 11 is a block diagram of an exemplary memory array. Dual column decoder 3 02 304 generates column select lines for the array, with column select lines spanning array 3 00, as described herein below. In this embodiment, the word line driver circuits (not shown) are spatially distributed under the memory array and alternate by means of individual memory array blocks (two blocks labeled 3〇6, 3〇8). Vertical connections on the sides (one of which is labeled 3 1〇) are connected to the word lines. The illustrated memory array includes two memories, strips "3 18, 32", and further includes four row decoders and bit line circuit blocks at the top, middle, bottom, bottom, and bottom of the array, respectively. 312, 314, 315, 316. Additional strips may also be incorporated as described herein, and each strip may include one or more memory racks. The bit lines within each block are also 2: interlaced As an example, the bit line 322 is associated with (ie, driven and sensed by) the upper row circuit block 312, and the bit line 324 is tied to the bottom row circuit block 3 14 . In an exemplary embodiment, the memory array 3 is a two-dimensional memory array of passive element memory cells formed on the memory planes of the four memory planes. Preferably, a resistor element (as described herein) can be fine-tuned 123178.doc -32-200826114, and can also include an anti-fuse. Each logic word line is connected to each of the four word line layers. a line segment on the word line layer (each with a different memory plane) Correlation) Each strip of memory array 300 is divided into a plurality of blocks, such as block 308. In the particular exemplary embodiment described herein, each memory rack includes 16 brake train blocks, but Implementing other numbers of blocks. In the exemplary embodiment shown, each block includes 288 bit lines on each of the bit line layers for the four bit line layers of the individual four memory planes, thus A total of 1,1 52 bit lines per block. These bit lines are 2:1 interleaved so that the row decoders and data 1/〇 circuits of the top and bottom of an array block are interposed. 576 bit lines are also included. Other numbers and configurations of such bit lines and array blocks, including higher numbers, are also contemplated. Within a selected memory array block, the source selects bus lines XSELN (or One of the reverse source select busses XSELp) is decoded and driven to a valid bias condition by a column of bias circuits, while the remaining bus bars (also referred to as "bias lines") are driven to an inactive condition. (ie one applies to the voltage of an unselected word line). Therefore, a single selected R SEI^. (ie, the column select line, which corresponds to the decode output node 158 in FIG. 3) drives a word line in the selected memory block to a low state, and the other Ν" word lines within the selected block. Drive to an unselected bias level. In other non-selected memory blocks, any individual bus lines of the 3 source and reverse source select bus bars are not driven to be active, so no valid word lines are selected for the active RSEL line. Alternatively, the source and reverse source select busses within the unselected array block may be floated, particularly in the forward mode. 123178.doc -33 - 200826114 Each column selection line spans all memory blocks in the entire memory strip, and each pair of blocks in the strip (and more than two, each located in the second and last block) The RSEL line, such as the “external column line”, may also be referred to as the “global column line” and may also correspond to the column decoder output nodes referenced herein. Additional details of operations, eccentric conditions, floating conditions, operating modes (including reading and stylized modes), and the like are described in the aforementioned U.S. Patent No. ◎, Milk No. 丄 and additionally stated in christopher L Petti U.S. Patent No. 7, pp. 54,219, entitled &quot;Crystal Layout Configuration for Tightly Spaced Memory Array Lines&quot;, the entire disclosure of which is hereby incorporated by reference herein in Ε· Scheuerlein et al., U.S. Patent Application No. 11/146,952, filed on June 7, 2005, entitled "Decoding Circuit of Poetry Non-Binary Memory Line Driver Group" as a US Patent Application public Case No. 2006-022^02 was promulgated on October 5, 2006, and its full disclosure is incorporated herein by reference. To speed up the selection of a global column line, the RSEI^^ is based on two hierarchical columns. Select decoders 3 〇 2, 3 〇 4 (also referred to as global domain type decoders 302, 304 &quot;), each located outside the array on the left and right sides of the array strip, and driven at both ends thereof. The hierarchical decoder structure reduces the size of the global column decoder 302 to improve array efficiency. In addition, a reverse decoding mode can be conveniently provided to obtain improved test capabilities, such as the step-by-step instructions on July 6, 2006. The United States arrested the application for the publication of the second paragraph 6_6 (promulgated by H45193, US application No. 11/026'493 filed on December 3, 2004, 'Kenneth K· So et al.' The decoder circuit, 123178.doc -34- 200826114 is incorporated into its integrated circuit memory array and related operating methods.

The contents of Part (4) are incorporated herein by reference. The dry circuit for such a hierarchical decoder can be used... M Λ1 See US Patent Application Bulletin No. 2006- 0146639 Α1, Luca G Fas〇li牦, • m〇 等h, etc. Apparatus and method for hierarchical decoding of a dense memory array using a multi-level multi-head decoder, the entire disclosure of which is incorporated herein by reference. In the particular material sheet described herein, the exemplary four-yard encoder circuit includes four &quot;select&apos; bias lines and - single-unselected bias lines. The basic principle of this designation is because the decoder head couples its output to a &quot;selected&quot; bias line when selecting the input of a given decoder head (i.e., driving to a valid level). However, 'this does not imply that all four of the heads shown drive their individual outputs to - reflecting the level at which the output is being selected, since only one of the selected bias lines is suitable The actual bias voltage is selected under the condition of a selected output and the remaining three selected bias lines are biased under conditions suitable for a non-k output. The &quot;selected&quot; for a multi-head decoder, the bias line is described herein as a source selection bus, but similar operations, unless otherwise noted. Some embodiments also A second such bus is included, which is a &quot;reverse source selection bus&quot; instead of a single unselected bias line. Conversely, if the input node for the multi-head decoder is invalid or unselected , then all such heads drive their individual outputs to an associated, unselected, 1 bias line (or a separate bus select bus bar individual bus line for many useful embodiments, such The selected bias lines can be combined into a single bias line shared by all of the heads of the multi-head decoder. 123178.doc -35- 200826114 Similar or related word line decoder structures and techniques, including additional levels of such decoding, for The bias circuit blocking and related support circuits of the decoding busses (for example, XSELN and XSELP) are further described in R〇y E.

U.S. Patent No. 6,856,572 to Scheuerlein and Matthew P. Crowley, entitled "Multi-head Decoder Structure Using a Memory Array Line Driver with Dual-Purpose Driver Devices", the entire disclosure of which is incorporated herein by reference, U.S. Patent No. 6,859,410 to Scheuerlein and Matthew P. Crow, entitled "Specially Suitable for Interconnecting Tree-Decoder Structures with Very Small Layout Spacing," the entire disclosure of which is incorporated herein by reference. Figure 12 is a top plan view showing one of a word line layer and a bit line layer of a three-dimensional memory array in accordance with a particular embodiment of the present invention. Other word line layers and bit lines can be implemented using the layers shown and share the same vertical connections in some embodiments. Display memory blocks 332, 334 include a plurality of bit lines 333, 335, respectively, and have 2: 1 interleaved word line segments. The vertical connection to one half of the word line segments for a block is to the left of the block (e.g., word line segment 337 and vertical connection 339), and to the other word line segments for the block Half of the vertical connections are to the right of the block (eg, word line segment 336 and vertical connection 340). In addition, each vertical connection is used in a block of two adjacent blocks for a word line segment. For example, vertical connection 340 is coupled to word line segment 336 within array block 332 and to word line segment 338 within array block 334. In other words, each vertical connection (e.g., vertical connection 340) is shared by a word line segment within each of the two adjacent blocks. However, if desired, the individual ''outside' vertical connections for the first and last array blocks 123178.doc-36-200826114 are only used for word line segments within the first and last array blocks. For example, if block 334 forms the last block of a plurality of blocks of a memory array (or a self-contained rack), then its external vertical connection (eg, vertical connection 344) may be used only for the block. The word line segment 342 within 334 is thus not shared by the second word line segments throughout the other portion of the array. By the parent fault, the vertical line is separated by two lines between the individual word lines and the self. This is particularly advantageous because the word line spacing available for many passive element memory cell arrays is significantly less than the distance between many channel structures that can be used for forming vertical connections. Moreover, this can also be reduced. The complexity of the small word line driver circuit is implemented in a semiconductor substrate underneath the memory array. Referring now to Figure 13, a schematic diagram is shown showing a fragmented word in accordance with a particular embodiment of the present invention. Configuring one of the three-dimensional memory arrays. Each word line is formed by one or more word line segments of at least one (and advantageously a plurality of) word line layers in the memory (four) column. For example, a first word line The word line segment 36〇 placed on the word line layer of the memory array and the word line segment 362 placed on the other word line layer are formed by the word line segments 360 and 362. A vertical connection 358 is connected to form a first word line. The vertical connection 358 also provides a connection path to a driver device wz placed in another layer (e.g., within the semiconductor substrate). A column of decoders (not shown) The decoded output 352 traverses substantially parallel to the word line segments 360, 362, and sometimes the device 172 combines the word line segments gw (4) to a substantially parallel slant of the word line segments. Decoding bias line 167 (e.g., source select bus XSELN), sometimes translating 4, etc. pre-wire segments 360, 362 to a decode bias line 2〇3 (eg, as shown The reverse source selection bus (XSELp) shown in Figure 9. Also, the member shows the sub-line 3 61,3 63, which line is connected by a vertical connection 359 to open a second word line and to provide a connection path to the word line driver circuits 175 and 176. Another decoded output 353 from the column decoder is sometimes coupled to the decoded source select line (i.e., bias line) 167 via the ping 176, which is sometimes transmitted by the device 175. The equal word line segments 361, 363 are coupled to the decode bias line 2 〇 3. Although this illustration conceptually describes a sample live array configuration, many specific embodiments are described below, including variations of the illustrated grievances, and include It may be suitable for a particular embodiment, but not necessarily for the details of all embodiments. In a particularly preferred embodiment, a six-word line driver is utilized. Six word lines associated with the six-word line driver circuit Shared by two adjacent memory blocks as described in the aforementioned U.S. Patent No. 7, G54, 219. In other words, a given six-word line driver decodes and drives six of the blocks in two adjacent blocks. Word lines. As the figure implies, the adjacent blocks can be considered to be on the left and right sides of the associated word line drivers respectively. However, in a better specific implementation, the 'itb class multi-word line driver f quality The upper system is placed in these垂直] Below the block, and only the vertical connections of the word lines are fabricated between the blocks of the Haihai area. Covering with non-mirror arrays (eg, a word line layer is only associated with a single bit line layer) Specific embodiments of the invention, such as the US towel application No. 11/G95, 9G7 filed on March 31, 20G, by (3) α? "01丨 et al., entitled "&quot; for use in a memory array and The apparatus and method for the redundancy of a human block is described in U.S. Patent No. 7,142,471, the entire disclosure of which is incorporated herein by reference. In particular, Figure 15 shows a 4-bit line layer with a 16-bit row decoder on top and bottom sides of an array block. This figure shows that the 4-bit line on each layer of the 4-bit line layer is combined by a single 16-head row decoder to the top data bus (description 4 1/〇 layer), and is equally in the same 4 bits. The 4-bit line on each layer of the meta-layer is coupled to the bottom data bus by a single "head-to-line decoder" (but in this description, the 16 selected positioning elements of the two groups are located at the same Within the array block, other specific embodiments are contemplated, such as a two-bit line layer sharing a word line layer, to form a two-memory array. In the following figures, the use of weight is illustrated. Various specific embodiments of stylized (ie, reverse dusting stylization). Therefore, some definitions are used in turn for this part of the content. The term &quot;setting&quot; should be considered as a single forward bias ( Or group of memory cells to cause a lower resistance through each memory cell. The term &quot;erase&quot; should be considered as a forward biasing of a memory cell block to cause a change through each memory cell. Low resistance. Finally, the term &quot;reset, should be considered as a Biasing a memory cell to cause a higher resistance through each such cell. (For other embodiments described herein, such definitions may not apply to a particular one. The reverse bias condition across a memory cell increases the resistance of the cell.) Referring now to Figure 14, the &quot;memory array 370 includes a first strip 371 and a second strip 372 ° the strip 371 The system is also labeled as the strip G and the second strip 372 is also the center of the main D. Strip 371 includes two memory racks ΒΑγ-〇〇 and ΒΑγ-〇ι. Each such memory rack includes a plurality of array blocks (e.g., financial memory blocks 123178.doc - 39 - 200826114 body array blocks). Although this exemplary memory array 370 is shown to include two memory strips, each having two memory racks, other numbers of strips and racks are also contemplated. The first memory rack BAY_00 represents another memory rack. A total of 16 memory array blocks, two of which are labeled 374 and 375, each having a sense amplifier placed under the memory array (eg, within the layers of the semiconductor substrate, but one or more memories) A plane can be formed on a dielectric layer formed on the substrate layers). A top row decoder circuit 380, a top data bus 373 and a top bit line selection block span the six array blocks of the rack and exit the same 7G from the top of each array block Line associated. A bottom row decoder circuit 379, a bottom lean bus 378 and a bottom bit line selection block 2 spanning 16 array blocks of the rack and exiting from the bottom of each array block The bit line is associated. It will be appreciated that the top row decoder circuit 380 can be illustrated as being "above" the array blocks, and the bottom row decoder circuit 379 can be illustrated as being "in the &quot;below&quot;. The orientation of the circuit blocks shown in the schematic diagram. Such locations may also be described as &quot;one side&quot; and &quot;opposite side&quot; in the array blocks (but this is generally acknowledged to be a horizontal substrate for implementation thereon) In addition, the directional term &quot;North&quot; and, "South" is a convenient term used to describe the positional relationship of various circuit blocks. In contrast, 'in a particular embodiment, a memory array can be formed on a substrate" and various circuit blocks are illustrated as being in a memory array &quot;below&quot; as applied herein, on a substrate or a memory Array blocks (both of which are 123178.doc -40-200826114 generally having a planar physical property), above &quot;or &quot;lower&quot; relative to - perpendicular to such substrate or memory plane In terms of the surface, in Figure u, 'Although the bottom row (four) can be described as "below" in the array block, such a stone is not fixed under the memory array (ie, more sin Near-substrate). Subtracting 'can be assumed to be within the boundaries of the array block and described as under the array block "below" or "below" the inductively amplified block (labeled SA) To convey the location and structural relationship of such entities.

/ In the context of this manual and the various diagrams, it should be clear that the above &quot;and&quot; In a particular exemplary implementation, the bit line decoder is a (6) decoder that simultaneously selects a 16-bit line on the top side of the --memory array block. This &quot;select&quot; relates to row decoding, not necessarily implying that all 16-bit lines are actually stylized at the same time. Preferably, the sixteen selected bit lines are arranged on each of the four bit line layers to exit the four adjacent bit lines of the array at the top (or at the bottom of other decoders). The sixteen I/O lines of the top data bus 373 traverse all of the sixteen blocks horizontally. Such a bus bar corresponds to the above-mentioned SEL]B bus bar. The bus lines of the individual bus bars of the data bus 373 are coupled to the individual of the sixteen sense amplifier circuits distributed among the sixteen blocks shown. The data bus bars of the sixteen data bus bars can also be lightly coupled to an associated bias circuit (ie, a reset circuit) that can be used to properly bias such a mode of operation during a particular mode of operation. "Select" the individual bit lines within the 16 bit lines. For example, for a reset mode of operation, the reset circuit is based on the data bits for the bit lines of the 16-bit lines, and also allows the number of simultaneous programming lines according to 123178.doc -41 - 200826114 (Of course means a stylized unit coupled to a particular bit line) to properly bias the &apos;select&quot;16 bit lines of the desired stylized bit line and the undesired stylized bits Yuan line. The bias circuits can be deactivated and cause them to exhibit a high impedance during a read mode of operation when the selected bit lines are coupled to the individual sense amplifiers via data bus 3 73 (ie, the SELB bus) . The sixteen 1/〇 lines of the bottom data bus 378 traverse all of the sixteen blocks horizontally. Such busbars correspond to the other SELB busbars described above, which are used to exit the bitlines at the bottom of the array (it should be remembered that the bitlines are 2:1 interleaved). As previously described, each of the individual bus bars of the &amp; data sinking pawl is coupled to one of the sixteen sense amplifier circuits distributed among the sixteen blocks shown. In each group of 16 blocks = one rack, there are 32 inductive amplifiers connected to 32 selected positioning elements. In reading the mode &lt;, all of the selected positioning elements can be configured to fall within the sixteen blocks, or can be otherwise configured, as will be explained herein. The sense amplifiers can be conveniently implemented under the memory array block, but the data bus lines 373, 378, the sixteen header select decoders (ie, the bit line select blocks 381, 382) And a small portion of the row decoders 379, 380 are preferably implemented external to the array block. Additional details of the use of a row decoder configuration can be found in U.S. Patent Application Serial No. 1 1/095,907 (U.S. Patent No. 7,142,471), and the aforementioned U.S. Patent Application Publication No. 2006-0146639 A1. In a stylized mode, the total number of stylized circuits can limit the number of simultaneous memory cells. In addition, along a single selected location line or word 123178.doc -42- 200826114 =, the number of streams can also limit the number of memory cells, and can be reliably stylized at the same time. 々 In each row &amp; _ non-targeted structure, if two bits of the same line in the same array are solved, a total of 32 bit lines are selected. The mosquitoes each selects four bit lines (ie, four bit lines from the respective memory planes) in each of the four bit line layers to select on each memory plane. The word line segment shall support mm for a total of eight selected memory cells as shown in Figure 13 to show: individual word line segments for each layer. The four memory cells of the selected memory cells are associated with a bit line that exits north, and the other four selected cells are associated with a southbound exit bit line. All 32 cells of the selected memory cells will be driven by the same word line driver circuit, but each memory cell of the selected memory cells is driven by its own bit line driver circuit.

As suggested above, even though the total programmed current for 32 cells can be supplied by the integrated circuit, the programmed current for the eight selected memory cells can cause an unacceptable along the selected word line segments on each layer. The voltage drop. In addition, the selected word line driver circuit may not be able to use a receivable voltage drop to drive such current. In the reset stylized mode, a reverse bias is applied to each of the selected passive memory cells, thereby resetting the modifiable resistive material to a high resistance state to program the user data. One or more bit lines within a block may be selected for simultaneous programming, and flow to the selected bit line as the bits of the bit are reset to a higher resistance state The current of the selected word line is significantly reduced, and the remaining bits are seen due to the reduced word line drop. 123178.doc -43- 200826114 'It is easier to stylize the bit changed first. Higher voltages are at a significantly higher voltage. Thus, the state is changed, so that the help of the more ''stubborn'' is stylized. Nonetheless, but 32 selected memory cells reside in the phase

One of the individual. It is unacceptable in the same array area in the figure. Thus, the two differentizations each use the two data bus array blocks 374 to be cross-hatched to indicate their choice for resetting the stylization. One of the outputs of the top row decoder 380 for block 374 is active, thereby coupling the 16 selected positioning element lines to the top data bus 373 (represented by the arrows from array block 374 to data bus 373) . In addition, array block 375 is cross-hatched to indicate that it is used to reset the stylized selection. One of the output of the bottom row decoder 379 for block 375 is also valid, thereby consolidating the 16 selected positioning line handles to the bottom data bus 378 (from the array block 375 to the data bus 3 7 8 Before the head indicates). A single column 377 is selected by the global column decoders (not shown) on either side of the memory array, which drives a global column select line across the entire strip 371. Such a global column select line corresponds to the decode output 158 of the column decoder circuit shown in FIG. A multi-word line driver circuit is enabled (by appropriate bias conditions on its source select bus and reverse source select bus) to drive a selected word line 376 and region within block 374 A selected word line within block 375. Since such word lines are shared within this exemplary embodiment, such a selected word line driver circuit drives word lines within two blocks 374, 375. The entire programmed current is still initiated by this selected word line driver 123178.doc -44- 200826114 circuit, but now the current along each selected word line segment is halved, since each word line segment now only supports 4 selected memories unit. It should be noted that the lower-higher or lower word lines within blocks 374 and 375 are driven by the two separate word line driver devices and the peak current in either of the word line driver devices will be approximately half. The shared word line driver can be completely avoided by selecting to configure the data page in a more complex block configuration corresponding to odd or even word lines. For example, assume that the even word line is driven from the left side of the -feed column block and the odd word lines are driven from the right side of a given array block. When an even word line is selected within a given array block, the block to the left can be selected at the same time, and when an odd word line is selected in the array block, the block to the right can be selected at the same time. In this case, no selected word lines appear in an unselected array block. In an alternate embodiment, the data page to be written can be configured to avoid sharing the word line driver. In the dual data bus example described above, each memory block is associated with two data bus bars 373, 378. In a different memory cycle, other bit lines associated with array block 374 will be coupled to bottom data bus 378, while other bit lines associated with array block 375 will be coupled to the top data bus 373. In this and other embodiments, for optimal performance, the blocks selected for reading in a given rack are different than the blocks selected for reset. A single block is selected for reading at a time, but two blocks are selected for reset. Both data busses are valid for reading, but accessing a single block is different from resetting the above. There are various other dual data bus configurations that offer similar benefits. Figure i5 shows a § reciprocal rack 400, wherein the odd-numbered memory blocks are only associated with a first data bus of 123178.doc -45-200826114, and the even-numbered memory blocks are only Associated with a second data bus. The odd array block 4〇6 is associated with the first data bus bar 402, which is represented as a bit line selection block 4〇8, and the even array block block 407 is associated with the second data bus bar 4〇4. Union. The two memory array blocks (e.g., array blocks 406, 4〇7) are simultaneously selected, each coupling its selected location line to one of the data bus bars (denoted as individual bold arrows 410, 412). Figure 16 shows a memory rack 420 in which each memory block is associated with a first data bus 422 and a second data bus 424. In a non-memory cycle, the first array block 426 is selected and positioned to coordinate the line coupling (bold arrow 430) to the first data bus 422, while the second array block 427 is simultaneously selected and The selected location line is coupled (bold arrow 432) to the second data bus 424. In another memory cycle, the first array block 426 can be selected and its selected location line coupled to the second lean bus 424, while the second array block 427 is simultaneously selected and positioned to locate the line. Engaged in the first data bus 422. Figure 17 shows a memory frame 44A, wherein each memory block is associated with a first data bus 442 and a second data bus 4, all of which are located in the same array block. side. The first array block 446 is associated with the first data bus 442 by a first bit line selection block 449, and is also associated with the second data bus by a second bit line selection block 448. 444 is associated. In the exemplary memory cycle illustrated, two memory array blocks (e.g., array blocks 447, 446) are simultaneously selected, each coupling its selected location line to the first and second data sinks. 123178.doc -46- 200826114 444 (expressed as individual bold arrows 450, 454). Referring now to Figure 18, a memory bay 460 is depicted which is similar to the memory bay BAY-00 described above except that in this exemplary embodiment, two simultaneously selected array blocks 462, 464 are not adjacent. In a memory cycle, array block 462 is selected and selected for location line coupling (ie, bold arrows) to upper data bus 466, while array block 464 is simultaneously selected and positioned to locate the line. Coupling to the lower data bus 468. This organization is particularly useful when the word lines are not shared between adjacent memory array blocks, but can be used even if such word lines are shared. In this case, a selected word line within a selected block will also extend into the adjacent memory block. In the specific embodiments of the illustrated embodiments, more than one block is selected for resetting the stylization. A reverse bias is applied to the passive component cells within the selected array block (ie, selected &quot;sub-array)), thereby resetting the modifiable resistive material to a high resistance state to program the user data Within the array. This may be done at high bandwidth for several reasons. First, by selecting more than one block for stylization, the number of simultaneous stylized memory cells can be increased beyond that imposed by a given wordline segment. Or even impose such restrictions on the scorpion driver circuit. More than two selected array blocks can be selected as long as the data bus reaches each such block. In addition, the stylized direction helps to allow the program. A larger number of cells. In other words, since some of the bits of the stylized bits are reset to a higher resistance, the amount of current flowing from the bit line to the word line is significantly reduced, so the winning bit is due to Decreasing word line voltage drop and seeing a slightly higher voltage. For 123178.doc -47- 200826114 at a given maximum stylized current 'may be from low to high resistance ratio from high to low resistance reliable Stylizes more bits. It also contributes to a high-bandwidth stylized set of bias conditions on all of the large number of unselected word lines and bit lines. Since all of the lines are kept grounded, there is no selection and cancellation. When the array block is selected, the boost bias voltage has a large delay associated with the unselected array arrays, and there is no large current transient current that must be used to rise and fall in such array blocks. In this reset stylized configuration, even the unselected word lines and bit line biases in the selected memory block are grounded (ie, float to the left when using a particular exemplary decoder structure). In a specific embodiment, K is a memory wafer such that each rack has its own read write circuit group and at least the data read/write circuit is connected to the bit line selection circuit. Row. This busbar extends across the width of the rack, or in other words, "crossing," a group of blocks. It may be stored on the top side of the block - the row decoder and the bottom side of the block - the second line of decoders, so there are two Data bus. In a particular embodiment, there may be two sets of read: write circuits associated with respective bus bucks. Preferably, a particular data page is spread across all racks to obtain the highest bandwidth. This point is described in the exemplary embodiment shown in Figure 14 by __ pairs of selected array blocks in each memory frame. Preferably, the selected locations are 八孙八士,疋位Two blocks distributed in a rack, a block having the row decoders of the row decoders and the associated bit lines of the data sinks and the second blocks It is selected by another line and the greedy "flow bar", so that each rack doubles the bandwidth, but the current in any word, the film &amp; the moving current does not change. In addition, the 123178.doc in a selected row position -48- 200826114 The bit line - or many of them are also selected for resetting the stylization. At the same time, the number of processes may be limited by the current flowing from the selected bit lines in a block to the shared word line. However, this limitation is mitigated in a method in which some of the bits of the bit are reset to a higher resistance state, and the current through the 6 reset &quot;single 70 is reduced, along the IR of the shared word line segment. The drop is reduced and the remaining bits get more voltage to facilitate their reset. The preferred lines in each selected block (4) are all on the same column ^, thereby eliminating the decoding implication, since the global column decoder current does not need to be k-ized to support this point. Preferably, the simultaneously selected blocks are adjacent, in particular, in the case where word lines are shared between adjacent blocks. The decoding is configurable such that for any selected word line shared between two adjacent blocks, the two adjacent array blocks can be configured to simultaneously select the array block. For example, a given word line driver placed between the second and second blocks drives a common word line within the first and second blocks (both simultaneously selected). The next word line (assuming it is in the left and right sides of the array blocks in a 2: 丨 interleaved form) will be driven by an array of line drivers between the second and third array blocks, the array areas The block can also be selected as an array block. This avoids processing the selected word line from extending into the adjacent non-selected array block. When using the reset stylization, each memory unit is set back to a low resistance state by the "set", operation mode, which can be used to rewrite new data, or by applying a positive one time. To bias a bit to a bit, bite a number of bits in a data page or a erase block to erase a group of bits. Efficient erase can be selected by selecting multiple bit lines in a block Or a plurality of word lines, and set the special element to a low resistance. The current limiting circuit in the bit driver drive 123178.doc -49- 200826114 limits the total current flowing to the common word line. The selected memory cell technology, the relative number of set currents and reset currents, and the amount of u-cell leakage current can be used to set or erase operations by selecting fewer blocks for reset (ie, stylized). The selection of the resistive material is to form a diode polycrystalline germanium material. An antifuse ('AF'') can be serialized with the polycrystalline germanium diode, and the antifuse is in a stylizing event during a formatting step in manufacturing. Before the jump. This anti-fuse is used to limit the setting. The maximum current of the meta-conduction. As described above, preferably, the memory array includes a segmented word line architecture (as shown in Figures 12 and 13), and is preferably a three-dimensional array. In a particular embodiment, The word lines on a given word line layer are associated with bit lines on a single bit line layer, and in a particular embodiment, in a so-called "semi-mirror" configuration - the word lines on a given word line layer are shared between a two bit line layer (i.e., a single word line layer defining a two memory plane and a two bit line layer). Such a memory array structure further illustrates In the aforesaid U.S. Patent No. 6,879,505, the description of the various decoder circuits has been focused on a single array block. It should be recalled that each decoder has been in the _ source selection bus and for some embodiments - The background of the reverse source selection bus is described. The word line decoding hierarchy can be regarded as relatively direct. The source bus and the untwisted (four) line or the reverse miscellaneous selection confluence (4) are decoded based on the address information, and according to which array area Block system is valid _. Ben The other column decoding circuit has been referenced elsewhere. The (other) individual source selection bus and/or unselected bias line for the word line associated with the unshirted array block can be used. 123178.doc • 50- 200826114 Floating to the left. With respect to these row decoder configurations, a hierarchical bus configuration can be used to provide efficient routing of read/write data and effective biasing of bit lines within selected and unselected array blocks. A useful hierarchical bus configuration is illustrated in the context of the dual source select bus decoder shown in Figures 9 and 10, but these configurations are adjustable for use with other decoder specific embodiments. In the read and set, an exemplary hierarchical bus arrangement provides an appropriate bias on the SELN bus for a selected array block and causes the SELN bus of the unselected array block to float. This helps to reduce the undesirable power consumption in the array blocks within a selected one of the selected array blocks. The unselected word lines in a selected array block are biased at a relatively high voltage VUX (e.g., VPP_VT), and under a common word line architecture, the unselected word lines also extend to adjacent The selected array block (i.e., half of the word lines within the unselected array block are shared with the selected array block). The unselected locating elements within the adjacent array block are preferably biased at the unselected locating element line voltage VUB (e.g., ντ). This is a waste of power due to leakage current through unselected memory cells. The other half of the word lines in adjacent unselected array blocks float so that they leak until the VUB voltage, so the leakage power is minimized for half of the unselected cells. The exemplary hierarchical bus configuration also provides a vehicle and a long SELN.path&apos; that spans a number of blocks to reach the reset data drivers distributed under the array blocks. The four exemplary hierarchical bus arrangements are described in the next four figures. Referring now to Figure 19, a bus arrangement 500 is illustrated that includes three memory array blocks 502, 504, 506 that represent all of the array blocks within a rack. Although only three array blocks are shown, the incremental nature of the configuration and its extensibility to the number of any array block should be clear. The individual SELN bus segments for each of the array blocks are displayed. As used herein, a busbar segment is only a busbar that is smaller than other such busbars, while in other embodiments (described below), multiple busbar segments can be coupled together.

To form a single larger bus. In the undefined mode, the SELN busbar segments for a selected array block are coupled to a longer GSELN busbar that spans the entire memory bay by a coupling circuit 5〇8. The coupling circuit 5〇8 can be as simple as 16 electrons each coupling a different SELN bus line to an individual GSELN bus line. This coupling circuit 508 is activated by a control signal EN_GSELN which is effective for the selected array block (described below) in the set mode or in the reset mode. During this set mode, the GSELN busbar is coupled to the unselected location line voltage VUB (i.e., the busbar lines of the GSELN bus are coupled to this voltage). The individual EN-GSELN control signals for the unselected array blocks are active, and the individual coupling circuits 5〇8 are turned off, thereby allowing individual SELN bus-segment segments to float as needed. In the reset mode, the individual En-GSELN control registers for all of the array blocks are active and the individual coupling circuits 5〇8 are turned on to switch the individual selln bus segments to the GSELN bus. This point provides write data to all array blocks' regardless of which block is selected. The SELB bus is driven to the VUX voltage (e.g., ground) to provide unselected positioning element bias conditions 123178.doc -52 - 200826114 to reset the stylization. This is a relatively simple circuit configuration, requiring only an additional 16 global lines (GSELN) and 16 additional transistors per array block (coupling circuit 508). Disadvantages (at least with respect to other embodiments described below) include a relatively high capacitance on both the SELB and SELN busbars. The capacitance on the SELB bus is always present, but only during a read cycle, and when all of the SELN bus segments are coupled to the global bus GSELN, the combined bus transfers are reset during this time. Data information, the higher capacitance on the SELN bus is present during this reset mode. In certain other embodiments, the reset mode can be configured with the entire non-negative voltage without dividing the reset voltage VRR into -VRR/2 and +VRR/2. In this case, the unselected word lines and bit lines are biased at the midpoint (now VRR/2). Therefore, when coming out of the reset mode, the discharge rate of the lines should be carefully controlled to avoid excessive current surges during discharge. Referring now to Figure 20, another embodiment is described in which the individual SELN busbar segments are coupled together to form a single larger busbar that spans the entire memory bay. In the set mode, the SELN bus for a selected array block is coupled to a single bias line VUB by a coupling circuit 532 that spans the entire memory frame. The coupling circuit 532 can be as simple as 16 transistors, each coupling a different SELN bus bar to the VUB bias line (which is coupled to a suitable bias circuit, as shown). The coupling circuit 532 is enabled by a control signal BLATVUB that is active for the selected array block when in the set mode. For the unselected array regions 123178.doc • 53- 200826114, the individual BLATVUB control signals are disabled and the individual coupling circuits 532 are turned off&apos; thus floating individual SELn bus segments as needed. In the reset mode, the SELB bus is driven to the VUB voltage (e.g., ground) to provide an unselected positioning element bias condition for resetting the stylization. In addition, the individual SELEN busbar segments are coupled together by a coupling circuit μ3 to form a single busbar spanning the entire memory frame, the memory chassis being coupled to the reset circuit for The combined bus provides a reset data negative &quot; one of the HELN SELN bus segments can be coupled to the reset circuit by a bus bar 53A. In a particular embodiment, a coupling circuit 535 can be used to provide a connection to the reset block in RESET mode. This is a relatively simple circuit configuration in which only one additional bias line (VUB) &amp; 32 additional transistors are required per array block (the coupling circuits 532, 533). Similar to the previous embodiment, there is still a relatively high capacitance on the two SELB and SELN busbars. Referring now to Figure 21, a busbar configuration 55A is described which incorporates features from two prior embodiments. In SET mode, the SELN bus segment for a selected array block is coupled to a VUB bias line across the entire memory frame by a coupling circuit 554, which is coupled by a control signal BLATVUB. (4). For unselected arrays, the individual BLATVUB control signals are not valid, and the individual coupling circuits 554 are turned off, thus allowing individual SELN bus segments to float as needed (since the EN-GSELN signal is also inactive in SET mode). In the reset mode, the 'single-slide control signal for a selected array block is valid, so a separate coupling circuit 552 is turned on to couple the individual 123178.doc -54 - 200826114 SELN bus segment to the GSELN. Bus bar. The individual EN-GSELN control signals for the unselected array blocks are invalid, and the individual coupling circuits 552 are turned off, thereby causing individual SELN bus segments to float. This configuration only provides write data to this (etc.) unselected array block, which significantly reduces the total capacitance. The SELB bus is driven to the VUX voltage (e. g., ground) to provide unselected positioning element bias conditions for reset stylization. This circuit configuration requires 17 additional lines (VUB bus and GSELN bus) and 32 additional transistors for each array block (the coupling circuits 552, 554). Unlike these prior embodiments, this configuration provides for significantly reducing the capacitance on the SELN bus, since the individual SELN bus segments for unselected array blocks are not coupled to the GSELN bus. There is still a fairly south capacitance on the SELB bus. Figure 22 depicts another hierarchical bus arrangement, this time using only a single global selection bus GSEL across the memory frame and dividing the SELB bus into a separate SELB bus segment for each array block. For a selected array block, individual SELB busses or individual SELN bus segments are coupled to the GSEL bus. During the SET mode, the selected block SELB busbar segment is consuming to the GSEL busbar, and the selected block SELN busbar segment is coupled to the VDSEL. bias line (which transmits an appropriate bias during SET) The unselected positioning element line bias condition VUB generated by the circuit, as shown). The unselected block SELN bus is floated to the left. During the RESET mode, the selected block SELN bus segment is coupled to the GSEL bus, and the selected block SELB bus segment is coupled to the VDSEL bias line (during rESET) It passes the unselected positioning element line bias condition νυχ). The unselected block SELN bus is again floated to the left. This configuration is the most complex of the described configurations, requiring 17 global lines per array block (ie, spanning the memory rack) and 64 additional transistors, and may require more layout in some embodiments. area. However, it also provides low capacitance on the SELB and SELN busbars because it allows for higher efficiency and provides a one-pole modular block design. Moreover, larger memory racks can be implemented without significantly increasing the capacitance on the SELB and SELN busbars. In another embodiment, the row decoder circuits can be modified to provide a separate row decode output for the NMOS and PMOS transistors of the bit line driver circuit, so that the bit line selector can be set at High impedance and sadness. However, this configuration will significantly increase the bit line selector area as well as its own row decoder. Referring now to Figure 23, a data circuit is illustrated that includes separate blocks for the set, reset, and read modes. It will be recalled that in the reverse bias mode (i.e., reset mode), the selected positioning elements are coupled to a different SELN bus line (i.e., the reverse source select bus). Here, it is found that a reset driver 61 5 is coupled to the SELN bus 617 (which indicates that the path to any of the four hierarchical bus configurations can be used). Essentially, this table does not ultimately couple to the Sarn bus segment for a selected array block. The slave write data information is received in the &quot;〇 logic6〇[, on the bus 602 is passed to a write latch block 6〇4, and 123178.doc -56-200826114 is passed on the bus to the control logic 60 8 'The control logic then controls the reset driver 61 5 by means of the control line 6丨2. It should be remembered that in this forward mode, the selected positioning elements are coupled to an individual SELB bus line. Since the two SEt and READ modes utilize the forward bias mode, a set driver 614 and a read sense amplifier 613 are simultaneously spliced to the SELB bus bar 616 (which represents any of the above four hierarchical bus bar configurations). Or any other configuration to the path of the SELB bus). The sensing data is passed from bus 609 to a read latch 605 for transfer to I/O logic 601 by bus 603. Various bus bars 606, 6 10 and 611 are provided for a stylized control loop, sometimes referred to as a smart write, which can turn off the stylized current when a meta-system is successfully toggled or set. The bus banks also provide a pre-write read capability to determine, for example, any previous stylized states (e.g., LSB data bits) that should be retained prior to subsequent stylization operations. Such capabilities are further described in the 023-0049 and 023-0055 applications referenced below. A simplified exemplary reset driver 6丨5 and a word line and bit line select path representation of a selected memory cell 638 are depicted in FIG. A word line select path 639 represents the path through the word line driver circuit (i.e., the decoder head) to the circuitry used to generate the decoded source select bus XSELN. A one-element selection path 636 represents the path through the bit line driver circuit and through any of the matching circuits (e.g., the circuits described in the various hierarchical bus arrangement embodiments) to the individual SELN bus bars 635. . A preferred reset method and associated reset driver are described in the SAND-01U4US0 and SAND-01114US1 applications referenced below, in particular to Figure 13 of 123178.doc • 57-200826114. The capacitance of the bit line selection path is precharged before attempting to program a new address selection location line. This can be performed using a higher current than the amount required to actually reset the selected memory cell, but at the appropriate timing, such higher amounts of pre-charging can speed up the pre-charge time without a decisive influence on the memory cells. This precharge is controlled by a precharge line signal pCHGCOL that is passed on control signal 637 to bit line select path 636. A one-line precharge (BLP) current limit circuit 633 and a reset limit circuit 634 are simultaneously provided to control the number of upper bits of the individual bit line precharge and reset current. If the data is such that no reset operation is required, both are disabled by signal 632 and the SELN bus bar 635 is floating. Conversely, 'If the data causes the memory cell to be reset, the disable line 632 is disabled' and temporarily (eg, 200 ns to 5 ns) enables the BLP current limiting circuit 633 to provide a higher level of control current for Such pre-charging, after which it is disabled (by a control signal not shown), causes reset current limiting circuit 634 to supply a lower amount of current for resetting the selected memory cell. Since resetting a memory cell causes it to change from a lower resistance state to a higher resistance state, it is less necessary to perform the inductive reset operation and disable the reset limit 634 since the cell automatically reaches its reset state. shut down. As with the various embodiments described above, many types of memory cells can be programmed using a reverse bias (e.g., the reset mode described above). Such a unit includes a passive component unit having a metal oxide (e.g., a transition metal oxide) and a diode. Other suitable units include such elements of a resistive material within a matrix of diodes. Examples include a programmable 123178.doc -58- 200826114 metallization connection, a phase change resistor (such as GST material), an organic material variable resistor, a composite metal oxide, a carbon polymer film, a broadcast Heterosulfide glass and a Schottky barrier diode containing a migrating atom to change the electrical resistance. The selected resistive material provides one-time programmable (0TP) memory cells or multiple writes to the memory cells. In addition, a polysilicon diode can be used which has a reverse bias stress modified conduction. ‘The useful memory unit for reverse reset operation is described in grant s.

U.S. Patent No. 6,952, 〇 3, issued to Brad Herner et al., entitled "High Density Two-Dimensional Memory Unit"; and also on December 30, 2005; US application by Tanmay Kumar et al. Case No. 11/237,167, entitled "Method of Using Memory Units with Switchable Semiconductor Memory Elements with Trimmer Resistors", April 26, 2007 as US Patent Application Bulletin No. 2007-0090425. A suitable metal oxide memory cell system is shown in U.S. Application Serial No. 11/394,903, filed on March 31, 2006 by S. Brad Herner, entitled "Resistivity Switching Oxide or Nitride" And a multi-layer non-volatile memory cell of the anti-filament." A suitable memory cell system using a phase change material that provides a plurality of resistive states is shown in U.S. Patent Application Publication No. 2〇〇5_ 015 8 9 5 0 'The title is π tandem containing the dielectric layer and the non-volatile memory of the phase change material'. The entire contents of the above referenced disclosures are by reference. Incorporated into this article. Has one Other exemplary memory cells that pass metal oxides (eg, including such oxides with cobalt) and exemplary cells in which the polycrystalline germanium material of the steering element itself comprises a switchable resistive material are described in the above-referenced ΜΑ-163- 1 Application. 123178.doc •59-200826114 In addition, US Application No. 11/125,939, filed May 29, 2005, to S. Brad Herner et al., entitled "Including Diodes and Resistor Switching The rewritable memory unit of the material is disclosed in U.S. Patent Application Publication No. 2006-0250836, issued on Dec. 9, 2006, which discloses the utility of a tantalum oxide (nickel oxide) incorporated into a diode. The memory unit can be rewritten, wherein the resistance of the memory unit can be repeatedly switched from low to high and from high to low resistance. U.S. Application Serial No. 11/395,995, filed on Mar. 31, 2006, entitled,,,,,,,,,,,,,,,,,,, Japanese Patent Application Publication No. 2006-0250837 discloses a οτρ multilayer memory unit that is set using a forward bias and reset using a reverse bias. The entire contents of each of the above-referenced publications are hereby incorporated by reference. In many of the embodiments described herein, the precise bias conditions imposed on each individual bus bar within the data path are independently controlled. The specific voltage and current settings for each of these drivers for setting and resetting the drive can be adjusted for each element of the data path. Thus, a particular memory unit (i.e., "multi-layer" memory unit) having more than two states is contemplated for use with the many structures described herein. Exemplary multilayer memory cells are described in the aforementioned U.S. Application Serial No. Exemplary passive element memory cells and associated non-volatile memory structures that can be used in the practice of the present invention are described in the following documents, the entire contents of each of which are hereby incorporated by reference: s. , titled &quot;Vertical stacking field, programmable non-volatile memory and manufacturing method," awarded GjQhns〇n et al; US Patent No. 6,420,215, entitled "Three-Dimensional Memory Array and Manufacturing Method", awarded N. Johan Knall et al.; U.S. Patent No. 6,525,953, entitled &quot;Vertical Stacking Field Programmable Non-Volatile Memory and Manufacturing Method&quot;, awarded to Mark J〇hns〇n et al; US Patent No. 6,490,218, title For &quot;Su will be a memory method and system for storing multi-bit digital data," issued by Michaei Vyv〇da et al; US Patent No. 6,952,043, entitled "Electrical Insulation Columns in Active Devices" Michael Vyvoda et al; and U.S. Patent Application Bulletin No. 1182〇〇5-〇〇52915, entitled, with high and first impedance states Electric anti-solvent, filament non-volatile memory unit ', filed by S · Brad Herner et al. The following applications (each filed during the same period) describe the memory cell structures, circuits, systems, and methods that can be used to implement the present invention, and the entire contents of each application are hereby incorporated by reference: U.S. Application No. 11/496,985 (Attorney) File No. 10519-141, entitled "Multi-Purpose Memory Units and Memory Arrays", by Roy Scheuerlein and Tanmay Kumar (&quot;10519_141" Application); US Application No. 11/496,984 (Attorney Profile) No. 105 19-150), entitled "Usage of Multi-Purpose Memory Units and Memory Arrays", by Roy Scheuerlein and Tanmay Kumar (''10519-150' application 123178.doc -61 - 200826114); Application No. 11/496,874 (Attorney Docket No. 10519-142), entitled ''Mixed-use memory unit π, applied by R〇y Scheuerlein (''10519-142' application); US Application No. 11/ No. 496,983 (Attorney Docket No. 10519-151), entitled "How to Use Mixed-Use Memory Units", by R〇y

Application by Scheuerlein (&quot;10519-15Γ application); US Application No. 11/496,870 (Attorney Docket No. 1〇519_149), entitled "Mixed-use memory unit with different data status,, by R〇 y

Scheuerlein and Christopher Petti Application (&quot;10519-149" Application); US Application No. 11/497,021 (Attorney Docket No. 10519_152), entitled "Usage Method for Mixed-Use Memory Units with Different Data Status", by Roy Scheuerlein and Christopher Petti Application (π 105 19-152); US Application No. 11/461,393 (Attorney Docket No. SAND-01114US0), entitled "Controlled Pulse Operation in Non-Volatile Memory, , by R〇y

Scheuerlein Application (&quot;SAND-01114US0', Application); US Application No. 1 1/461,399 (Attorney File No. 8 Octopus _ 01114US 1), entitled "Controlled Pulse Operation in Non-Volatile Memory糸, applied by Roy Scheuerlein (&quot;SAND-01114US1,, application); US application No. 11/461,410 (lawyer file number sand 01115US0), titled &quot;High bandwidth first field programmable Memory,,, 123178.doc -62- 200826114 Application by Roy Scheuerlein and Christopher J. Petti (''SAND-01115 US 0'' application); US application No. 11/461,419 (lawyer file number SAND-0111) 5US 1), entitled "System for High-Bandwidth One-Time Programmable Memory", by Roy Scheuerlein and Christopher J. Petti ('SAND-0111 5USln Application); US Application 11/461 , No. 424 (attorney file number SAND-0111 7US0), entitled "Reverse Bias Fine-Tuning Operation in Non-Volatile Memory", by Roy Scheuerlein and Tanmay Kumar (''SAND-01117US0') ; U.S. Application No. 11/461,431 (Attorney Docket No. SAND-01117US 1) entitled "System for Reverse Bias Fine-Tuning Operation in Non-Volatile Memory", applied by Roy Scheuerlein and Tanmay Kumar ( ΠSAND-01117USΓ' application; US Application No. 11/496,986 (Attorney Archive No. VIII-163-1), entitled "Use of Memory Units Containing Switchable Semiconductor Memory Elements with Trimmer Resistors" Method · ', applied by Tanmay Kumar, S. Brad Herner, Roy E. Scheuerlein and Christopher J. Petti (&quot;MA-163-1" application); US application No. 11/461,339 (lawyer file number) 023-0048), titled ''passive element memory array π incorporating reverse polarity word line and bit line decoder, applied by Luca G. Fasoli, Christopher J. Petti and Roy Ε Scheuerlein (π〇23) -0048π Application); US Application No. 11/461,364 (Attorney Docket No. 023-0054), Title 123178.doc -63 - 200826114 Incorporating Reverse Polarity Word Lines and Bit Line Decoders for π Use Method for passive array elements ', applied by Luca G. Fasoli, Christopher J. Petti and Roy Ε Scheuerlein (''023-0054' application)); US application No. 11/461, 343 (lawyer file number 023-0049), titled π is used to read a multi-layer passive element memory cell array, ', applied by Roy Ε. Scheuerlein, Tyler Thorp and Luca G. Fasoli (&quot;023-0049) application); US application 11/ 461,367 (attorney file number 023-0055), entitled ''Method for reading a multi-layer passive element memory cell array', by Roy E. Scheuerlein, Tyler Thorp and Luca G. Fasoli (&quot ; 023-0055" application; US Application No. 11/461,352 (Attorney Docket No. 023-0051), titled π for a dual data dependent bus for coupling read/write circuits to a memory array '', applied by Roy Ε. Scheuerlein and Luca G. Fasoli (&quot;023-0051" application); US application No. 11/461,369 (lawyer file number -023-0056), titled π for coupled reading Double data sharing of the fetch/write circuit to the memory array The use of row '', Ε the Roy. Scheuerlein and Luca G.

Fasoli application ("〇23-0056" application); US application No. 11/461,359 (attorney file number 023-0052), entitled "Incorporating data bus for memory array block selection" Memory array '', applied by Roy E. Scheuerlein, Luca G. Fasoli and Christopher J. Petti (''023-0052'' application); US application No. 11/46 1,372 (lawyer file number) 023-0057), Title 123178.doc -64- 200826114 π is used in the memory array block selection two data bus," by Roy Ε Scheuerlein, Luca G. Fasoli and Christopher J. Petti ( 〇23-0057" Application); US Application No. 11/46 1,362 (Attorney Docket No. 023-0053), titled π Hierarchical Bit Line Bias for Block Selectable Memory Arrays Busbars'', applied by Roy Ε. Scheuerlein and Luca G. Fasoli (, 〇 23-0053); and US Application No. 11/461, 376 (lawyer file number 023 - 0058), titled &quot;Using a hierarchical pattern for block selectable memory arrays The method of bit line bias bus bar &quot;, applied by Roy E. Scheuerlein and Luca G. Fasoli (&quot;023-0058&quot; application). It should be understood that the specific exemplary embodiments shown herein are always in a specific digit. The background of the example illustrates, for example, the number of decoded outputs, the number of decoder heads, the number of bus bars, the number of data busses, the number of array blocks in a memory frame, and the number of memory banks. Other teachings that conform to other design goals are implemented using the teachings of this disclosure. For clarity, not all of the conventional features of the &amp; scheme are described and illustrated. Most memory array designs have a relatively high Uniformity. For example, i usually includes the same number of memory cells per bit line. As another example, the number of primitive lines, word lines, array blocks, and even memory planes is often 2 integers. Power (eg '2n) to obtain simplification and efficiency of the decoding circuit. However, such regularity or consistency is of course not required for any particular embodiment of the invention. For example, For a different number of memory cells, the memory array may include three memory 123178.doc -65 - 200826114 body planes, and the word line segments in the first and last array blocks may be in the number of memory cells or bit line groups Any change in state and many other irregular changes to the general consistency of the memory array design, unless otherwise explicitly stated in the scope of the patent application, even as shown in the specific embodiments described herein, such general rules Sex should not be included in the meaning of any patent independent item. It should be understood that the indications of the top, left, bottom and right are merely illustrative terms for the four sides of a memory. The word line segments for a block may be implemented as horizontally oriented inter-finger word line segment groups, and the bit lines for a block may be implemented as vertically oriented two-finger bit lines Group. Each individual sub-line or group of bit lines can be served by a different decoder/driver circuit on the four sides of the array and a different sensing circuit. As used herein, a column extends across the entire memory frame (if not across the entire strip) and includes a number of word lines. As used herein, a bus or line that generally spans a plurality of array blocks includes almost all of the array blocks, such as spanning all but except the last block (eg, a given bus bar is not coupled to one of the last blocks) Piece). Such bus bars or wires may be placed on the side of the array block or may be placed above or below such a block (i.e., in a direction perpendicular to a semiconductor substrate). As used herein, &quot; coupling a selected location line to a first bus&quot; means coupling each such option bit line to one of the first bus bars corresponding to the bus bar, respectively. As used herein, a word line (eg, including a word line segment) and a bit line generally represent a positive parent array line, and generally conforms to a common assumption in the art that the word line is driven and sensed at least during a read operation cycle.元123178.doc -66 - 200826114 Line. Moreover, as used herein, a &quot;global line&quot; (e.g., a global selection line) spans one of a plurality of memory blocks, but no specific inference should be drawn to imply that such a global line must be horizontal Across the entire memory array or substantially across an entire integrated circuit.

As used herein, a read/write circuit (eg, a set and read circuit) can be used for one or more data bits, and thus can be coupled to a single wire, or can include coupling to separate data bits. A separate read/write circuit of each of the bus bars of one of the data bus bars. As used herein, a “data bus” or data bus&quot;fragment, at least multiple data-receiving information, but not always. For example, such data buss can deliver the same bias information on each bus line of such data bus for a particular mode of operation. As used herein, a global domain can span multiple array blocks without having to span (or span) the entire memory matrix. For example, such a global bus can span a memory rack and does not necessarily span an entire memory bank. Where appropriate, the data circuit may comprise a read/write circuit, a set circuit, a reset circuit, a read circuit or a stylized circuit, one or more or any combination. The ''selected' lines (e.g., selected bit lines within an array block) are used to correspond to such bit lines that are simultaneously selected by a multi-head decoder circuit and each coupled to a corresponding bus bar. Such bit lines may or may not be selected by data or I/O circuitry to actually perform a given read, program, set, reset or erase operation. Example > If a 16-bit row decodes r "select" & couples a 16-bit line to a given bus (eg, SELN bus), then it covers no bit lines, one bit line, More than one of the 123178.doc -67-200826114 bit lines or all of the bit lines of the 16-bit line group may actually receive a selected bias condition suitable for a given mode of operation, while the remaining bit lines are receivable Not &amp; bias conditions. Such bus bars can be described as a &quot;data dependent&quot; bus. In other embodiments, there may be more than one such &quot;selected&quot; bias conditions given Passing on the bus, for example, when the two selected memory cells are programmed into different data states. As used herein, the passive component memory array includes a plurality of 2 terminals. The body is 61, and the body is 7L, each connected to a correlation. Between a connection line (such as a word line) and an associated Y line (such as a bit line). Such a memory array may be an array of two or M planes or may have a plane with more than one memory unit. Dimensional array. This type of memory Having a non-linear conductivity in which the current in a reverse direction (eg, from the cathode to the anode) is lower than the current in the -forward direction. A passive component memory array can be programmed once ( That is, one or two writes to the memory array or a read/write (ie, multiple writes), the body array. Such a passive component memory array can be generally regarded as having a current in the direction of the a direction. The operating element and another component capable of changing its shape, such as a solution wire, an anti-fuse, a capacitor, a resistor element (4), the stylized state of the memory element can be induced current or voltage drop To read. The directionality of the various array lines in each figure is only convenient for simplifying the description of the two-cross line group in the array. As used herein, an integrated circuit memory array is a single-span integrated circuit structure. Rather than one or more of the integrated circuits that are packaged together or closely connected. The block diagram in the text can be used in the terminology of a single node of a connected block. 123178.doc -68- 200826114. However, the library has a new one. Should When required by the background, such a "node" may actually be used to convey one of the eight knives or one of the nodes, or may be used to carry a number of related signals for use, , and an A for a separate conductor (such as a busbar) that forms a digital word or a plurality of other signals of a plurality of 虎5 tigers. Although it is generally assumed that the circuit and the 贯 、 、 、 、 It should be fully recognized, however, that in modern semiconductor design and fabrication, the physical structure and circuitry can be embodied in a computer readable descriptive form suitable for subsequent design, testing, or fabrication stages, as well as the resulting semiconductor integrated circuitry. Regarding the line of a conventional circuit or structure conforming to its specific language, it can be understood that its computer readable codec and table are not interrupted in the medium or combined with a suitable reader to allow the manufacture of the corresponding circuit and/or structure. Refine, test or design. The present invention also encompasses systems including circuits, package modules including such circuits, systems utilizing such circuits and/or modules and/or other memory devices, associated methods of operation, and methods for fabricating such circuits And computer readable media codes of such circuits and methods are as defined herein and as defined in the patent scope. As used herein, computer readable media includes at least a magnetic disk, magnetic tape, or other magnetic, optical, semiconductor (e.g., flash memory card, ROM) or electronic media and a network, wired, wireless, or other communication medium. One of the codes of a circuit may include circuit diagram information, physical layout information, behavioral simulation information, and/or may include any other code that may represent or communicate the circuit. The foregoing detailed description has set forth a few of the various embodiments of the invention. For this reason, it is intended that the detailed description be only illustrative and not restrictive. Variations and modifications of the specific embodiments disclosed herein may be made without departing from the scope and spirit of the invention. It is intended that the scope of the invention, including the claims Therefore, other specific embodiments, changes, and improvements described herein do not depart from the scope of the invention. [Simple description of the map]

The present invention will be understood by those skilled in the art, and many of its objects, features and advantages are apparent. 1 is a schematic diagram of a memory array illustrating selected and unselected word lines and bit lines, and exemplary bias conditions in a forward bias mode of operation. 〃

Figure 2 is a schematic illustration of one of the memory arrays of Figure 1, with exemplary bias conditions in a bias mode of operation. Figure 3 is a schematic diagram of a word line decoder circuit, exemplary conditions under pressure operating conditions. Figure 4 is a schematic diagram of a word line decoder circuit, exemplary conditions under pressure operating conditions. Figure 5 is a schematic diagram of one of the one-line decoder circuits. Example conditions under bias operating conditions. Figure 6 is a diagram of one of the one-line decoder circuits. Example conditions under bias operating conditions. FIG. 7 is a schematic diagram of a fresh-coded circuit of a word line solution of the stone, and FIG. 8 is a schematic diagram of a single-line resolving code as a circuit under the conditions of A and A wide reverse bias operation. ό 明 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一</ RTI> includes exemplary conditions under a reverse bias operating condition for other specific embodiments of 123178.doc-70-200826114. Figure 9 is a diagrammatic representation of a word line decoder circuit having dual decoded source select busses&apos; including exemplary conditions for resetting the stylized reverse bias operating conditions. Figure 10 is a schematic illustration of a bit line decoder circuit having data dependent source select busses, including exemplary conditions for resetting stylized reverse bias operating conditions. Figure 11 is a block diagram showing an exemplary integrated circuit including a three-dimensional memory array, and the integrated circuit includes a global column decoder on one side of the array and a pair at the top and bottom of the array simultaneously Line decoder. Figure 12 is a diagram showing a three-dimensional memory according to a specific embodiment of the present invention.

Interleaved word line segments, wherein a vertical connection to a half of the word line segments for a block is to the left of the block, and a vertical connection to the other half of the word line segments for the block It is on the right side of the block. In addition, word line segments from one of the two adjacent blocks share the vertical connections. Figure 13 is a three-dimensional view depicting a portion of a three-dimensional memory array in accordance with a particular embodiment of the embodiment shown in Figure 12, a block 愧K jn ' in each block of the array block and illustrating the use of two-phase adjacent

The line is coupled to a memory array associated with the memory rack and each of the plurality of memory arrays is simultaneously selected 'one of the two data busses each of which has its individual bits connected to each other 123178.doc -71 - 200826114. —: A block diagram of the system and the body of the body, indicating the other two; one of the two data bus associated with the body frame. The two-array block system is shown as being simultaneously selected, which causes M %fA ^ ^ to couple /, individual bit lines to the individual of the data bus associated with the rack. - Figure-block diagram of a memory rack, indicating that another array of array blocks is displayed as simultaneous /, M each couples its individual bit lines to, and the L-body rack is associated with m^μ^ ^ ^ One of the individual rows of the Bellow Ten Thousand Machines, which are placed on the same side of the memory array block. Figure 18 is a block diagram of a memory rack illustrating another configuration in which a non-adjacent array block is selected to have its individual bit lines 1 associated with the memory rack when the helmet is to be helmeted. One of the two data bus rows 0 Figure 19 is a block diagram of one of the memory racks, illustrating that an exemplary hierarchical depletion configuration is used to provide appropriate conditions for selection on the source selection busbars And the array block is not selected. Field _-a block diagram of one of the memory racks, f-Make another - the exemplary stratum reading code g &amp; the stock provides the appropriate conditions on the source selection m b for selected and unselected array blocks . Figure 21 is a block diagram of one portion of a memory rack illustrating another exemplary hierarchical decoding configuration for providing suitable conditions for selected and unselected array blocks on the (four) pole select bus. 123178.doc -72- 200826114 Figure 22 is a block diagram of one portion of a memory rack illustrating another exemplary hierarchical decoding configuration for providing appropriate conditions for selection and selection on the source select busses. Figure 23 is a block diagram of a data circuit including a read sense amplifier, a set driver, and a reset driver for various embodiments described herein.

Figure 24 is a block diagram of an exemplary reset circuit including a reset path through a selected memory cell and one of the word line and bit line select paths. The same reference numerals are used in the different drawings to indicate similar or identical items. [Main element symbol description] 100 Exemplary passive element memory array 101 Passive element memory unit 102 Word line 103 Passive element memory unit 104 Word line 105 Passive element memory Body unit 106 bit line 107 passive element memory unit 108 bit line 152 column decoder 153 power node 154 power node 155 output / node 123178.doc -73- 200826114 156 inverter 157 multiplexer 158 decode output 159 output 160 Inverter 161 multiplexer 162 Decode output 164 Node 167 Bus 168 Bus bar 171 PMOS transistor 172 NMOS transistor 173 PMOS transistor 174 NMOS transistor 175 PMOS transistor 176 NMOS transistor 177 PMOS transistor 178 NMOS Transistor 181 Unselected Word Line 183 Unselected Word Line 200 Exemplary Bias Condition 202 Row Decoder 203 Power Node 204 Power Node 123178.doc -74- 200826114 205 Output 206 Inverter 207 Multiplexer 208 Decode Output 209 Output 210 inverter 211 multiplexer 212 decode output 214 Node 217 Bus 218 Bus 221 PMOS transistor 222 PMOS transistor 223 PMOS transistor 224 NMOS transistor 225 PMOS transistor 226 NMOS transistor 227 PMOS transistor 228 NMOS transistor 231 bit line 233 unselected locator Line 300 Exemplary Memory Array 302 Dual Column Decoder 304 Dual Column Decoder - 75 · 123178.doc 200826114 306 Memory Array Block 308 Memory Array Block 310 Vertical Connection 312 Bit Line Circuit Block 314 Bit Line Circuit Area Block 315 bit line circuit block 316 bit line circuit block 318 memory "strip π 320 memory" strip π 322 bit line 324 bit line 332 memory block 333 bit line 334 memory block 335 Bit Line 336 Word Line Segment 337 Word Line Segment 338 Word Line Segment 339 Vertical Connection 340 Vertical Connection 342 Word Line Segment 344 Vertical Connection 352 Decode Output 353 Decode Output 123178.doc -76- 200826114 358 359 360 361 362 363 370 371 372 373 374 375 376 377 378 379 380 381 382 400 402 404 406 407 Vertical connection vertical connection word line segment word line segment word line Segment word line segment memory array first second second top data bus memory array block memory array block selected word line column bottom data bus bottom line decoder circuit top row decoding circuit top bit line selection area Block bottom bit line selection block memory frame first data bus second data bus array odd array block even array block 123178.doc -77- 200826114 408 410 412 420 422 424 426 427 430 432 440 442 444 446 447 448 449 450 454 460 462 464 466 468 Bit Line Selection Block Bold Arrow Bold Arrow Memory Rack Data Bus Second Data Bus First Array Block Second Array Block Bold Arrow Bold Arrow memory rack first data bus second data bus first array block array block second bit line selection block first bit line selection block bold arrow bold arrow memory rack array The upper data bus of the upper block of the block array block is the data bus 123178.doc -78- 200826114

500 bus arrangement 502 memory array block 504 memory array block 506 memory array block 508 coupling circuit 532 coupling circuit 533 coupling circuit 535 coupling circuit 536 bus bar 550 bus bar configuration 552 coupling circuit 554 coupling circuit 601 I / O logic 602 bus 603 bus 604 write latch block 605 read latch 606 bus 607 bus 608 control logic 609 bus 610 bus 611 bus 612 control line 123178.doc -79- 200826114 613 614 615 616 617 632 633 634 , 635 636 637 638 639 Read sense amplifier set driver reset driver SELB bus SELN bus signal bit line precharge (BLP) current limit circuit reset limit circuit SELN bus line position The line selection path control signal selects the memory unit word line selection path 123178.doc -80-

Claims (1)

200826114 X. Patent application scope: L An integrated circuit, which comprises a double-resonant array, which has a plurality of array blocks, each array block includes a sub-line and a bit line, and the ---the global convergence a row, which generally spans the plurality of array blocks, for coupling a selected one of the selected regions to an individual data circuit; and a first bus segment of each array block And for transmitting the first unselected = element line partial condition suitable for the first mode of operation to the unselected location line of the selected block during a first-# mode: and adapting one The first operation 2. A bit of the unselected positioning element line 5 to the unselected positioning element line of the unselected array block. The integrated circuit of claim 1, wherein the fourth operation mode includes a set operation mode; and the first unselected positioning element line bias condition of the first operation mode includes an unselected positioning element line voltage And the second unselected w bias condition of the first mode of operation includes a floating condition. 3. The integrated circuit of claim 2, wherein: in the case of the younger one, the individual first bus segment of the selected array block is combined to be suitable for the second mode of operation in the individual = The individual data on the bus segment line is transmitted to the selected location line of the selected block. 4. The integrated circuit of claim 3, wherein: 123178.doc 200826114 The first global bus includes a coupling/writing bus. Read to one of the fetch/write circuits. 5. The integrated circuit of claim 4, the first step, includes: a coupling to a second data circuit, wherein each block includes a c-flow row; - The bus segment is lightly coupled to the first and sometimes floats. The king domain bus, sometimes making it τ 6 · If the product of the request item 5 is in the first mode of operation, the line is in the second type of the busbar condition suitable for the "..." two king domain busbars a bias voltage under unselected positioning element line bias conditions; and a bus bar of the first global bus bar in the winding mode: biasing under unselected positioning element line bias conditions suitable for the second mode of operation 7. The integrated circuit of claim 3, further comprising: a global bias line coupled to a bias circuit; each of the eight blocks includes a separate coupling circuit for sometimes the individual Each bus bar of the bus-strip segment is coupled to the global bias line during which the global bias line delivers an unselected locating line bias voltage suitable for the first mode of operation. The integrated circuit of 7 further comprising: a plurality of light combining circuits for coupling the individual first bus bar segments for the respective array blocks to form across the plurality of array regions One of the blocks of a single logic bus, the coupling one 123178.doc 200826114 The first bus segment is #狮口至边弟二数据电路. 9. The integrated circuit of claim 8, wherein: the individual first confluence for each Chen Wan π W ghost The segment segments are coupled together during the mode of the brother-in-law. 10. The integrated circuit of claim 8, wherein in the second mode of operation, each bus line of the global bus is tied to a bias voltage suitable for the unselected positioning element line voltage condition of the hammer mode; and: in the first and second modes of operation, the global bias line transmission: suitable for the first mode of operation The locating element bias voltage is not selected. 11. The integrated circuit of claim 7, wherein: each block includes an individual facet circuit for sometimes coupling the individual first bus bar segment to the second The global bus is as follows: I2. The integrated circuit of claim 11, wherein: in the second mode of operation, each of the 汇_μ first king-domain busbars is adapted to the second option Unbiased under the condition of the u line voltage; and in the And the second operation mode _, the eight-one, the global bias line transmission - the unselected locator bias voltage suitable for the first operation mode. 13. The integrated circuit of claim 7, wherein: A global bus includes a global selection bus that is coupled to one of the individual data circuits; and the memory array further includes each of the array blocks - an individual second bus segment for use in the first operation During the mode, it will be - suitable for: 123178.doc 200826114 = The data of the operating mode depends on the bit line offset (four) piece of the block it is written - μ, Wang Xuan - suitable for ρ ! used in the second mode of operation During this period, the unselected positioning element (4) condition to the un-mode is passed to the unselected positioning element of the un-arranged block. 14. The integrated circuit of claim 13, wherein each block comprises a separate coupling circuit for sometimes splicing individual second bus segments to the global selection bus and at a particular time Coupling 5 to the global bias line and floating it at other times; in the first mode of operation, the global bias line transmits an unselected locator bias voltage suitable for the first mode of operation; In the second mode of operation, the global bias line delivers an unselected locator bias voltage suitable for the second mode of operation. 15. The integrated circuit of claim 1, wherein: the memory array comprises a three-dimensional memory array having bit lines on a two bit line layer; and a two bit line in a different array block The bit line on the layer is simultaneously coupled to the individual bus segment. 16. The integrated circuit of claim 15, wherein each memory cell comprises a reversible resistor element. 17. The integrated circuit of claim 16, wherein: the reversible resistor element comprises a transition metal oxide. 18. The integrated circuit of claim 16, wherein: each a memory element comprises a reversible resistance of a string of diodes. 123 123.doc 200826114 19 · A product coded as claim 1 The computer of the body circuit can read the media. 20. A package module comprising the integrated circuit of claim 1. An integrated circuit comprising: a memory array having a plurality of array blocks, each array block comprising a sub-line and a bit line; a coupling member for coupling a selected positioning element line of the selected block to the individual data circuit by a first-global bus bar that generally spans the plurality of array blocks in a first mode of operation; a means for coupling unselected positioning element lines of the two selected and unselected array blocks to a different first bus line segment associated with each of the individual array blocks; a first pass of the individual operational modes associated with the block a means for transmitting a first unselected positioning element line bias condition on the first busbar segment with the selected array area; and a transfer means for associating with the unselected U-block Passing on the second two - a second unselected positioning element line bias condition suitable for the first mode of operation. 22. The integrated circuit of claim 21, wherein: the first mode of operation comprises - setting an operating mode; the component adapted to the first mode of operation comprises - unselected bit line voltage; and un... Selecting the positioning element line bias strip is suitable for the second piece of the first mode of operation to include a floating condition. 23. The integrated circuit of claim 21, further comprising a second operating mode 123178.doc 200826114: a coupling member for coupling a selected array block or a plurality of selected positioning elements to An individual first bus segment associated with the selected array block; ^ a transfer component 'for transmitting a suitable second mode of operation on the individual first bus segment associated with the selected array block The individual data is dependent on the bias condition; and a coupling member is operative to couple the unselected positioning element of the selected array block to the first global bus. 24. 25. 26. 27. The integrated circuit of claim 23, further comprising: in the second mode of operation, coupling the individual first busbar segment associated with the selected array block to A component of a data circuit. The integrated circuit of claim 23, wherein: the second mode of operation comprises a reset mode of operation; and the individual data coupled to the selected location line of the selected array block is adapted to the second mode of operation The pressing condition includes a first value for resetting the selected positioning element line and a second value for causing the selected positioning element line to not change. The integrated circuit of claim 23, wherein: the first global bus includes a read/write bus coupled to a read/write circuit. W. The integrated circuit of claim 26, further comprising: a coupling member for coupling an individual first Ε μ row of slaves for an array block to a second global bus, the second The global convergence 123178.doc 200826114 is coupled to a second drain # &amp; a Becco circuit' and is sometimes used to float the individual first bus segment. 28. The integrated circuit of claim 23, further comprising: a coupling member for sometimes consuming each bus bar segment of the individual first bus bar segment to a global bias line; and a transfer member 'It is used to sometimes pass an unselected positioning element line bias voltage suitable for the first mode of operation on the global bias line. 29. The integrated circuit of claim 28, further comprising: a lie member for sometimes equipping the individual first busbar segments for the respective array blocks into an array region... To form an early logic bus that spans the plurality of red patches; and a coupling member for coupling to the first bus segment of the $m' coupling 5 to the two-party data bus. 30. The integrated circuit of claim 28, wherein the further step comprises: to two configurations for sometimes merging the individual first bus bar segments with a global bus. 31. The integrated circuit of claim 28, wherein: the brother domain bus includes; the person 5 ·&gt;&gt;·4* the global selection of the 3 coupling &amp; to the individual data circuits - A k Selecting the bus bar; and the other circuit of the integrated circuit into the block block is used for the fine between the parent array, which will be suitable for: the first - the wide-range segment in the first operating mode至 ====================================================================================================== The 200826114 bit line bias condition is passed to the unselected location line of the unselected array block. 32. A method for cooperating with a memory array, the memory array having a plurality of array blocks, each array block comprising a word line and a bit line, and in a first mode of operation, the method comprises: Selecting a selected location element line of the selected block to the individual data circuit by traversing the first area of the plurality of array blocks, and selecting unselected positioning elements for both the selected and unselected array blocks a line coupled to a different first bus segment associated with each of the array blocks; transmitting a suitable one for the first mode of operation on the respective first bus segment associated with the selected array block _._^ 7 ^ Α You F unveil the first unselected locating element line bias condition; and pass on the individual first bus snippet segments associated with the unselected array block - the second unsuitable for the first mode of operation Select the positioning element line bias condition. 3: The method of claim 3, wherein: the first person suitable for the first mode of operation, the first unselected bit line bias condition comprises a net moving condition. 3. The method of claim 3, wherein: the first mode of operation comprises a set mode of operation; and the first component adapted to the first mode of operation comprises a de-emphasis The bead 1 is not selected to locate the line voltage at 匕3. 35. The method of claim 32, wherein: 匕3 in the second mode of operation 123178.doc 200826114, one of the selected array blocks is ^^ / 夕 疋 疋 线 线 与 与Array block associated with one, (1) first bus segment segment; in the selected first array region, the individual first bus segment segment associated with the block is passed a suitable for the second operation, 4, . ^ The individual data of the 相 type is dependent on the bias strip 1 and the de-sink of the selected array block. The 兀 兀 line is coupled to the first global domain 36. The method of claim 35, wherein the step 301 comprises: in the second mode of operation, an individual, associated with the 5th 疋 array block A bus segment is coupled to a data circuit. 37. The method of claim 36, further comprising: in the second mode of operation of the second mode, the individual first bus slice segments associated with the /, 5, and 疋 array blocks are crossed to the plurality of arrays The bus of the block. 3. The method of claim 35, wherein: the second mode of operation comprises a reset mode of operation; wherein the plurality of selected m lines of the selected array block are suitable for the second plug-in type The data dependent bias condition includes a first value that resets a selected line and a second value that does not change the selected positioning line. 39. The method of claim 35, wherein: the first global buffer includes a read/write bus that is coupled to the read/write circuit. The method of claim 39, further comprising: 123178.doc 200826114=The individual-busbar segments of the array block are lighted to the second: two: busbars' the second global busbar is itself coupled to a path 'and sometimes used to float the individual first bus segment 0. 41. The method of claim 4, further comprising: in the first mode of operation M ^ y. Each of the bus bars is biased under the first operating condition; the mode is biased by the unselected positioning element line of the type 1! In the second mode of operation, each of the first global busbars is merged with (4): the bias of the operating region is biased. 42. The method of claim 35, further comprising: sometimes combining the respective busbar lines of the individual first busbar segments to a global bias line; and transmitting one of the global bias lines at the time An unselected positioning element line bias voltage suitable for the first mode of operation. 43. The method of claim 42, further comprising: coupling the individual first bust segments for respective array blocks to form a single logic across the plurality of array blocks a bus bar; and the first bus segment that is lightly coupled to the second data bus. 44. The method of claim 43, further comprising: coupling the respective first bus segments for the respective array blocks during the second mode of operation. 45. The method of claim 43, wherein the second step comprises: in the second mode of operation, the cable is biased at each of the busbars suitable for the second operational global bus; and, $ is unselected The 70-line bias strip is transferred over the global bias after the first and second operating modes, ^^ 、, and is suitable for the first operating deep pressure. The unselected locating element bias voltage 46. The method of claim 42, wherein the step _ comprises: arranging the individual first bus at times. The method of claim 46, further comprising: in the second mode of operation, each of the bus bars of the global bus bar is adapted to the second Operating the 偏压 bias from the unselected locating element line bias condition; and in the first and second modes of operation - flying one, transmitting a suitable one on the global bias line Bamboo carrier, 丄 乍 1乍 mode unselected positioning element bias voltage. 48. The method of claim 42, wherein: the first global bus bar comprises a monk $ — μ , 3 coupled to one of the individual data circuits, the global selection bus, and the method further comprising An additional second bus segment 'in the first-operation mode' can pass the individual data-dependent bit line bias conditions suitable for the first mode of operation to the selected block 123178. Doc -11 - 200826114 &amp; bit line, and used to pass an unselected locating element line bias condition in the beta mode of operation to the unselected array block during the second mode of operation Select the positioning element line. The method of claim 48, wherein: the individual data dependent bias conditions passed to the selected positioning element of the selected array block during the first mode of operation include - enabling - selecting a location line in The first value of the upper operation and the - make-select positioning element line do not change the second value. 5. The method of claim 48, further comprising: coupling the gamma-supplied, and singular-single-bus two-segment segments for a zone wall to the global k-selection machine row, At other times, it is consumed by the global bias line 'and floats in the material of the second material system. In this first operation mode, a suitable one is transmitted on the global bias line. Unselected locating element bias voltage; and in the second mode of operation, transmitting on the global omni-directional I line - suitable for the second mode of operation $ go, west h, 51 puzzling unselected locating element Bias voltage. A method for fabricating a G-body product, the method comprising: forming a memory array having a plurality of array blocks, each array block comprising word lines and bit lines , forming a first global bus, one piece, for sometimes - selected area /, multiple array area material circuit; earth mouth blade forming each array block _ post ^ ^ ^ (7) Diocese a row segment for adapting a pick f during the first mode of operation The first 123178.doc -12- 200826114 of the operation mode is passed to the unselected positioning element of the "selection block". The second unselected positioning element line suitable for the first operation mode is 5m. The method of claim 51, wherein: the first operation mode includes a set operation mode; (in the first operation mode (4) - the unselected position line is not selected. Partial job 3 unselected location line voltage; and ^ (4) the first mode of operation - the unselected location line condition includes a floating condition. 53. The method of claim 52, wherein: - in the second mode of operation, the individual first = row segments of a selected array block are wired to pass individual bias conditions on the individual bus-bus segment bus lines suitable for the (four) two mode of operation to the selected The block selection location line 54. The method of claim 53, further comprising: forming the first-global bus as a dedicated read/write bus that is coupled to a read/write circuit. 55. The method of claim 54, further comprising Forming a second global busbar that is coupled to a second data circuit; forming a separate circuit for each block for coupling the individual first bus bar segment to the second global bus The method of claim 5, wherein the method further comprises: forming a global bias line coupled to a bias circuit; 123178.doc -13 - 200826114 for each block, Forming an additional coupling circuit for sometimes coupling respective bus bars of the respective first bus bar segments to the global bias line ' during which the global bias line is transmitted for a first mode of operation The positioning element line bias voltage is not selected. 57. The method of claim 56, further comprising: forming a plurality of coupling circuits for coupling together the individual first busbar segments for respective array blocks to form across the complex number One of the array blocks is a single logic bus, and the coupled bus segments are coupled to the second data circuit. The method of claim 56, further comprising: forming, for each of the blocks, a separate coupling circuit for coupling the individual first busbar segments to the second global busbar. 5. The method of claim 5, wherein the first global bus includes a global selection bus coupled to one of the individual data circuits; Extendingly forming a second bus bar segment of each array block for transmitting a conditional element (4) condition suitable for the first interpolation mode to the m during the first mode of operation The block selection = element line, and during the second mode of operation, the unselected positioning element line conditions suitable for the = operating mode are passed to the unselected positioning elements of the unselected array block. 60. The method of claim 51, further comprising: a meta-three-dimensional memory array having a bit on a two-bit line layer 123178.doc -14 - 200826114 61. The method of claim 60, Where: Resistor component. Forming a memory unit that includes a reversible 123178.doc 15-