JP2007509499A - 低k誘電体を半導体製造プロセスにおいて形成する方法 - Google Patents
低k誘電体を半導体製造プロセスにおいて形成する方法 Download PDFInfo
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- JP2007509499A JP2007509499A JP2006536603A JP2006536603A JP2007509499A JP 2007509499 A JP2007509499 A JP 2007509499A JP 2006536603 A JP2006536603 A JP 2006536603A JP 2006536603 A JP2006536603 A JP 2006536603A JP 2007509499 A JP2007509499 A JP 2007509499A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02054—Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
Abstract
Description
当業者であれば、これらの図における構成要素が説明を簡単かつ明瞭にするために示され、そして必ずしも寸法通りには描かれていないことが分かるであろう。例えば、これらの図における幾つかの構成要素の寸法を他の構成要素に対して誇張して描いて本発明の実施形態を理解し易くしている。
とができる。導電層30は銅であることが好ましいが、別の導電材料とすることができる。キャップ層32は、テトラエチルオルトシリケート(TEOS)を使用して形成される酸化物であることが好ましいが、他の誘電体材料とすることができる。誘電体24は複合層であり、上層はSiCOH、またはフッ素及びTEOS(FTEOS)を使用して形成される酸化物のいずれかであることが好ましい。CMPプロセスを誘電体層24に適用して、CMP処理後の層24の表面上の材料を変えることができるようにする。CMPプロセスを実行する前の層24上の材料の好適な組み合わせは、シリコンリッチな酸化物、シリコンリッチな酸窒化物、TEOS酸化物であり、この組み合わせにより、層24の上部表面は、素子10が形成されるウェハ全体に渡って同じとはならない。半導体素子10は、低kバリア層26及び低K誘電体28から成る複合層、及び低kバリア層34及び低K誘電体層36から成る複合層を形成する方法を除いた従来の手段によって形成することができる従来構造である。
によって歩留まりが著しく改善された。
Claims (29)
- 半導体基板の上に層を形成するための方法であって、
半導体基板を設ける工程と、
疎水性表面を有する第1誘電体層を前記基板の上に形成する工程と、
前記疎水性表面を親水性表面に改質する工程と、
前記親水性表面をスクラブ処理する工程と、
第2誘電体層を前記第1誘電体層の上に形成する工程とを備える方法。 - 前記第1誘電体層はシリコン、炭素、及び窒素を含有する、請求項1記載の方法。
- 前記疎水性表面から前記親水性表面への改質は酸素プラズマにより行なう、請求項1記載の方法。
- 前記第2誘電体層はシリコン、炭素、酸素、及び水素を含有する、請求項1記載の方法。
- 前記疎水性表面から前記親水性表面への改質は酸素プラズマにより行なう、請求項2記載の方法。
- 前記第2誘電体層はシリコン、炭素、酸素、及び水素を含有する、請求項5記載の方法。
- 前記親水性表面を、水を用いた洗浄液でスクラブ処理する、請求項6記載の方法。
- 水を用いた前記洗浄液は水酸化アンモニウムを含有する、請求項7記載の方法。
- 前記第1誘電体層はシリコン、窒素、及び炭素を含有する、請求項5記載の方法。
- 前記親水性表面を、水を用いた洗浄液でスクラブ処理する、請求項9記載の方法。
- 水を用いた前記洗浄液は水酸化アンモニウムを含有する、請求項10記載の方法。
- 前記第1誘電体層を形成する工程及び前記疎水性表面を親水性表面に改質する工程は、in−situで行われる、請求項5記載の方法。
- 前記第1誘電体層を形成する工程、及び前記疎水性表面を親水性表面に改質する工程は、in−situで行われる、請求項1記載の方法。
- 第1誘電体をプラズマ放電により堆積させ、及びプラズマにより改質する、請求項1記載の方法。
- 半導体基板の上に層を形成するための方法であって、
半導体基板を設ける工程と、
第1誘電体層を前記基板の上に形成する工程と、
前記第1誘電体層を酸素プラズマで処理する工程と、
前記第1誘電体層を水溶液で洗浄する工程と、
第2誘電体層を前記洗浄済み第1誘電体層の上に形成する工程とを備える、方法。 - 前記第1誘電体層を前記酸素プラズマで処理することによって、前記第1誘電体層の疎
水性表面を親水性表面に改質する、請求項15記載の方法。 - 前記第1誘電体層を洗浄する工程では、前記第1誘電体層を前記水溶液でスクラブ処理する、請求項16記載の方法。
- 前記水溶液は水酸化アンモニウムを含有する、請求項17記載の方法。
- 前記第1誘電体層はシリコン、炭素、及び窒素を含有する、請求項18記載の方法。
- 前記第1誘電体層はシリコン、炭素、及び窒素を含有する、請求項15記載の方法。
- 前記第1誘電体層を形成する工程は第1チャンバー内で行なわれる、請求項20記載の方法。
- 前記第1誘電体層を前記酸素プラズマで処理する工程は前記第1チャンバー内で行なわれる、請求項21記載の方法。
- 半導体構造の製造方法であって、
半導体基板を設ける工程と、
シリコン、炭素、及び窒素を含有する第1誘電体層を前記基板の上に形成する工程と、
前記第1誘電体層を酸素プラズマで処理する工程と、
前記第1誘電体層をスクラブ処理する工程と、
第2誘電体層を前記第1誘電体層の上に形成する工程と、を備える製造方法。 - 前記第1誘電体層は疎水性表面を有する、請求項23記載の方法。
- 前記第1誘電体層を処理する前記工程によって、前記疎水性表面のほぼ全てが親水性表面に改質される、請求項24記載の方法。
- スクラブ処理する工程では、水を用いた洗浄水溶液でスクラブ洗浄する、請求項23記載の方法。
- 水を用いた前記洗浄水溶液は水酸化アンモニウムを含有する、請求項26記載の方法。
- スクラブ処理する工程では、機械的洗浄及び化学的洗浄を行なう、請求項27記載の方法。
- 前記第1誘電体層を形成する工程は、
シリコン、炭素、及び窒素から成る第1誘電体層を形成する工程を備え、
前記第1誘電体層を形成する工程、及び前記第1誘電体層を処理する工程は、in−situで行われる、請求項23記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/690,060 US6902440B2 (en) | 2003-10-21 | 2003-10-21 | Method of forming a low K dielectric in a semiconductor manufacturing process |
PCT/US2004/024904 WO2005045914A1 (en) | 2003-10-21 | 2004-07-30 | Method of forming a low k dielectric in a semiconductor manufacturing process |
Publications (3)
Publication Number | Publication Date |
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JP2007509499A true JP2007509499A (ja) | 2007-04-12 |
JP2007509499A5 JP2007509499A5 (ja) | 2007-09-13 |
JP4659751B2 JP4659751B2 (ja) | 2011-03-30 |
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JP2006536603A Expired - Fee Related JP4659751B2 (ja) | 2003-10-21 | 2004-07-30 | 低k誘電体を半導体製造プロセスにおいて形成する方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6902440B2 (ja) |
JP (1) | JP4659751B2 (ja) |
KR (1) | KR101054676B1 (ja) |
CN (1) | CN100501937C (ja) |
TW (1) | TW200515532A (ja) |
WO (1) | WO2005045914A1 (ja) |
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US8465991B2 (en) | 2006-10-30 | 2013-06-18 | Novellus Systems, Inc. | Carbon containing low-k dielectric constant recovery using UV treatment |
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CN103854962B (zh) * | 2012-11-28 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | 晶圆刻蚀后的清洗方法 |
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US20050085082A1 (en) | 2005-04-21 |
JP4659751B2 (ja) | 2011-03-30 |
CN1864251A (zh) | 2006-11-15 |
US6902440B2 (en) | 2005-06-07 |
KR20060101758A (ko) | 2006-09-26 |
KR101054676B1 (ko) | 2011-08-08 |
TW200515532A (en) | 2005-05-01 |
CN100501937C (zh) | 2009-06-17 |
WO2005045914A1 (en) | 2005-05-19 |
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