TWI825142B - 用以改善選擇性沉積製程中之選擇性的預處理方法 - Google Patents

用以改善選擇性沉積製程中之選擇性的預處理方法 Download PDF

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TWI825142B
TWI825142B TW108127668A TW108127668A TWI825142B TW I825142 B TWI825142 B TW I825142B TW 108127668 A TW108127668 A TW 108127668A TW 108127668 A TW108127668 A TW 108127668A TW I825142 B TWI825142 B TW I825142B
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copper
metal
improving
selectivity
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丹尼斯 豪斯曼恩
伊爾哈姆 莫希尼
鵬翼 張
保羅 Ｃ 勒邁爾
卡希什 沙瑪
亞歷山大 Ｒ 福克斯
納葛 珊卡
卡蒲 瑟利西 瑞迪
大衛 查爾斯 史密斯
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美商蘭姆研究公司
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Abstract

一種用以改善選擇性沉積製程中之金屬之選擇比的方法。金屬用之預處理製程修飾金屬表面且具有先自金屬移除有機污染而還原金屬的步驟以及之後氧化金屬而使金屬氧化物之單層成長於表面上的步驟。此金屬修飾使抑制分子能吸附至金屬氧化物之單層上而改善選擇比。

Description

用以改善選擇性沉積製程中之選擇性的預處理方法
本發明係關於半導體製造方法。更具體而言，本發明係關於用以改善選擇性沉積製程中之選擇性的方法。
製造半導體裝置通常需要內連線結構，內連線結構包含在半導體晶片中用以連接裝置的金屬導線。導線通常包含形成在延伸橫跨晶片之介電層中的金屬線以及連接晶片之不同位準之導線的插塞。在許多應用中，在基板上進行選擇性沉積以形成插塞。金屬線及插塞通常由鋁或銅所形成且藉由介電材料絕緣。
在半導體製造中，期望插塞能與其所連接的兩層位準完全對準。當往下鑽鑿以形成通往下方金屬線的插塞時，若有任何的失準，插塞可能錯過期望的金屬線而接觸另一金屬線因而造成短路。
在形成完全對準之插塞的製程中，通常在沉積金屬線(即銅)之後，選擇性地將鋁之氧化物 (Al2 O3 )沉積在介電表面上作為蝕刻停止層。已知Al2 O3 只會沉積在介電表面(如矽氧化物)上而不會沉積在已被暴露至抑制分子之原生銅表面上。然而利用此選擇性沉積製程形成插塞需要原生銅表面，如利用物理汽相沉積(PVD)所沉積者，其需要高操作溫度且亦難以沉積在複雜的幾何結構上。修飾銅表面以改善選擇性的現有技術使用兩步驟製程：(1)將原生銅表面暴露至抑制劑；及(2)利用熱原子層沉積(ALD)沉積Al2 O3 。此製程僅適用於PVD所沉積的銅而不適用於電填充(EF)所沉積的銅或EF後進行化學機械研磨(CMP)的銅。
然而在形成完全對準之塞插的製程中，銅通常係利用EF製程所沉積然後受到化學機械研磨而形成插塞。此藉由EF/CMP製程所沉積的銅無法吸附抑制分子，是以後續用以沉積蝕刻停止層的ALD  Al2 O3 製程並非選擇性的。因此，期望改善在形成完全對準之插塞之製程中藉由EF/CMP所沉積之銅上之沉積製程的選擇性。
根據一實施例，提供一種用以改善金屬之選擇性的方法。在一半導體處理室中提供一基板。該基板具有形成於一介電層中之複數金屬線。該金屬係藉著自該金屬移除有機污染而自一金屬氧化物還原為金屬。在還原該金屬之後，接著氧化該金屬並使金屬氧化物的一單層成長於該金屬的一表面上。
根據另一實施例，提供一種用以改善電填充製程所沉積之銅之選擇性的方法。在一半導體處理室中提供一基板。該基板具有形成於一介電層中之複數銅線。該銅係藉著自該銅移除有機污染而自一銅氧化物還原為銅。在還原該銅之後，接著氧化該銅並使銅氧化物的一單層成長於該銅的一表面上。在使該單層成長之後，沉積僅對該銅有選擇性的抑制分子，該抑制分子能吸附至銅氧化物之該單層上。
根據更另一實施例，提供一種用以改善在蝕刻停止層上選擇性沉積的方法。在一半導體處理室中提供一基板。該基板在其表面上具有一介電層。藉由一電填充製程將銅沉積至該基板之該表面上。接著化學機械研磨該銅。接著使氨與氮的一電漿混合物流入該處理室中，以藉著自該銅移除有機污染而使該銅自一銅氧化物還原為銅。在還原該銅之後，接著使一氧電漿或氧流至該處理室中，氧化該銅並使銅氧化物的一單層成長於該銅的一表面上。在使該單層成長之後，沉積僅對該銅有選擇性的硫醇分子，該硫醇分子能吸附至銅氧化物之該單層上。選擇性地將一蝕刻停止層沉積至該介電層上方。
現將參考附圖所例示之數個較佳實施例詳細說明本發明。在下列說明中例舉多個特定細節以提供對本發明的全面瞭解。但應明白，對於熟知此項技藝者所而言，可在缺乏部分或全部此些特定細節的情況下實施本發明。在其他情況中，不詳細說明已知的製程步驟及/或結構以免不必要地模糊本發明。
文中的實施例係大致上關於選擇性沉積製程。尤其，文中的實施例關於用以改善選擇性沉積製程中之選擇性的預處理方法。可預處理金屬如銅、鈷、及鎢以修飾金屬表面而接受抑制分子。藉著使用兩步驟預處理，可改飾例如EF/CMP銅表面而使其接收抑制分子，並致使蝕刻停止層如Al2 O3 、矽之氧化物(SiO2 )、及其他低介電常數(low-k)薄膜的接續淨選擇性沉積。
參考圖1-3說明用以改善銅表面之選擇性之預處理製程的實施例。用以改善選擇性的預處理製程在用以形成完全對準之插塞的製程中尤其有用。根據文中所揭露的一實施例，預處理製程修飾金屬(並不一定要原生的金屬)的表面以改善選擇性。例如，利用如預處理製程可修飾藉由EF或EF/CMP所沉積的銅而改善選擇性。如下面將更詳細討論的，使用兩步驟預處理製程改善EF或EF/CMP所沉積之金屬(如銅、鈷、鎢)的選擇性，以允許抑制劑吸附而達成僅在介電材料上之接續選擇性沉積。
改善選擇性在用以形成完全對準之插塞的製程中尤其有用。插塞對準在半導體裝置中對於可靠度是很關鍵的，因為一般期望最大的接觸而如上所述失準的插塞可能會導致短路。一般而言，在用以形成完全對準之插塞的製程中使用用以沉積銅線的電填充製程，接著對銅線進行CMP。為了使銅線凹陷，選擇性地將Al2 O3 介電層沉積在介電層上方(但不沉積於銅上方)作為蝕刻停止層。如上所述，藉由電填充所沉積且接著受到化學機械研磨的銅無法吸附抑制劑因此接續之用以沉積Al2 O3 的ALD 製程非為選擇性的。
根據文中所揭露的實施例，藉由下列方式修飾金屬表面以改善選擇性：(1)移除有機污染以還原金屬、及(2)在還原後進行受到控制之氧化。可使用電漿如氨(NH3 )與氮(N2 )之電漿混合物、氫(H2 )電漿、氨(NH3 )電漿、及非熱能之二硼烷(B2 H6 )電漿以自金屬移除有機污染。在其他實施例中，可使用檸檬酸或乙酸移除有機污染。藉著將金屬暴露至氧(O2 )電漿、氧(O2 )、臭氧(O3 )、或過氧化氫(H2 O2 )可進行受到控制之氧化。金屬表面的氧化會造成金屬氧化物之單層的熱重新成長。單層係較佳地大於1 Å厚。應瞭解，在理想上單層應儘可能地薄，因為金屬氧化物並不如純金屬為導電的故經降低的導電率可能會使半導體裝置退化。金屬表面的還原及接續氧化會導致表面能吸附抑制分子。
在氧化後，接著將金屬暴露至能吸附在金屬表面上的抑制分子。適合的抑制劑包含硫醇(如丁烷硫醇及十二烷硫醇)及膦酸(如十八烷基膦酸)。應瞭解，硫醇較佳地吸附在經修飾過的銅表面上而膦酸較佳地吸附在經修飾過的鈷表面上。然而，若使用膦酸作為抑制劑必須使用濕式化學品，因為膦酸並非揮發性的故不適合用於蒸氣化學品。另一方面，硫醇為揮發性的故在使用硫醇作為抑制劑時不一定要使用濕式化學品。
根據一特定之實施例，藉由下列方式修飾銅表面以達成選擇性：(1)移除有機污染以將CuOx還原為Cu、及(2)在還原後進行受到控制之氧化。可使NH3 與N2 共流以形成電漿混合物而移除有機污染並還原銅。接著藉著將銅表面暴露至O2 電漿或O2 以熱重新成長CuOx 之單層而將銅表面氧化。單層較佳地大於1 Å厚。雖然銅表面的典型製備係由利用NH3/ N2 電漿的單一還原步驟所完成，而在此還原過程後進行氧化步驟看似違反直覺(因為其似乎會使初始的還原步驟失去其意義)，但此氧化步驟對於達到選擇性是很關鍵的，因為此氧化步驟能使銅吸附抑制分子如硫醇或膦酸。
參考圖1說明一種改善金屬之選擇性之方法的實施例。方法100始於在步驟110中於半導體處理室中提供基板，基板具有形成於介電層(如矽之氧化物(SiO2 ))中之複數金屬線。金屬係由電填充製程所沉積然後受到了化學機械研磨。在步驟120中，藉著自金屬移除有機污染而將金屬自金屬氧化物還原成金屬。在步驟130中，將金屬氧化，以造成熱重新成長之金屬氧化物之單層。在重新成長金屬氧化物之單層之後，在步驟140中沉積僅對金屬有選擇性的抑制分子。經熱重新成長之金屬氧化物的單層使抑制分子能吸附，因此所得之金屬氧化物層相較於預處理步驟120-140之前的金屬表面具有經改善的選擇性。
參考圖2說明用以改善電填充處理所沉積之銅之選擇性的方法的一實施例。方法200始於在步驟210中於半導體處理室中提供基板，基板具有形成於介電層中之複數銅線。 銅係藉由電填充製程所沉積。在某些實施例中，在電填充製程之後銅受到了化學機械研磨。在步驟220中，使NH3 /N2 電漿流至處理室中以自銅移除有機污染並自CuOx還原為Cu。在步驟230中，使O2 電漿或O2 流至處理室中以將銅氧化。若氧化使用O2 電漿，則使O2 電漿流至處理室中約1-5秒。若氧化使用O2 ，則O2 流至處理室的持續時間範圍可自數分鐘至數小時。應瞭解，可使用較高溫度來增加氧化速率。氧化會導致熱重新成長之CuOx的單層。在重新成長CuOx之單層後，在步驟240中沉積僅對銅有選擇性的抑制分子。根據一實施例，沉積硫醇分子作為抑制劑。經熱重新成長之CuOx的單層能使抑制分子吸附，因此所得之銅層相較於預處理步驟220-240之前之銅表面具有經改善的選擇性。
根據其他實施例，能移除有機污染而還原金屬之某些其他適合的預處理選擇包含氫電漿、氨電漿、非熱能之二硼烷電漿、檸檬酸、及乙酸。除了氧電漿與氧(O2 )之外，能氧化經還原之金屬之其他適合的預處理選擇包含在室溫下將基板暴露至20%的氧與氮氣混合物約5分鐘(如週遭空氣)、臭氧(O3 )、及過氧化氫(H2 O2 )。應瞭解，預處理製程包含還原步驟及之後的氧化步驟，且可使用還原方法與氧化方法的不同組合。
文中所述之預處理製程可在一反應器中進行，此反應器例如是加州佛里蒙之科林研發公司所製造之Striker®及Vector®沉積反應器。
圖3為選擇性沉積蝕刻停止層之方法300之另一實施例的流程圖。方法300始於在步驟310中於半導體處理室中提供基板，該基板在其表面上具有介電層。在步驟320中，以電填充製程沉積銅。接著在步驟330中，化學機械研磨經電填充之銅。在步驟340中，使NH3 /N2 電漿流至處理室中以自銅移除有機污染並自CuOx還原為Cu。在步驟350中，使O2 電漿或O2 流至處理室中以將銅氧化。氧化會導致熱重新成長之CuOx的單層。在重新成長CuOx之單層後，在步驟360中沉積硫醇抑制分子並使硫醇抑制分子吸附至CuOx層上。經熱重新成長之CuOx的單層能使抑制分子吸附，因此所得之銅層相較於預處理步驟340-360之前之銅表面具有經改善的選擇性。在步驟370中，選擇性地將蝕刻停止層沉積至介電層上方。根據一實施例，蝕刻停止層為Al2 O3 層。在某些實施例中，Al2 O3 層係利用熱原子層沉積(ALD)製程所沉積。然而應瞭解，可使用其他沉積方法來沉積Al2 O3 層。一般而言，使用熱製程沉積蝕刻停止層，因為熱製程不會損傷抑制分子。應瞭解，電漿沉積處理可能會損傷抑制分子，因此會損害選擇性。
雖然僅詳細說明本發明之數個實施例，但應明白，可在不脫離本發明精神與範疇的情況下以許多其他形式實施本發明。有鑑於上述之全有內容，應明白，本發明之實施例為例示性而非限制性的，且本發明不限於文中所列舉之細節，在隨附申請專利範圍的範疇與等效物內可修改本發明。
100:方法 110:步驟 120:步驟 130:步驟 140:步驟 200:方法 210:步驟 220:步驟 230:步驟 240:步驟 300:方法 310:步驟 320:步驟 330:步驟 340:步驟 350:步驟 360:步驟 370:步驟
本發明係藉由實例說明而非限制，在圖示及附圖中類似的參考標號代表類似的元件，其中：
圖1為根據一實施例之用以改善金屬之選擇性之方法的流程圖。
圖2為根據一實施例之用以改善電填充製程所沉積之銅之選擇性之方法的流程圖。
圖3為根據一實施例之選擇性沉積蝕刻停止層之方法的流程圖。
100:方法
110:步驟
120:步驟
130:步驟
140:步驟

Claims (18)

  1. 一種用以改善金屬之選擇性的方法，其包含：在一半導體處理室中提供一基板，該基板具有形成於一介電層中之複數金屬線；藉著自該金屬移除有機污染而使該金屬自一金屬氧化物還原為金屬；在還原該金屬之後，氧化該金屬並使金屬氧化物的一單層成長於該金屬的一表面上；及在使該單層成長之後，沉積僅對該金屬有選擇性的抑制分子，並使該抑制分子吸附至金屬氧化物之該單層上。
  2. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該金屬係由一電填充製程所沉積。
  3. 如申請專利範圍第2項之用以改善金屬之選擇性的方法，其中在沉積該金屬之後化學機械研磨該金屬。
  4. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該金屬係選自由銅、鈷、及鎢所構成之族群。
  5. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該介電層包含矽之氧化物。
  6. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該還原步驟包含使氫電漿、氨與氮之電漿混合物、氨電漿、非熱能性之二硼烷電漿、檸檬酸、或乙酸流至該處理室中。
  7. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該氧化步驟包含使氧電漿、氧、臭氧、或過氧化氫流至該處理室中。
  8. 如申請專利範圍第1項之用以改善金屬之選擇性的方法，其中該抑制分子包含硫醇或膦酸。
  9. 一種用以改善電填充製程所沉積之銅之選擇性的方法，其包含：在一半導體處理室中提供一基板，該基板具有形成於一介電層中之複數銅線；藉著自該銅移除有機污染而將該銅自一銅氧化物還原為銅；在還原該銅之後，氧化該銅並使銅氧化物的一單層成長於該銅的一表面上；及在使該單層成長之後，沉積僅對該銅有選擇性的抑制分子，並使該抑制分子吸附至銅氧化物之該單層上。
  10. 如申請專利範圍第9項之用以改善電填充製程所沉積之銅之選擇性的方法，其中在還原該銅之前，化學機械研磨該銅。
  11. 如申請專利範圍第9項之用以改善電填充製程所沉積之銅之選擇性的方法，其中該介電層包含矽之氧化物。
  12. 如申請專利範圍第9項之用以改善電填充製程所沉積之銅之選擇性的方法，其中該還原步驟包含使氫電漿、氨與氮之電漿混合物、氨電漿、非熱能性之二硼烷電漿、檸檬酸、或乙酸流至該處理室中。
  13. 如申請專利範圍第9項之用以改善電填充製程所沉積之銅之選擇性的方法，其中該氧化步驟包含使氧電漿、氧、臭氧、或過氧化氫流至該處理室中。
  14. 如申請專利範圍第9項之用以改善電填充製程所沉積之銅之選擇性的方法，其中該抑制分子包含硫醇。
  15. 一種用以改善選擇性沉積蝕刻停止層的方法，其包含：在一半導體處理室中提供一基板，該基板在其表面上具有一介電層；藉由一電填充製程將銅沉積至該基板之該表面上；化學機械研磨由該電填充製程所沉積之該銅；在化學機械研磨該銅之後，使氨與氮的一電漿混合物流入該處理室中，以藉著自該銅移除有機污染而將該銅自一銅氧化物還原為銅；在還原該銅之後，使一氧電漿或氧流至該處理室中，以氧化該銅並使銅氧化物的一單層成長於該銅的一表面上；在使該單層成長之後，沉積僅對該銅有選擇性的硫醇分子，並使該硫醇分子吸附至銅氧化物之該單層上；及選擇性地將一蝕刻停止層沉積至該介電層上方。
  16. 如申請專利範圍第15項之用以改善選擇性沉積蝕刻停止層的方法，其中該介電層包含矽之氧化物。
  17. 如申請專利範圍第15項之用以改善選擇性沉積蝕刻停止層的方法，其中該蝕刻停止層包含鋁之氧化物。
  18. 如申請專利範圍第15項之用以改善選擇性沉積蝕刻停止層的方法，其中該蝕刻停止層係藉由一熱原子層沉積製程所沉積。
TW108127668A 2018-08-06 2019-08-05 用以改善選擇性沉積製程中之選擇性的預處理方法 TWI825142B (zh)

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