TW400599B - Method of confirming the reasons of the defects in the IC process - Google Patents

Abstract

This invention provides a method of confirming whether the reason of defects is caused by the electrostatic discharge (ESD) in the IC process. Such a method includes the steps of: firstly, providing a wafer formed thereon a semiconductor device, and the wafer comprising a metal layer; next, providing another wafer formed thereon the same semiconductor device with the first wafer, but replacing the metal layer with an insulation layer; applying the two wafers to any unit of the same process and allowing the first wafer to have the defects caused by the approximate electrostatic discharge (ESD); and finally, detecting whether the same defects appear in the second wafer. If yes, it is known that the defects are not caused by ESD; otherwise, the defects are caused by ESD.

Description

V. Description of the invention (1) The present invention relates to semiconductor process technology, and in particular, to a method for confirming the cause of defects in an IC process. In some special IC (AS 1C) manufacturing processes, it will be found that after the metal dielectric layer (IMD) is cleaned by a scrubber, the surface will have a via-crack. Defects occur. Scanning electron microscopy (SEM) revealed that these dielectric layers have caves or cracks. At the same time, the energy dispersive spectrum (EDS; Energy Dispeaicm Spectrum) showed that these defects contained A1 and F. , Ci and other elements, which means that the underlying metal layer is also exposed as a result, and may be invaded. Because via-crack always occurs on top of the metal pattern, and the SEM also shows that the underlying metal is bursting, electrostatic discharge (ESD; electrostatic discharge) is first considered the main cause; another is also available To explain that via-crack always occurs on the metal pattern, then the effect of inward metal dielectric interlayer stress is described. However, there is no simple and effective test method in the conventional technology that can let us know which one is the real cause of the aforementioned via-crack. In order to find out the root cause of via-crack, the inventor of this case conducted a series of experiments. 'During the experiment, it was found that in two different sets of scrubbers, the proportion of via-crack was higher (70 ~ 80%). The electrostatic field generated by the scrubber 'during the cleaning process is always higher than the normal value (about -3-5 KV / inch' normally about -1 ~ -2 KV / inch). Such results show that via-crack and ESD seem to be highly correlated. In another experiment, the inventor of this case studied the relationship between the parameters of the scrubber and via_crack.

C: \ Program Files \ Patent \ 0503-3793-E.ptd page 4 V. Description of the invention (2). The system, including spraying, finds rotation relevance, but adds. However, for example, a scrubber was produced. In order to enter, I will chuck) the replacement procedure. The new one has changed the pressure, rotation speed, and washing time of 5-0.8 KV / i water column. There is nothing to do with the washing time and vi a —crack ^ The pressure rise of 7 will make via-crack After increasing the number of experiments, even if I reduce the via_crack ratio and the pressure of the water column, we still cannot avoid via_crack. I understand the relationship between electrostatic discharge (ESD) and via-crack. Teflon rotating chuck (叩 4 ^ π rotating chuck made of electrical material and then performing the same washing. The conductor loss is used to reduce the electrostatic charge accumulated on the wafer. After the washing process, the electrostatic field in the center of the wafer is only 0nch ' Please refer to Table 1: Table 1 Teflon chuck electrostatic field (KV / inch) Via-crack number Via-crack wafer number total wafer number -4 to -5 2 2 4 _conductor chuck 0.5 to 0.8 6 5 8 # φ Table 1 shows that after replacing the Teflon chuck with the conductor chuck, although the points have been reduced. The onion has been greatly reduced, but the number of via_crack has not decreased. Although the above experiments to reduce the electrostatic field cannot make via-crack Decrease in number, I still cannot rule out Electrical discharge is via crack at cause may

V. Description of the invention (3) Due to the possibility of electrostatic discharge / +, if the charge flow to the Y-pillar of the Yoshioka ’s Y-pillar is in contact with the wafer, it may not be able to detect the ESD fast. The electrostatic detector has the fact that the wafer has been subjected to the second article and still shows a low electrostatic value. However, it can be known from the above that in the conventional drying method, it can be used to confirm that there are no simple and effective methods or other methods. There are other reasons.疋 Is it a result of electrostatic discharge?

In view of this, the method for confirming the cause of the defect in the main I of the present invention, a: "A total of one method is used to clarify the suspected ESD as a defect when the IC process is caused. The method of Θ can quickly Obtaining confirmation or description: 'The present invention provides a method for confirming whether electrostatic discharge (ESD) is the cause of a defect in the 1c process, including the following steps: (a) providing a first wafer on which There are semiconductor elements, at least-a metal layer, (b) a second wafer is provided on which the same semiconductor element as the first wafer is formed, but an insulating layer is used instead of the metal layer '(c) The two wafers are subjected to any identical processing unit and a defect caused by a suspected electrostatic discharge appears on the second wafer; and (d) comparing whether the second wafer has the same defects as the first wafer, if it is , It means that the above defect is not caused by electrostatic discharge; otherwise, it means that electrostatic discharge is the cause of the defect. = In the above method, the insulating layer of the second wafer and the metal layer of the first wafer preferably have the same Pattern, and the material of the insulating layer is, for example, silicon nitride formed by plasma enhanced chemical vapor deposition (PE-CVD).

C: \ ProgramFiles \ Patent \ 0503-3793-E.ptd page 6 5. Description of the invention (4) In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following is a better example. The embodiment is described in detail as follows: In the embodiment, since vi a-crack always occurs on the metal pattern, in addition to electrostatic discharge (ESD) as a possible cause, another possible cause is the inner metal dielectric layer. (IMD). In order to find out the real reason, this embodiment prepared two wafers with the same elements, and replaced the metal layer of one of them with the insulating layer of the same pattern: ★ Prepare a semiconductor wafer according to the conventional method Semiconductor devices such as Mos are fabricated on the substrate, and an inner metal dielectric layer (IMD) is formed on the Al Cu metal layer. On the other hand, another semiconductor with the same elements is made, but a silicon nitride insulating layer with the same pattern is used to replace the aforementioned AlCu metal layer. The silicon nitride insulating layer is made by pE_CVD method. The thickness is about 7000 Angstroms, which is equivalent to the thickness of the metal layer. The I layer in this embodiment is made by the following method: firstly, a first dielectric layer having a thickness of about 2000 angstroms is deposited by a PE CVD method; and then a SA-CVD method (sub-pressure chemical vapor deposition method) is used An oxide layer with a thickness of about 5000 angstroms is formed, and then a cover oxide layer with a thickness of about 2000 angstroms is deposited by a PE-CVD method. Subsequently, the spin-coated glass layer (s0G) with a thickness of about 600 angstroms was first flattened, and after being completely etched back, a PE-CVD method was used to form a brother with a thickness of about OO angstroms. Two dielectric layers complete the fabrication of the inner metal dielectric layer. The above two wafers are subjected to the same knee washing procedure: under the condition of spin off, cleaning with a nozzle diameter of 0.2 mm (please refer to another case in the joint trial by the inventors of this case: "^ I c

Five 'Invention description (5) method used to detect the impact of stress caused by the scrubber cleaning process'). After cleaning the wafer, the number of via _ crack defects was scanned by KLA. The results are shown in Table 2: Table 2 Number of defects under process conditions AlCu + IMD > 100 S13N4 + IMD > 100 As can be seen from the above table, even with the same pattern Via-crack will still appear if the insulating layer replaces the original AlCu metal layer. It can be seen that the occurrence of via_crack is indeed not related to electrostatic discharge and should be the result of stress. It can be known from the foregoing that the present invention does provide a simple and effective method 'to quickly confirm whether ESD is the cause of the defect. Although the present invention has been disclosed as above with a preferred embodiment, but it is also used to limit the present invention. Anyone skilled in this art can not make any changes but can use various modifications and decorations. ^ The scope of Japanese precision protection shall be determined by the scope of the attached patent application. x 明 之 保

Attached sheet Electrostatic field (KV / inch) Via-crack number Via-crack wafer number total wafer number Teflon chuck-4 * — 5 2 2 4 conductor chuck 0.5 to 0.8 6 5 8 process condition defect number AlCu + IMD > 100 S13N4 + IMD > 100 C: \ Program Files \ Patent \ 0503-3793-E.ptd page

Claims (1)

6 'Patent Application Scope h 丨 · A method for confirming whether electrostatic discharge (ESD) is the cause of a defect in an IC process, the method includes the following steps: Ca) providing a first wafer on which a semiconductor element is formed, It includes at least one metal layer; (b) providing a second wafer on which the same conductive element as the first wafer is formed, but in which the metal layer is replaced by an insulating layer; ~ (c) the above The two wafers are subjected to any identical processing unit, and a defect caused by a suspected electrostatic discharge appears on the first wafer; and (d) comparing whether the second wafer appears with the first wafer and ^ 'if If yes, it means that the above defect is not the same as that of electrostatic discharge. It means that electrostatic discharge is the cause of the defect. 2. The method described in item 1 of the scope of patent application, wherein the insulating layer and the metal layer of the first wafer have the same pattern. Second wafer 3 • The confirmation method described in item 2 of the scope of patent application, the material of the read insulation layer is silicon nitride. ′ Among them 4. The method described in item 1 of the scope of patent application, wherein a yuan includes: other processes of subjecting the above-mentioned two wafers to the same scrubber and treating the defects caused by electrostatic discharge alone. 5 Same doubts 5. The method as described in item 1 of the scope of patent application, wherein the above includes an inner metal dielectric layer. The metal layer C: \ ProgramFiles \ Patent \ 0503-3793-E.ptd page 9