KR20010065863A - A method for forming metal film pattern for eliminating polymer - Google Patents
A method for forming metal film pattern for eliminating polymer Download PDFInfo
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- KR20010065863A KR20010065863A KR1019990066876A KR19990066876A KR20010065863A KR 20010065863 A KR20010065863 A KR 20010065863A KR 1019990066876 A KR1019990066876 A KR 1019990066876A KR 19990066876 A KR19990066876 A KR 19990066876A KR 20010065863 A KR20010065863 A KR 20010065863A
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- polymer
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 229920000642 polymer Polymers 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010937 tungsten Substances 0.000 claims abstract description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 3
- 239000011737 fluorine Substances 0.000 claims abstract description 3
- 239000000460 chlorine Substances 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 claims 8
- 239000010409 thin film Substances 0.000 claims 4
- 238000005406 washing Methods 0.000 claims 4
- 238000004380 ashing Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 229910015844 BCl3 Inorganic materials 0.000 abstract 1
- 239000004411 aluminium Substances 0.000 abstract 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 10
- 229910052799 carbon Inorganic materials 0.000 description 10
- 239000002904 solvent Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 150000001412 amines Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 125000005647 linker group Chemical group 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XIJXHOVKJAXCGJ-XLPZGREQSA-N 1-[(2r,4s,5r)-4-hydroxy-5-(hydroxymethyl)oxolan-2-yl]-5-iodopyrimidin-2-one Chemical compound C1[C@H](O)[C@@H](CO)O[C@H]1N1C(=O)N=CC(I)=C1 XIJXHOVKJAXCGJ-XLPZGREQSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 150000002221 fluorine Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000003446 ligand Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 235000012434 pretzels Nutrition 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 금속막 식각 공정 시에 발생하는 폴리머 제거 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for removing a polymer generated during a metal film etching process.
반도체 소자 제조분야에 있어서, 여러 공정 중 각 개별소자간의 전기적 연결을 위한 패턴의 형성이 필수적으로 요구되고 있다.In the semiconductor device manufacturing field, it is essential to form a pattern for electrical connection between individual devices among various processes.
상기와 같은 각 개별소자간의 전기적 연결을 위한 패턴 형성을 위해서는 일반적으로 금속이 많이 사용이 되는데, 특히 알루미늄(Al) 또는 텅스텐(W)이 주로 사용되고 있다.In order to form a pattern for the electrical connection between each individual element as described above, metal is generally used. In particular, aluminum (Al) or tungsten (W) is mainly used.
여기서, 종래기술에 따른 금속배선 패턴 형성 공정은 통상적으로 금속막 식각과 감광막 제거 및 세정공정의 2단계로 나누어지는데, 이를 각각 살펴보기로 한다.Here, the metallization pattern forming process according to the prior art is generally divided into two stages of metal film etching, photoresist film removal, and cleaning process, which will be described.
먼저, 상기 금속식각과 감광막 제거공정을 살펴보면, 소정의 공정을 마친 실리콘 기판 상부에 금속배선을 위한 금속막인 Al 또는 W을 증착한다.First, referring to the metal etching and photoresist removing process, Al or W, which is a metal film for metal wiring, is deposited on the silicon substrate after the predetermined process.
다음으로 금속막의 불필요한 부분을 제거하기 위해 식각마스크로서 감광막을 형성하고 금속막을 식각한다.Next, in order to remove unnecessary portions of the metal film, a photosensitive film is formed as an etching mask and the metal film is etched.
이때, 금속막 식각은 Cl2, BCl3, N2, Ar 등의 가스를 사용한 플라즈마 건식식각법을 통상적으로 사용하고, 감광막 제거시는 감광막 스트리퍼(Photo Resister Stripper)에서 600sccm 이하의 유량을 가진 O2가스를 이용하여 제거를 하게 된다.At this time, the metal film etching is commonly used a plasma dry etching method using a gas such as Cl 2 , BCl 3 , N 2 , Ar, and when removing the photoresist, O having a flow rate of 600 sccm or less in the photo resist stripper (Photo Resister Stripper) 2 gas is used for removal.
다음으로 세정공정을 수행하게 되는데, 통상적으로 세정공정을 위해서는 여러가지 장비가 필요하게 된다. 구체적으로 살펴보면, 솔벤트 수조1(Solvent Bath)1, 솔벤트 수조2(Solvent Bath2), IPA수조(IPA Bath), QDR수조(Quick DumpRinse Bath), 최종린스수조(Final Rinse Bath) 및 회전건조장치(Spin Dryer)를 사용하고 있다.Next, the cleaning process is performed, and in general, various equipments are required for the cleaning process. Specifically, Solvent Bath 1, Solvent Bath 2, IPA Bath, IPDR Bath, Quick DumpRinse Bath, Final Rinse Bath, and Spin Dryer Dryer) is used.
여기서, 세정을 위한 화학용액으로써, 아민계열의 유기용매인 ACT935용액을 주 용액으로 사용하게 되는데, 상기 솔벤트 수조1(Solvent Bath)1 및 솔벤트 수조2(Solvent Bath2)에서 사용을 하게 된다. 그러나, 통상적으로는 상기 솔벤트 수조2(Solvent Bath2)까지 거치지 않고 상기 솔벤트 수조1(Solvent Bath1)에서 하부층이 손상되지 않을 정도의 적당한 시간 동안 디핑(Dipping)을 하게 된다.Here, as a chemical solution for cleaning, An amine-based organic solvent, ACT935, is used as a main solution, and is used in the Solvent Bath 1 and the Solvent Bath 2. However, dipping is usually performed for a suitable time such that the lower layer is not damaged in the solvent bath 1 without passing through the solvent bath 2.
다음으로, ACT935용액을 희석하기 위하여 IPA(Isoprophil Alcohl)용액이 담겨진 IPA수조를 거치게 되고, 웨이퍼 상에 정전기로 인한 파티클(Particle)이 달라붙는 것을 방지하기 위하여 QDR수조 및 최종린스수조를 거쳐, 마지막으로 회전건조방식(Spin Dry)으로 건조시켜 금속배선 패턴을 완성하게 된다.Next, to dilute the ACT935 solution, an IPA bath containing IPA (Isoprophil Alcohl) solution is used, and a QDR tank and a final rinse tank are used to prevent particles from sticking to the wafer. By drying by spin drying method to complete the metal wiring pattern.
다음으로, 결과물 전면에 IMD(Inter Metal Dielectric)를 형성하게 된다.Next, IMD (Inter Metal Dielectric) is formed on the entire surface of the result.
그러나, Al 또는 W을 사용한 금속배선 패턴 형성 공정에서 선형 중합체(Polymer)의 소오스라 할 수 있는 카본 소오스(Carbon source)가 발생, 성장하여 결국 상기 IMD공정을 수행할 때 상기 카본 소오스의 급성장으로 인해 여러가지 문제가 발생하고 있다.However, in the metallization pattern forming process using Al or W, a carbon source, which is a source of a linear polymer, is generated and grown, resulting in the rapid growth of the carbon source when the IMD process is performed. There are various problems.
상기 문제점에 대해서 도면을 참조하여 보다 구체적으로 살펴본다.The problem will be described in more detail with reference to the accompanying drawings.
도 1a는 IMD공정 수행 전까지의 단계인, 증착된 Al을 식각하고 감광막 제거까지 진행된 금속배선의 패턴이 도시되어 있다.FIG. 1A shows a pattern of metallization, which is a step before etching of the IMD process and etching the deposited Al and removing the photoresist.
이때, 도시된 바와 같이 금속배선 패턴의 측벽부분에 카본 소오스(10)가 발생한 것을 알 수가 있다. 여기서 카본 소오스(10)의 분자구조를 살펴보면 다음과 같다.At this time, it can be seen that the carbon source 10 is generated in the side wall portion of the metal wiring pattern. Here, the molecular structure of the carbon source 10 is as follows.
- C - C - C - C --C-C-C-C-
│ │ │ ││ │ │ │
- C - C - C - C --C-C-C-C-
여기서, 카본 소오스(10)는 그 형태를 정확히 확인할 수가 없으나, 중합체(Polymer)의 형태의 모습으로 된다는 것으로 추정된다.Here, the carbon source 10 cannot be accurately identified, but is assumed to be in the form of a polymer.
한편, 카본 소오스(10)로 판단되는 시드(Seed)의 카본 결합 각도가 106°를 형성하고, 결합기가 4개의 구조를 가지고 있어 선형 뿐만 아니라 3차원 가교 결합도 가능하기 때문에, 도 1d에 도시된 바와 같이 꽈배기처럼 꼬이는 형태 및 그물망 구조를 가질 수도 있어 다양하게 성장됨을 도 1b와 같이 도시하였다.On the other hand, since the carbon bonding angle of the seed determined to be the carbon source 10 forms 106 °, and the bonding group has four structures, not only linear but also three-dimensional crosslinking is possible, As shown in Figure 1b it can have a variety of twisted shape and net structure as a pretzel as shown in Figure 1b.
다음으로, 도 1c는 금속패턴 형성 후의 공정인 IMD형성을 수행함에 따라 상기 카본 소오스(10)가 완전한 중합체로 성장하게 됨을 도시하였다. 여기서 상기 중합체의 구성을 살펴보면, SiONCH + CO2의 구성으로 이루어진다.Next, FIG. 1C shows that the carbon source 10 grows into a complete polymer as the IMD formation is performed after the metal pattern is formed. Looking at the configuration of the polymer here, it consists of a configuration of SiONCH + CO 2 .
도 2a는 FIB(Focused Ion Beam)로 확인한 선형 중합체의 모습을 나타낸 것으로써, 상기와 같이 성장된 선형중합체가 기 형성된 금속배선 패턴을 덮고 있는 층간 절연막을 뚫고 나와 있는 것을 알 수가 있다. 이와 같은 현상은 층간절연막의 손상뿐만 아니라 후속공정 전반에 걸쳐 악영향으로 작용할 수가 있다.FIG. 2A illustrates a linear polymer as confirmed by a focused ion beam (FIB), and it can be seen that the linear polymer grown as described above penetrates the interlayer insulating layer covering the metal wiring pattern. Such a phenomenon may not only damage the interlayer insulating film, but may also adversely affect the subsequent processes.
그리고, 도 2b는 또 다른 금속배선과의 연결을 위한 비아홀 형성 후의 모습을 주사전자현미경(Scanning Electronic Microscope, SEM)으로 찍은 사진으로써,사진에서 알 수 있듯이 상기 선형 중합체의 성장으로 인하여 비아홀의 형성에 있어서도 문제점으로 작용하고 있음을 알 수가 있다. 또한, 도 2c는 상기 도 2b를 확대한 사진이다.And, Figure 2b is a photograph taken after the formation of the via hole for the connection with another metal wiring with a scanning electron microscope (Scanning Electronic Microscope, SEM), as can be seen in the formation of the via hole due to the growth of the linear polymer as shown in the photo It can be seen that it also acts as a problem. 2C is an enlarged photograph of FIG. 2B.
그리고, 도 3 또한 주사전자현미경(Scanning Electronic Microscope, SEM) 사진으로 금속배선 형성 후 금속배선간에 상기 선형 중합체가 잔유물로써 존재하고 있음을 나타내고 있다.In addition, FIG. 3 also shows that the linear polymer is present as a residue between the metal wires after forming the metal wires by scanning electron microscope (SEM) photograph.
상기 언급한 바와같이, 상기 선형중합체의 발생 및 그에 따른 성장이 후속공정, 즉 층간절연막의 형성 및 비아홀 형성 등의 후속공정 진행에의 문제점뿐만 아니라, 반도체 소자의 프로브(Probe) 테스트 시 DC 레벨에서 먼저 테스트를 거친 후 AC 레벨에서 여러가지 테스트를 진행하게 되는데, 첫 단계인 DC 레벨에서 페일(Fail)이 발생하는 문제점이 대두되고 있다.As mentioned above, the generation and growth of the linear polymer is not only a problem in the subsequent process, that is, the formation of the interlayer insulating film and the formation of the via hole, but also at the DC level during the probe test of the semiconductor device. After the test, various tests are conducted at the AC level, and the problem of failing at the first level, the DC level, is emerging.
본 발명은 상술한 바와 같은 문제점을 해결하기 위하여 안출된 것으로써, 금속막 식각 시 발생하는 중합체의 근본적 제거를 통하여 각 개별소자의 특성을 향상시키고 반도체 소자의 불량률을 감소시켜 보다 신뢰성을 가질 수 있는 반도체 소자를 제공하는데 그 목적이 있다.The present invention has been made to solve the problems described above, it is possible to improve the characteristics of each individual device through the fundamental removal of the polymer generated during metal film etching and to reduce the defect rate of the semiconductor device can be more reliable The object is to provide a semiconductor device.
도1a 내지 도1d는 Al 식각 시 발생한 카본소오스가 중합체로 성장됨을 도시한 도면.Figures 1a to 1d is a view showing that the carbon source generated during Al etching is grown into a polymer.
도2a는 FIB로 확인한 선형 중합체의 모습.Figure 2a is a view of a linear polymer confirmed by FIB.
도2b는 비아홀 형성 후의 모습을 주사전자현미경으로 찍은 사진.Figure 2b is a photograph taken after the formation of the via hole with a scanning electron microscope.
도2c는 상기 도2b를 확대한 사진.Figure 2c is an enlarged photograph of the Figure 2b.
도3은 주사전자현미경으로 금속배선 형성 후 금속배선간에 중합체가 잔유물로써 존재하고 있음을 찍은 사진.Figure 3 is a photograph showing that the polymer is present as a residue between the metal wiring after forming the metal wiring with a scanning electron microscope.
도4는 본 발명의 일실시예에 따라 중합체를 제거한 후의 모습을 주사전자현미경으로 찍은 사진.Figure 4 is a photograph taken with a scanning electron microscope after removing the polymer according to an embodiment of the present invention.
상기 목적을 달성하기 위한 본 발명은, 중합체 제거를 위한 금속막 패턴 형성방법에 있어서, 금속막 상에 식각마스크로서 감광막 패턴을 형성하는 제1 단계; 클로오린계 가스의 플라즈마하에서 상기 금속막을 식각하는 제2 단계; 상기 제2 단계가 수행된 반응실에서 플루오린계 가스 플라즈마 처리하는 제3 단계; 상기 감광막 패턴을 제거하는 제4 단계; 및 세정하는 제5 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a metal film pattern forming method for removing a polymer, the method comprising: forming a photoresist pattern as an etching mask on a metal film; Etching the metal film under plasma of chlorine-based gas; A third step of performing a fluorine-based gas plasma treatment in the reaction chamber in which the second step is performed; A fourth step of removing the photoresist pattern; And a fifth step of cleaning.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기로 한다.Hereinafter, a person skilled in the art to which the present invention pertains will be described in detail so that the technical spirit of the present invention can be easily implemented.
먼저, Al 및 감광막 패턴이 형성된 기판을 Al식각 챔버(Etch Chamber)에 넣고 클로오린(Chluorine)계열의 가스, 즉 Cl2또는 BCl3와 같은 가스를 주 식각가스로 하고 여기에 N2및 Ar과 같은 가스가 첨가된 혼합가스를 이용하는 플라즈마 건식식각 방법을 사용하여 Al을 식각한다.First, the substrate on which Al and the photoresist pattern is formed is placed in an Al etching chamber, and a gas such as chlorine-based gas, such as Cl 2 or BCl 3 , is used as the main etching gas, and N 2 and Ar Al is etched using a plasma dry etching method using a mixed gas to which the same gas is added.
이때, 식각 후에 다시 전기음성도가 큰 플루오린(Fluorine)계열의 가스인 CF4가스 플라즈마 처리를 추가로 실시하여, 상기 식각 시에 발생한 카본 소오스, 즉 선형 중합체의 긴 사슬을 일정한 크기로 잘라내게 한다.At this time, after etching, a CF 4 gas plasma treatment, which is a fluorine series gas having a high electronegativity, is further performed to cut a long chain of a carbon source, that is, a linear polymer, generated at the time of etching. do.
또한, 다음 공정인 감광막 제거장치(Photo Resister Stripper)에서 수행되는 감광막 제거를 보다 용이하게 하기 위하여, 상기 Al식각챔버에서 O2가스 처리를 일차로 실시하여 노광공정 등으로 인하여 약간 변형된 상기 감광막의 표면 일부를 제거한다.In addition, in order to more easily remove the photoresist film, which is performed in the next step, the photo resist stripper, the Al etching chamber is primarily subjected to O 2 gas treatment so that the photoresist film is slightly deformed due to an exposure process. Remove part of the surface.
다음으로, 남아있는 상기 감광막을 제거하기 위하여 상기 식각챔버에 있던반도체 기판을 감광막 제거장치(Photo Resister Stripper)로 이동한 후 O2가스를 이용하여 상기 감광막을 제거하게 된다.Next, in order to remove the remaining photoresist, the semiconductor substrate in the etching chamber is moved to a photo resist stripper, and then the photoresist is removed using O 2 gas.
이때, 본 실시예에서는 상기 종래기술에 비해 감광막 제거 시 사용하는 O2가스의 양을 600sccm 내지 1000sccm으로 증가를 시켜 선형 중합체의 길이를 더 작게 만든다.In this embodiment, the length of the linear polymer is made smaller by increasing the amount of O 2 gas used to remove the photoresist film to 600 sccm to 1000 sccm, compared to the conventional art.
상기와 같이 감광막 제거까지 마치게 되면, 세정공정으로 들어가게 된다.When the photoresist film is removed as described above, the cleaning process is started.
먼저, ACT935 용액이 담긴 제1솔벤트수조 및 제2솔벤트수조에 상기 감광막dl 제거된 반도체 기판을 담그게 된다.First, the semiconductor substrate from which the photosensitive film dl is removed is immersed in the first solvent bath and the second solvent bath containing the ACT935 solution.
이때, 상기 제1솔벤트수조 및 제2솔벤트수조에서의 온도는 75℃ 내지 95℃에서 진행을 하고, 담그는 시간은 300″ 내지 1200″의 시간동안 진행을 한다.At this time, the temperature in the first solvent bath and the second solvent bath proceeds at 75 ℃ to 95 ℃, the soaking time proceeds for a time of 300 "to 1200".
여기서, ACT935용액의 성분은 아민(〓NH)성분으로 이루어져 있어서, 니트로겐(Nitrogen)기의 결합기가 2개인 곳에 선형 중합체의 에틸기(Etyle, -C2H5) 및 메틸기(Methyl, -CH3)가 결합을 하게된다. 그 결과, 화학결합에 의한 리간드(Rigand)를 형성하여 선형 중합체를 대부분 제거하게 된다.Here, the component of the ACT935 solution consists of an amine (〓NH) component, where the ethyl group (Etyle, -C 2 H 5 ) and the methyl group (Methyl, -CH 3 ) of the linear polymer are provided at two bonding groups of the nitrogen group. ) Will be combined. As a result, ligands are formed by chemical bonding to remove most of the linear polymer.
다음으로, ACT935 용액을 희석시키기 위하여 IPA(Isoprophil alcohl)용액이 담긴 수조에 반도체 기판을 담그게 된다.Next, in order to dilute the ACT935 solution, the semiconductor substrate is immersed in a bath containing IPA (Isoprophil alcohl) solution.
이때, ACT935 용액 자체도 카본기(Carbon)를 함유하고 있기 때문에, 완벽한 중합체 발생요인의 제거를 위하여 담그는 시간을 60″내지 400″의 조건을 사용한다.At this time, since the ACT935 solution itself also contains a carbon group, a soaking time of 60 ″ to 400 ″ is used to remove the perfect polymer generating factor.
다음으로, 웨이퍼 상에 정전기로 인한 파티클(Particle)이 달라붙는 것을 방지하기 위하여 QDR(Quick Dump Rinse)수조 및 최종린스수조를 거친 후, 마지막으로 기상건조방식(Vapor Dry)으로 건조시켜 Al을 사용한 금속배선 패턴을 완성하게 된다.Next, in order to prevent particles from sticking to the wafer due to static electricity, after passing through a QDR (Quick Dump Rinse) tank and a final rinse tank, and finally drying by using a vapor dry method (Vapor Dry) The metallization pattern is completed.
도 4는 본 발명의 일실시예의 방법에 따라 선형 중합체를 제거한 후의 모습을 주사전자현미경(Scanning Electronic Microscope, SEM)으로 찍은 사진으로써, 깨끗한 금속배선 패턴 형성이 이루어짐을 알 수가 있다.Figure 4 is a photograph taken after the removal of the linear polymer according to the method of an embodiment of the present invention by a scanning electron microscope (Scanning Electronic Microscope, SEM), it can be seen that a clean metal wiring pattern is formed.
한편, 본 실시예에서는 금속배선 패턴 형성 시 Al을 사용하여 그 일례로 설명하였으나, 텅스텐(W)을 사용하여 금속배선을 형성할 때도 본 발명은 적용된다.On the other hand, in the present embodiment has been described as an example using Al when forming a metal wiring pattern, the present invention is also applied when forming a metal wiring using tungsten (W).
상기 본 발명의 일실시예에서와 같이 처음의 식각단계에서부터 각 챔버에 소정의 공정변화를 가하여 상기 선형 중합체를 근본적으로 제거하여, 후속공정인 절연물의 증착단계에서 발생하였던 선형 중합체로 인한 문제점을 방지할 수 있다.As in the embodiment of the present invention, the linear polymer is fundamentally removed by applying a predetermined process change to each chamber from the initial etching step, thereby preventing a problem due to the linear polymer generated in the deposition step of the insulator which is a subsequent process. can do.
결국, 반도체 기판의 테스트인 DC 레벨에서의 테스트 실패 확률을 감소시켜 소자의 신뢰성을 확보할 수 있다.As a result, the reliability of the device can be secured by reducing the probability of a test failure at the DC level, which is a test of the semiconductor substrate.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상기 본 발명에 따른 일실시예로써, 반도체 소자의 불량률 감소에 따른 수율 향상 효과가 있다.As an embodiment of the present invention, there is an effect of improving the yield according to the reduction of the defective rate of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030052168A (en) * | 2001-12-20 | 2003-06-26 | 동부전자 주식회사 | Method for metal line patterning of semiconductor device |
| KR100752202B1 (en) * | 2006-09-25 | 2007-08-27 | 동부일렉트로닉스 주식회사 | Method for cleaning semiconductor wafer after etching metal layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030052168A (en) * | 2001-12-20 | 2003-06-26 | 동부전자 주식회사 | Method for metal line patterning of semiconductor device |
| KR100752202B1 (en) * | 2006-09-25 | 2007-08-27 | 동부일렉트로닉스 주식회사 | Method for cleaning semiconductor wafer after etching metal layer |
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