KR20020068621A - Method for manufacturing interconnection of semiconductor device - Google Patents
Method for manufacturing interconnection of semiconductor device Download PDFInfo
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- KR20020068621A KR20020068621A KR1020010008719A KR20010008719A KR20020068621A KR 20020068621 A KR20020068621 A KR 20020068621A KR 1020010008719 A KR1020010008719 A KR 1020010008719A KR 20010008719 A KR20010008719 A KR 20010008719A KR 20020068621 A KR20020068621 A KR 20020068621A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 소자의 특성을 향상시키는데 적당하도록 한 반도체 소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a wiring of a semiconductor device suitable for improving the characteristics of the device.
일반적으로, 배선을 알루미늄을 사용할 경우에 있어서, 배선 형성을 위해 알루미늄을 증착하고 식각한 후 알루미늄 코로젼(Corrosion)을 방지하기 위해서 후처리 공정이 필요하다.In general, in the case of using aluminum as a wiring, a post-treatment process is required to prevent aluminum corrosion after depositing and etching aluminum to form the wiring.
이러한 후처리 공정은 클로린(Chlorine) 플라즈마에서 알루미늄 식각 후 즉각 순수한 물에 담궈 잔류된 클로린을 제거하므로써 코로젼을 방지하고자 하였다.This post-treatment process was intended to prevent coronation by removing residual chlorine by immediately immersing it in pure water after aluminum etching in a chlorine plasma.
코로젼을 방지하기 위한 또 하나의 방법으로서는 인-시튜(In-situ)로 H2O 베이포 플라즈마(Vapor plasma)를 이용하여 잔류된 클로린을 제거하였다.As another method to prevent the coronation, residual chlorine was removed using H 2 O Vapor plasma in-situ.
대부분의 알루미늄 식각장비가 식각 챔버(Chamber)와 H2O 베이포 클리닝(Vapor cleaning)/에싱(ashing) 챔버로 구성된다.Most aluminum etching equipment consists of an etch chamber and a H 2 O vapor cleaning / ashing chamber.
따라서, 식각 후 진공파괴가 없이 H2O 베이포 플라즈마를 형성하여 코로젼을 방지한다.Thus, after etching, H 2 O vapor plasma is formed without vacuum destruction to prevent the co-ordination.
그러나, H2O 플라즈마 클리닝시에 잔류된 클로린의 제거와 더불어 H, O, OH 이온들에 의해 식각 패턴 형성을 위한 감광막이 제거되는 문제를 야기시킨다.However, in addition to the removal of chlorine remaining during the H 2 O plasma cleaning, the photoresist film for forming the etching pattern is removed by the H, O and OH ions.
또한, 감광막의 물질 변화가 발생하여 알루미늄 또는 알루미늄 합금으로 이루어진 배선위에 심한 폴리머(polymer)성 잔류물을 남기게 된다.In addition, a change in the material of the photosensitive film occurs, leaving a severe polymer residue on the wiring made of aluminum or aluminum alloy.
이러한 잔류물은 O2에싱 처리를 하더라도 제거되지 않는다.These residues are not removed even after O 2 ashing treatment.
따라서, 상기 잔류물을 제거하기 위한 방안으로서 아민(Amine)기를 포함하는 용액(예를들어 ACT, EKC 등)이나 강한 산성용액에서 습식지리를 통해 제거하였다.Therefore, the solution was removed by wet geography in a solution containing an amine group (for example, ACT, EKC, etc.) or a strong acidic solution to remove the residue.
이하, 종래 기술에 따른 반도체 소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a wiring of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 소자의 배선 형성방법을 설명하기 위한 공정 단면도이다.1A to 1C are cross-sectional views for describing a wiring forming method of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 절연층(1)상에 제 1 베리어층(2)을 형성한다.As shown in FIG. 1A, the first barrier layer 2 is formed on the insulating layer 1.
그리고, 상기 제 1 베리어층(2)상에 배선용 금속층(3)과 제 2 베리어층(4)을 차례로 형성한다.Then, the wiring metal layer 3 and the second barrier layer 4 are sequentially formed on the first barrier layer 2.
여기서, 상기 제 1, 2 베리어층(2)(4)의 물질로는 Ti/TiN를 이용하고, 상기 금속층(3)은 알루미늄을 이용하여 형성한다.Here, Ti / TiN is used as a material of the first and second barrier layers 2 and 4, and the metal layer 3 is formed using aluminum.
그리고, 상기 제 2 베리어층(4)상에 감광막을 도포한 후 노광 및 현상공정을 통해 감광막 패턴(5)을 형성한다.Then, after the photosensitive film is coated on the second barrier layer 4, the photosensitive film pattern 5 is formed through an exposure and development process.
상기 감광막 패턴(5)을 마스크로 Cl2가스를 포함하는 플라즈마에서 제 2 베리어층(4), 금속층(3), 제 1 베리어층(2)을 차례로 식각한다.The second barrier layer 4, the metal layer 3, and the first barrier layer 2 are etched sequentially in a plasma containing Cl 2 gas using the photoresist pattern 5 as a mask.
이 과정에서 금속층 패턴(3a) 측면 및 잔류 감광막 패턴(5a)에 클로린이 잔류하게 된다.In this process, chlorine remains on the side of the metal layer pattern 3a and the residual photoresist pattern 5a.
이어, 도 1b에 도시한 바와 같이, 인-시튜로 H2O 베이포 플라즈마 클리닝을 실시하여 상기 금속층 패턴(3a) 측면의 클로린을 제거한다.Subsequently, as shown in FIG. 1B, chlorine on the side of the metal layer pattern 3a is removed by performing H 2 O vapor plasma cleaning in-situ.
상기 금속층 패턴(3a) 측면의 클로린은 다음의 화학반응식 H2O + Cl → HCl과 같이 반응하여 제거된다.Chlorine on the side of the metal layer pattern 3a is removed by reacting with the following chemical reaction H 2 O + Cl → HCl.
그러나, 상기 금속층 패턴(3a)에 증착되어 있는 클로린을 포함한 폴리머가 대기 중에 노출될 때 상기 클로린이 대기 중의 H2O와 반응하여 생긴 HCL이 상기 금속층 패턴(3a)을 부식시킬 수 있다.However, when the polymer including chlorine deposited on the metal layer pattern 3a is exposed to the atmosphere, HCL generated by reacting the chlorine with H 2 O in the atmosphere may corrode the metal layer pattern 3a.
이를 해결하기 위해 도 1c에 도시한 바와 같이, 웨이퍼를 진공상태에서 스트립 챔버(Strip chamber)로 옮긴 후, 감광막 패턴(5a)을 제거하는 에싱 공정을 수행함으로써 상기 잔류 감광막 패턴(5a)과 폴리머의 일부가 제거된다.In order to solve this problem, as shown in FIG. 1C, the wafer is transferred to a strip chamber in a vacuum state, and then an ashing process of removing the photoresist pattern 5a is performed to remove the residual photoresist pattern 5a and the polymer. Some are removed.
여기서, 상기 에싱 공정은 CF4/O2을 이용한 에싱을 실시하여 상기 폴리머 및 감광막 패턴(5a)을 제거한다.Here, the ashing process is subjected to ashing using CF 4 / O 2 to remove the polymer and the photoresist pattern 5a.
이때, 부식마진 향상을 위한 패시베이션(Passivation) 단계에서 사용되는 H2O는 클로린 치환능력이 떨어지며, CF4는 폴리머 및 상기 잔류 감광막 패턴(5a) 제거시 하부층 측면에 손상을 주고, 상기 금속층 패턴(3a)과 제 1, 2 베리어층(2a)(4a)의 이종 금속계면 사이에 영향을 주어 들뜨게 한다.At this time, H 2 O used in the passivation step to improve the corrosion margin is inferior in chlorine substitution capacity, CF 4 damages the side of the lower layer when removing the polymer and the residual photoresist pattern (5a), the metal layer pattern ( Influence between 3a) and the dissimilar metal interface of the first and second barrier layers 2a and 4a is exhilarating.
그러나, 상기와 같은 종래의 반도체 소자의 배선 형성방법은 다음과 같은 문제점이 있다.However, the conventional wiring forming method of the semiconductor device has the following problems.
첫째, 클리닝 공정에서 사용하는 H2O는 금속층 패턴 측면에 증착된 클로린을 치환하는데 한계가 있다.First, H 2 O used in the cleaning process has a limitation in substituting chlorine deposited on the side of the metal layer pattern.
둘째, 에싱 공정에 사용하는 CF4는 금속층 패턴의 측면손상 및 금속층과 베리어층 간의 이격을 유발한다.Second, CF 4 used in the ashing process causes side damage of the metal layer pattern and separation between the metal layer and the barrier layer.
본 발명은 이와 같은 종래 기술의 반도체 소자의 배선 형성방법의 문제를 해결하기 위한 것으로, 클리닝 및 에싱 공정에서 클로린 치환능력이 향상되며 금속층패턴의 측면손상을 줄이는데 적당한 반도체 소자의 배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the conventional method of forming the wiring of the semiconductor device, to provide a method of forming a wiring of a semiconductor device suitable for improving the chlorine substitution capacity in the cleaning and ashing process and reducing side damage of the metal layer pattern. The purpose is.
도 1a 내지 도 1c는 종래 기술의 반도체 소자의 배선 형성방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a wiring of a semiconductor device of the prior art.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 배선 형성방법을 나타낸 공정 단면도2A through 2C are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 절연층 22 : 제 1 베리어층21: insulating layer 22: first barrier layer
23 : 금속층 24 : 제 2 베리어층23: metal layer 24: second barrier layer
25 : 감광막 패턴25 photosensitive film pattern
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 배선 형성방법은 절연층상에 제 1 베리어층, 금속층, 제 2 베리어층을 차례로 형성하는 단계; 감광막 패턴을 마스크로 제 2 베리어층, 금속층, 제 1 베리어층을 선택적으로 식각하는 단계; 상기 식각 공정시 발생하는 폴리머를 NH4OH을 포함한 플라즈마 클리닝을 이용하여 제거하는 단계; 잔류하는 상기 폴리머 및 감광막 패턴을 NF3/O2을 이용한 에싱을 실시하여 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a semiconductor device according to the present invention includes forming a first barrier layer, a metal layer, and a second barrier layer on an insulating layer in sequence; Selectively etching the second barrier layer, the metal layer, and the first barrier layer using the photoresist pattern as a mask; Removing the polymer generated during the etching process using plasma cleaning including NH 4 OH; And removing the remaining polymer and photoresist pattern by performing ashing using NF 3 / O 2 .
이하, 본 발명의 반도체 소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 배선 형성방법을 설명하기 위한 공정 단면도이다.2A to 2C are cross-sectional views for illustrating a wiring forming method of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 절연층(21)상에 제 1 베리어층(22)을 형성한다.As shown in FIG. 2A, the first barrier layer 22 is formed on the insulating layer 21.
그리고, 상기 제 1 베리어층(22)상에 배선용 금속층(23)과 제 2 베리어층(24)을 차례로 형성한다.Then, the wiring metal layer 23 and the second barrier layer 24 are sequentially formed on the first barrier layer 22.
여기서, 상기 금속층(23)은 알루미늄 또는 알루미늄 합금을 이용하고, 상기 제 1, 2 베리어층(22)(24)의 물질로는 Ti/TiN를 이용하여 형성한다.Here, the metal layer 23 is formed of aluminum or an aluminum alloy, and the material of the first and second barrier layers 22 and 24 is formed using Ti / TiN.
이는, 현재 알루미늄 식각에 쓰이는 대부분의 식각장비에서 알루미늄과 감광막의 선택비는 1.5:1을 넘지 않는 반면에 나이트라이드 등을 이용한 베리어층을 사용할 시에는 알루미늄과 베리어층의 선택비를 10:1 정도까지 올릴 수 있다.This means that in most etching equipment used for aluminum etching, the selectivity of aluminum and photoresist is not more than 1.5: 1, whereas when using barrier layer using nitride, the selectivity ratio of aluminum and barrier layer is about 10: 1. Can raise up.
이어, 상기 제 2 베리어층(24)상에 감광막을 도포한 후, 노광 및 현상공정을 통해 감광막 패턴(25)을 형성한다.Subsequently, after the photosensitive film is coated on the second barrier layer 24, the photosensitive film pattern 25 is formed through an exposure and development process.
상기 감광막 패턴(25)을 마스크로 Cl2가스를 이용한 플라즈마에서 제 2 베리어층(24), 금속층(23), 제 1 베리어층(22)을 차례로 식각하고, 동시에 부식방지를 위하여 인-시튜 처리를 한다.The second barrier layer 24, the metal layer 23, and the first barrier layer 22 are sequentially etched in a plasma using Cl 2 gas using the photoresist pattern 25 as a mask, and at the same time, in-situ treatment is performed to prevent corrosion. Do
여기서, 상기 Cl2가스를 이용한 플라즈마에서 식각공정을 진행하면 상기 제 1 베리어층(22) 하부의 절연층(21)도 소정깊이로 식각된다.Here, when the etching process is performed in the plasma using the Cl 2 gas, the insulating layer 21 under the first barrier layer 22 is also etched to a predetermined depth.
또한, 상기 식각 공정시 Cl2가스가 상기 금속층 패턴(23a) 및 감광막 패턴(25a)과 반응하여 비휘발성의 폴리머를 형성한다.In the etching process, Cl 2 gas reacts with the metal layer pattern 23a and the photoresist layer pattern 25a to form a nonvolatile polymer.
상기 폴리머는 휘발되지 않고 상기 금속층 패턴(23a)의 측면에 증착된다.The polymer is deposited on the side of the metal layer pattern 23a without volatilization.
그리고, 피치 크기가 감소됨에 따라 금속층 패턴(23a)간 공간이 좁아 이 부분에 증착된 클로린은 쉽게 휘발되지 않게 된다.As the pitch size decreases, the space between the metal layer patterns 23a is narrowed, so that chlorine deposited on this portion is not easily volatilized.
이어, 도 2b에 도시한 바와 같이, NH4OH을 이용한 플라즈마 클리닝을 실시한다.Subsequently, as shown in FIG. 2B, plasma cleaning using NH 4 OH is performed.
이때, 상기 금속층 패턴(25a) 측면에 증착된 클로린은 다음의 화학반응식 NH4OH + Cl → HCl과 같이 반응한다.At this time, the chlorine deposited on the side of the metal layer pattern 25a reacts with the following chemical reaction NH 4 OH + Cl → HCl.
따라서, 부식마진 향상을 위한 패시베이션(Passivation) 단계에서 사용되는 NH4OH는 금속층 패턴(23a) 측면의 클로린을 효율적으로 제거한다.Therefore, NH 4 OH used in the passivation step to improve the corrosion margin effectively removes chlorine on the side of the metal layer pattern 23a.
도 2c에 도시한 바와 같이, NF3/O2을 이용한 에싱을 실시하여 잔존하는 폴리머 및 상기 감광막 패턴(25a)을 제거한다.As shown in Fig. 2C, ashing is performed using NF 3 / O 2 to remove the remaining polymer and the photosensitive film pattern 25a.
그리고, 상기 NF3는 폴리머 및 상기 감광막 패턴(25a) 제거시 상기 금속층 패턴(23a) 측면에 질화막을 형성하여 금속층 패턴(23a)에 대한 비부식 마진(Anti-corrosion margin)을 확보할 수 있다.In addition, the NF 3 may secure a non-corrosion margin with respect to the metal layer pattern 23a by forming a nitride layer on the side of the metal layer pattern 23a when the polymer and the photoresist layer pattern 25a are removed.
상기와 같은 본 발명의 반도체 소자의 배선 형성방법은 다음과 같은 효과가 있다.The wiring forming method of the semiconductor device of the present invention as described above has the following effects.
클리닝 공정에서 NH4OH을 이용한 플라즈마 클리닝 공정으로 금속층 패턴의 측면에 증착된 클로린을 효과적으로 치환할 수 있다.In the cleaning process, a plasma cleaning process using NH 4 OH may effectively replace chlorine deposited on the side of the metal layer pattern.
또한, NF3를 이용한 에싱 공정으로 금속층 패턴 측면에 질화막을 형성하여 금속층 패턴에 대한 비부식 마진을 확보할 수 있다.In addition, a nitride film may be formed on the side of the metal layer pattern by an ashing process using NF 3 to secure a non-corrosive margin for the metal layer pattern.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100432894B1 (en) * | 2001-12-11 | 2004-05-22 | 동부전자 주식회사 | Method for forming metal line of semiconductor device |
| KR100604671B1 (en) * | 2004-07-27 | 2006-07-25 | 주식회사 하이닉스반도체 | Method for forming metal conductive line in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100432894B1 (en) * | 2001-12-11 | 2004-05-22 | 동부전자 주식회사 | Method for forming metal line of semiconductor device |
| KR100604671B1 (en) * | 2004-07-27 | 2006-07-25 | 주식회사 하이닉스반도체 | Method for forming metal conductive line in semiconductor device |
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