JP2007042866A - 半導体装置および半導体チップ - Google Patents
半導体装置および半導体チップ Download PDFInfo
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Abstract
【解決手段】 本発明の半導体装置は、
半導体層10と、
前記半導体層10の上方に設けられた電極パッド20と、
前記電極パッド20の上方にあって、該電極パッド20の少なくとも一部を露出させる開口32を有する絶縁層30と、
少なくとも前記開口32に設けられた金属電極40と、を含み、
前記金属電極40は、
前記電極パッド20の上方に設けられた第1部分40aと、
前記電極パッド20の外側に位置する前記絶縁層30の上方に設けられ、前記第1部分40aと比して上面の面積が大きい第2部分40bとを有する。
【選択図】 図1
Description
半導体層と、
前記半導体層の上方に設けられた電極パッドと、
前記電極パッドの上方にあって、該電極パッドの少なくとも一部を露出させる開口を有する絶縁層と、
少なくとも前記開口に設けられた金属電極と、を含み、
前記金属電極は、
前記電極パッドの少なくとも一部の鉛直上方に設けられた第1部分と、
第1部分と比して上面の面積が大きい第2部分とを有する。
前記絶縁層の上面の高さは、ほぼ同一であることができる。
前記第1部分の上面の高さと前記第2部分の上面の高さとは、ほぼ同一であることができる。
前記第2部分の下方に位置する絶縁層の上に、保護層が設けられていることができる。
平面視において、前記第1部分の幅は前記第2部分の幅と比して小さいことができる。
前記第1部分の下方に位置する前記半導体層は、半導体素子が設けられることのない、禁止領域であって、
前記第2部分の下方に位置する前記半導体層は、素子形成領域であることができる。
配列された複数の金属電極を含む半導体チップであって、
前記複数の金属電極は、電極パッドの少なくとも一部の鉛直上方に位置する第1部分と、該第1部分と比して上面の面積が大きい第2部分とを有し、
前記複数の金属電極の前記第1部分および前記第2部分の少なくとも一方は、千鳥配置されている。
前記複数の金属電極は、
一方の金属電極の前記第1部分と、他方の金属電極の前記第2部分とが隣合い、
前記他方の金属電極の前記第1部分と、前記一方の金属電極の前記第2部分とが隣合うように配置されていることができる。
前記金属電極の配列に沿った方向の前記第2部分の幅は、第1部分の幅と比して大きく、
隣合う前記金属電極の第2部分の一部は、前記金属電極の配列に沿った方向の垂直方向からみて重なっていることができる。
1.1.第1の実施の形態
第1の実施の形態にかかる半導体装置について、図1および図2を参照しつつ説明する。図1は、本実施の形態にかかる半導体装置を模式的に示す断面図であり、図2は、図1に示す半導体装置に含まれる金属電極の平面形状を示す平面図である。なお、図1は、図22のI−I線に沿った断面である。
次に、本実施の形態にかかる半導体装置の変形例について、図3を参照しつつ説明する。本変形例にかかる半導体装置では、上述の実施の形態にかかる半導体装置と比して金属電極40の上面の高さが異なる例である。なお、以下の説明では、本実施の形態にかかる半導体装置と比して異なる点について説明する。
次に、第2の実施の形態にかかる半導体装置について、図4を参照しつつ説明する。図4は、本実施の形態にかかる半導体装置を模式的に示す断面図である。なお、第1の実施の形態と共通する構成および部材については、詳細な説明は省略する。
2.1.第1の実施の形態
次に、第1の実施の形態にかかる半導体チップについて、図5(A)および図5(B)を参照しつつ説明する。図5(A)は、本実施の形態にかかる半導体チップを示す図であり、図5(B)は、図5(A)のA部を拡大して示す平面図である。第2の実施の形態にかかる半導体装置は、第1の実施の形態で説明した金属電極40が複数配列されている。金属電極40の断面構造および平面形状については、1.1.の項の説明を参照されたい。
次に、第2の実施の形態にかかる半導体装置の変形例について図7(A)および図7(B)を参照しつつ説明する。図7(A)は、本実施の形態にかかる半導体チップを示す図であり、図7(B)は、図7(A)のA部を拡大して示す平面図である。
Claims (9)
- 半導体層と、
前記半導体層の上方に設けられた電極パッドと、
前記電極パッドの上方にあって、該電極パッドの少なくとも一部を露出させる開口を有する絶縁層と、
少なくとも前記開口に設けられた金属電極と、を含み、
前記金属電極は、
前記電極パッドの少なくとも一部の鉛直上方に設けられた第1部分と、
第1部分と比して上面の面積が大きい第2部分とを有する、半導体装置。 - 請求項1において、
前記絶縁層の上面の高さは、ほぼ同一である、半導体装置。 - 請求項1または2において、
前記第1部分の上面の高さと前記第2部分の上面の高さとは、ほぼ同一である、半導体装置。 - 請求項1ないし3のいずれかにおいて、
前記第2部分の下方に位置する絶縁層の上に、保護層が設けられている、半導体装置。 - 請求項1ないし4のいずれかにおいて、
平面視において、前記第1部分の幅は前記第2部分の幅と比して小さい、半導体装置。 - 請求項1ないし5のいずれかにおいて、
前記第1部分の下方に位置する前記半導体層は、半導体素子が設けられることのない、禁止領域であって、
前記第2部分の下方に位置する前記半導体層は、素子形成領域である、半導体装置。 - 配列された複数の金属電極を含む半導体チップであって、
前記複数の金属電極は、電極パッドの少なくとも一部の鉛直上方に位置する第1部分と、該第1部分と比して上面の面積が大きい第2部分とを有し、
前記複数の金属電極の前記第1部分および前記第2部分の少なくとも一方は、千鳥配置されている、半導体チップ。 - 請求項7において、
前記複数の金属電極は、
一方の金属電極の前記第1部分と、他方の金属電極の前記第2部分とが隣合い、
前記他方の金属電極の前記第1部分と、前記一方の金属電極の前記第2部分とが隣合うように配置されている、半導体チップ。 - 請求項7または8において
前記金属電極の配列に沿った方向の前記第2部分の幅は、第1部分の幅と比して大きく、
隣合う前記金属電極の第2部分の一部は、前記金属電極の配列に沿った方向の垂直方向からみて重なっている、半導体チップ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2005225450A JP4251164B2 (ja) | 2005-08-03 | 2005-08-03 | 半導体装置および半導体チップ |
US11/497,577 US7638886B2 (en) | 2005-08-03 | 2006-08-02 | Semiconductor device and semiconductor chip |
CNB2006100991936A CN100505224C (zh) | 2005-08-03 | 2006-08-02 | 半导体装置及半导体芯片 |
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JP2005225450A JP4251164B2 (ja) | 2005-08-03 | 2005-08-03 | 半導体装置および半導体チップ |
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JP2007042866A true JP2007042866A (ja) | 2007-02-15 |
JP4251164B2 JP4251164B2 (ja) | 2009-04-08 |
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JP2005225450A Expired - Fee Related JP4251164B2 (ja) | 2005-08-03 | 2005-08-03 | 半導体装置および半導体チップ |
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US (1) | US7638886B2 (ja) |
JP (1) | JP4251164B2 (ja) |
CN (1) | CN100505224C (ja) |
Cited By (2)
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JP2015015505A (ja) * | 2014-10-24 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2019102803A (ja) * | 2017-11-28 | 2019-06-24 | 旭化成エレクトロニクス株式会社 | 半導体パッケージ及びカメラモジュール |
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KR100773097B1 (ko) * | 2006-08-22 | 2007-11-02 | 삼성전자주식회사 | 패드를 갖는 반도체 소자 |
US20090102679A1 (en) * | 2007-10-19 | 2009-04-23 | Optimal Innovations Inc. | Infrastructure device with removable face plate for remote operation |
US8383949B2 (en) * | 2009-12-29 | 2013-02-26 | Intel Corporation | Method to form lateral pad on edge of wafer |
KR102450326B1 (ko) | 2015-10-06 | 2022-10-05 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
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JPH01152746A (ja) | 1987-12-10 | 1989-06-15 | Nec Corp | 半導体装置 |
JPH02278864A (ja) | 1989-04-20 | 1990-11-15 | Nec Corp | 半導体装置の入力保護回路 |
US5404047A (en) * | 1992-07-17 | 1995-04-04 | Lsi Logic Corporation | Semiconductor die having a high density array of composite bond pads |
US5444303A (en) * | 1994-08-10 | 1995-08-22 | Motorola, Inc. | Wire bond pad arrangement having improved pad density |
JPH0922912A (ja) | 1995-07-05 | 1997-01-21 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
JPH09237800A (ja) | 1996-02-29 | 1997-09-09 | Toshiba Corp | 半導体装置 |
KR100210711B1 (ko) * | 1996-10-01 | 1999-07-15 | 윤종용 | 반도체 칩 구조 |
US6882030B2 (en) * | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
EP0881686A3 (en) * | 1997-05-28 | 2000-04-19 | Oki Data Corporation | LED array and LED printer head |
JPH1140754A (ja) * | 1997-07-17 | 1999-02-12 | Mitsubishi Electric Corp | 半導体装置 |
KR100295637B1 (ko) * | 1997-12-29 | 2001-10-24 | 김영환 | 반도체웨이퍼의구조및반도체칩의제조방법 |
JP2000022206A (ja) * | 1998-07-01 | 2000-01-21 | Oki Electric Ind Co Ltd | 半導体発光装置 |
JP2000340696A (ja) | 1999-05-31 | 2000-12-08 | Matsushita Electric Works Ltd | 半導体パッケージの製造方法 |
JP3659112B2 (ja) * | 2000-02-03 | 2005-06-15 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP2001264391A (ja) | 2000-03-17 | 2001-09-26 | Mitsubishi Materials Corp | 電極端子及び該電極端子を有する回路素子 |
JP2001338955A (ja) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JP2003060051A (ja) | 2001-08-10 | 2003-02-28 | Rohm Co Ltd | 半導体集積回路装置及びそれを用いた電子装置 |
JP3785442B2 (ja) | 2001-11-21 | 2006-06-14 | 大日本印刷株式会社 | 半導体装置の製造方法 |
JP2003309120A (ja) | 2002-04-15 | 2003-10-31 | Mitsubishi Electric Corp | 半導体装置 |
JP2003332448A (ja) * | 2002-05-14 | 2003-11-21 | Mitsubishi Electric Corp | 半導体装置 |
JP3871609B2 (ja) * | 2002-05-27 | 2007-01-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP3986989B2 (ja) * | 2003-03-27 | 2007-10-03 | 松下電器産業株式会社 | 半導体装置 |
US6856022B2 (en) * | 2003-03-31 | 2005-02-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US7064450B1 (en) * | 2004-05-11 | 2006-06-20 | Xilinx, Inc. | Semiconductor die with high density offset-inline bond arrangement |
US7235412B1 (en) * | 2004-05-11 | 2007-06-26 | Xilinx, Inc. | Semiconductor component having test pads and method and apparatus for testing same |
US6953997B1 (en) * | 2004-06-04 | 2005-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with improved bonding pad connection and placement |
-
2005
- 2005-08-03 JP JP2005225450A patent/JP4251164B2/ja not_active Expired - Fee Related
-
2006
- 2006-08-02 US US11/497,577 patent/US7638886B2/en not_active Expired - Fee Related
- 2006-08-02 CN CNB2006100991936A patent/CN100505224C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015015505A (ja) * | 2014-10-24 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2019102803A (ja) * | 2017-11-28 | 2019-06-24 | 旭化成エレクトロニクス株式会社 | 半導体パッケージ及びカメラモジュール |
Also Published As
Publication number | Publication date |
---|---|
CN100505224C (zh) | 2009-06-24 |
CN1909225A (zh) | 2007-02-07 |
US20070045837A1 (en) | 2007-03-01 |
JP4251164B2 (ja) | 2009-04-08 |
US7638886B2 (en) | 2009-12-29 |
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