JP2007103853A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007103853A JP2007103853A JP2005294940A JP2005294940A JP2007103853A JP 2007103853 A JP2007103853 A JP 2007103853A JP 2005294940 A JP2005294940 A JP 2005294940A JP 2005294940 A JP2005294940 A JP 2005294940A JP 2007103853 A JP2007103853 A JP 2007103853A
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- semiconductor device
- external electrode
- film
- conductor pattern
- layer
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Abstract
【解決手段】半導体装置1は、BGA型の半導体装置であり、半導体チップ10、樹脂層20、絶縁層30、および外部電極パッド40を備えている。樹脂層20は、封止樹脂22およびアンダーフィル樹脂24によって構成され、半導体チップ10を覆っている。樹脂層20上には、絶縁層30が形成されている。絶縁層30中には、外部電極パッド40が形成されている。この外部電極パッド40は、絶縁層30を貫通しており、その一面S1が絶縁層30の表面に露出するとともに、他面S2が樹脂層20の内部に位置している。外部電極パッド40の面S2には、凹部45が形成されている。この凹部45内には、樹脂層20を構成する樹脂が入り込んでいる。
【選択図】図1
Description
(第1実施形態)
(第2実施形態)
2 半導体装置
10 半導体チップ
12 電極端子
20 樹脂層
22 封止樹脂
24 アンダーフィル樹脂
30 絶縁層
40 外部電極パッド
42 下層パッドメタル
44 上層パッドメタル
45 凹部
46 中間層パッドメタル
48 配線
50 電極バンプ
60 半田バンプ
Claims (13)
- 半導体チップと、
前記半導体チップを覆う樹脂層と、
前記樹脂層上に設けられた絶縁層と、
前記絶縁層を貫通するように設けられ、一面が前記絶縁層の表面に露出し、当該一面に外部電極端子が接続される外部電極パッドと、を備え、
前記外部電極パッドの他面には凹部が設けられており、当該凹部内に前記樹脂層を構成する樹脂が入り込んでいることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記外部電極パッドは、前記絶縁層中に設けられた第1の導体パターンと、前記樹脂層中に設けられた第2の導体パターンとを含んでおり、
前記第2の導体パターンに、前記凹部が設けられている半導体装置。 - 請求項2に記載の半導体装置において、
前記第1および第2の導体パターンの間に設けられた第3の導体パターンを備える半導体装置。 - 請求項2または3に記載の半導体装置において、
前記凹部の深さは、前記第2の導体パターンの厚みに略等しい半導体装置。 - 請求項2乃至4いずれかに記載の半導体装置において、
前記第2の導体パターンは、相異なる複数の金属膜によって構成された積層構造を有している半導体装置。 - 請求項5に記載の半導体装置において、
前記積層構造は、第1の金属膜と、当該第1の金属膜の前記第1の導体パターンと反対側の面上に設けられた第2の金属膜とによって構成されており、
前記第1および第2の金属膜にはそれぞれ、互いに連設されて前記凹部を構成する第1および第2の開口が設けられており、
前記第1の開口は、前記第2の開口に比して開口面積が大きい半導体装置。 - 請求項6に記載の半導体装置において、
前記第1および第2の金属膜は、それぞれCu膜およびNi膜である半導体装置。 - 請求項2乃至7いずれかに記載の半導体装置において、
前記第1の導体パターンは、相異なる複数の金属膜によって構成された積層構造を有している半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の導体パターンが有する前記積層構造は、Cu膜と、当該Cu膜の前記第2の導体パターン側の面上に設けられたNi膜とによって構成されている半導体装置。 - 請求項2乃至9いずれかに記載の半導体装置において、
前記第1の導体パターンは、側面の略全体が前記絶縁層で覆われるとともに、前記第2の導体パターンと反対側の面の略全体が前記絶縁層の表面に露出している半導体装置。 - 請求項1乃至10いずれかに記載の半導体装置において、
前記凹部の開口面の面積は、当該凹部の底面の面積よりも小さい半導体装置。 - 請求項1乃至11いずれかに記載の半導体装置において、
複数の前記凹部が1つの前記外部電極パッドに設けられている半導体装置。 - 請求項12に記載の半導体装置において、
前記複数の凹部は、平面視で規則的に配列されている半導体装置。
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JP2005294940A JP5000877B2 (ja) | 2005-10-07 | 2005-10-07 | 半導体装置 |
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JP2008084959A (ja) * | 2006-09-26 | 2008-04-10 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
WO2010013470A1 (ja) * | 2008-07-31 | 2010-02-04 | 三洋電機株式会社 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
JP5261255B2 (ja) | 2009-03-27 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN106783633B (zh) * | 2016-12-26 | 2020-02-14 | 通富微电子股份有限公司 | 一种扇出的封装结构及其封装方法 |
IT201700055983A1 (it) * | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti |
JP2019054159A (ja) * | 2017-09-15 | 2019-04-04 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
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