JP2006196899A - ダイの反りが抑制された半導体素子及びその製造方法 - Google Patents

ダイの反りが抑制された半導体素子及びその製造方法 Download PDF

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Publication number
JP2006196899A
JP2006196899A JP2006004185A JP2006004185A JP2006196899A JP 2006196899 A JP2006196899 A JP 2006196899A JP 2006004185 A JP2006004185 A JP 2006004185A JP 2006004185 A JP2006004185 A JP 2006004185A JP 2006196899 A JP2006196899 A JP 2006196899A
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JP
Japan
Prior art keywords
stress relaxation
material layer
semiconductor device
pattern
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006004185A
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English (en)
Japanese (ja)
Other versions
JP2006196899A5 (enExample
Inventor
Hyeoung-Won Seo
亨源 徐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006196899A publication Critical patent/JP2006196899A/ja
Publication of JP2006196899A5 publication Critical patent/JP2006196899A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2006004185A 2005-01-12 2006-01-11 ダイの反りが抑制された半導体素子及びその製造方法 Pending JP2006196899A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050002872A KR100652395B1 (ko) 2005-01-12 2005-01-12 다이-휨이 억제된 반도체 소자 및 그 제조방법

Publications (2)

Publication Number Publication Date
JP2006196899A true JP2006196899A (ja) 2006-07-27
JP2006196899A5 JP2006196899A5 (enExample) 2009-02-12

Family

ID=36695898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006004185A Pending JP2006196899A (ja) 2005-01-12 2006-01-11 ダイの反りが抑制された半導体素子及びその製造方法

Country Status (3)

Country Link
US (2) US7781851B2 (enExample)
JP (1) JP2006196899A (enExample)
KR (1) KR100652395B1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012501077A (ja) * 2008-08-29 2012-01-12 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド チップ・パッケージ相互作用安定性を高めるための応力緩和ギャップを含む半導体デバイス。
US8704226B2 (en) 2011-04-13 2014-04-22 Panasonic Corporation Three-dimensional integrated circuit having redundant relief structure for chip bonding section

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* Cited by examiner, † Cited by third party
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KR102059823B1 (ko) * 2013-06-11 2019-12-27 삼성전기주식회사 기판 제조 방법 및 빌드-업 기판 적층체
KR102065648B1 (ko) * 2013-08-14 2020-01-13 삼성전자주식회사 반도체 패키지
US9397051B2 (en) 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
CN103779245B (zh) * 2014-01-28 2016-09-28 苏州晶方半导体科技股份有限公司 芯片封装方法及封装结构
US9905515B2 (en) * 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure
US9847287B2 (en) * 2015-06-17 2017-12-19 Semiconductor Components Industries, Llc Passive tunable integrated circuit (PTIC) and related methods
US20170062240A1 (en) * 2015-08-25 2017-03-02 Inotera Memories, Inc. Method for manufacturing a wafer level package
CN107039235A (zh) * 2016-02-03 2017-08-11 奕力科技股份有限公司 具低翘曲度的驱动晶片及其制造方法
KR102484394B1 (ko) 2017-12-06 2023-01-03 삼성전자주식회사 반도체 장치
CN113518503B (zh) * 2021-03-31 2022-08-09 深圳市景旺电子股份有限公司 多层印刷线路板及其制作方法
US20230187850A1 (en) * 2021-12-13 2023-06-15 Intel Corporation Liquid metal connection device and method
CN116913868A (zh) * 2023-09-11 2023-10-20 深圳市威兆半导体股份有限公司 半导体器件及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167755A (ja) * 1997-08-21 1999-03-09 Seiko Epson Corp 半導体の構造

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US4918511A (en) * 1985-02-01 1990-04-17 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
US4654269A (en) * 1985-06-21 1987-03-31 Fairchild Camera & Instrument Corp. Stress relieved intermediate insulating layer for multilayer metalization
JPH01291430A (ja) * 1988-05-18 1989-11-24 Fujitsu Ltd 半導体装置の製造方法
JP2796657B2 (ja) * 1992-06-09 1998-09-10 三菱マテリアル株式会社 半導体ウェーハの製造方法
JPH06314664A (ja) * 1993-04-28 1994-11-08 Mitsubishi Electric Corp 半導体装置のメッキ方法
JP3229491B2 (ja) * 1993-10-05 2001-11-19 株式会社小糸製作所 自動車用ヘッドランプにおけるエイミング用水準器
US5438022A (en) * 1993-12-14 1995-08-01 At&T Global Information Solutions Company Method for using low dielectric constant material in integrated circuit fabrication
US5413962A (en) * 1994-07-15 1995-05-09 United Microelectronics Corporation Multi-level conductor process in VLSI fabrication utilizing an air bridge
KR0182073B1 (ko) * 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
JPH11307525A (ja) 1998-04-22 1999-11-05 Toshiba Corp 半導体装置及びその製造方法
US6016000A (en) * 1998-04-22 2000-01-18 Cvc, Inc. Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics
US6211057B1 (en) * 1999-09-03 2001-04-03 Taiwan Semiconductor Manufacturing Company Method for manufacturing arch air gap in multilevel interconnection
JP2001093863A (ja) 1999-09-24 2001-04-06 Toshiba Corp ウェーハ裏面スパッタリング方法及び半導体製造装置
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
US6570245B1 (en) * 2000-03-09 2003-05-27 Intel Corporation Stress shield for microelectronic dice
KR20020021123A (ko) * 2000-04-12 2002-03-18 롤페스 요하네스 게라투스 알베르투스 반도체 디바이스 및 이의 제조 방법
KR20010105641A (ko) 2000-05-17 2001-11-29 윤종용 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
KR100410990B1 (ko) * 2001-02-20 2003-12-18 삼성전자주식회사 다층배선을 갖는 반도체 장치 및 그의 제조방법
US6455924B1 (en) * 2001-03-22 2002-09-24 International Business Machines Corporation Stress-relieving heatsink structure and method of attachment to an electronic package
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TW504824B (en) * 2001-11-21 2002-10-01 Siliconware Precision Industries Co Ltd Semiconductor package having chip cracking prevention member
JP3882648B2 (ja) 2002-03-14 2007-02-21 富士電機デバイステクノロジー株式会社 半導体装置およびその製造方法
FR2857502B1 (fr) * 2003-07-10 2006-02-24 Soitec Silicon On Insulator Substrats pour systemes contraints
TWI256095B (en) * 2004-03-11 2006-06-01 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer and process for fabricating the same
US9929080B2 (en) * 2004-11-15 2018-03-27 Intel Corporation Forming a stress compensation layer and structures formed thereby

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167755A (ja) * 1997-08-21 1999-03-09 Seiko Epson Corp 半導体の構造

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012501077A (ja) * 2008-08-29 2012-01-12 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド チップ・パッケージ相互作用安定性を高めるための応力緩和ギャップを含む半導体デバイス。
US8704226B2 (en) 2011-04-13 2014-04-22 Panasonic Corporation Three-dimensional integrated circuit having redundant relief structure for chip bonding section

Also Published As

Publication number Publication date
US20100285654A1 (en) 2010-11-11
US7781851B2 (en) 2010-08-24
US20060163689A1 (en) 2006-07-27
KR100652395B1 (ko) 2006-12-01
KR20060082496A (ko) 2006-07-19

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