JP2006024641A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】 半導体基板の上に形成された多層配線構造を備える半導体装置において、この多層配線構造は、比誘電率が3.1以下で硬度が2.7GPa以上である有機シロキサン系絶縁膜を少なくとも一部に備えた層間絶縁膜を有する。また、この有機シロキサン系絶縁膜は、(炭素原子数/珪素原子数)の比が0.5以上1.0以下である。さらに、この多層配線構造は、有機シロキサン系絶縁膜から炭素が抜けて(炭素原子数/珪素原子数)の比が0.1以下になった絶縁層を有機シロキサン系絶縁膜の上面に有することができる。
【選択図】 図1
Description
2 第1の絶縁膜
3 第2の絶縁膜
4 第3の絶縁膜
5 レジスト膜
6,7 開口部
8 バリアメタル膜
9 銅層
10 第1の配線
11 第2の配線
12 ビアホール
13 配線溝
Claims (16)
- 半導体基板の上に形成された多層配線構造を備える半導体装置において、
前記多層配線構造は、比誘電率が3.1以下で硬度が2.7GPa以上である有機シロキサン系絶縁膜を少なくとも一部に備える層間絶縁膜を有しており、該有機シロキサン系絶縁膜は、(炭素原子数/珪素原子数)の比が0.5以上1.0以下であることを特徴とする半導体装置。 - 前記有機シロキサン系絶縁膜の硬度は3.0GPa以上である請求項1に記載の半導体装置。
- 前記有機シロキサン系絶縁膜は、Si−CH3結合、Si−O−Si結合およびSi−C−Si結合を有する請求項1または2に記載の半導体装置。
- 前記多層配線構造は、前記有機シロキサン系絶縁膜から炭素が抜けて(炭素原子数/珪素原子数)の比が0.1以下になった絶縁層を前記有機シロキサン系絶縁膜の上面に有する請求項1〜3に記載の半導体装置。
- 前記絶縁層の膜厚は5nm以上15nm以下である請求項4に記載の半導体装置。
- 前記絶縁層の最大膜厚と最小膜厚との差は、前記絶縁層の平均膜厚の20%以内である請求項5に記載の半導体装置。
- 前記絶縁層の上層に前記絶縁層に接してバリア絶縁膜が形成されている請求項4〜6に記載の半導体装置。
- 前記有機シロキサン系絶縁膜の下層に前記有機シロキサン系絶縁膜に接して前記有機シロキサン系絶縁膜より比誘電率の低い低誘電率絶縁膜が形成されている請求項1〜7に記載の半導体装置。
- 前記低誘電率絶縁膜は、(炭素原子数/珪素原子数)の比が0.5以上1.0以下である有機シロキサン系絶縁膜であって、比誘電率が2.8以下で硬度が1.8GPa以下である請求項8に記載の半導体装置。
- 前記多層配線構造は、前記有機シロキサン系絶縁膜および前記低誘電率絶縁膜の一部に設けられた配線溝と、該配線溝に対応して該低誘電率絶縁膜の他の一部に設けられたビアホールとに導電層が充填された構造を有する請求項8または9に記載の半導体装置。
- 前記多層配線構造は、前記有機シロキサン系絶縁膜および前記低誘電率絶縁膜に設けられた配線溝と、該配線溝に対応して前記有機シロキサン系絶縁膜に設けられたビアホールとに導電層が充填された構造を有する請求項8または9に記載の半導体装置。
- 多層配線構造を有する半導体装置の製造方法において、
半導体基板上に形成された下層配線の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜の上に第3の絶縁膜を形成する工程と、
前記第3の絶縁膜、前記第2の絶縁膜および前記第1の絶縁膜をドライエッチングして、前記下層配線に至る開口部を形成する工程と、
前記開口部の内面および前記第3の絶縁膜の上にバリアメタル膜を形成する工程と、
前記開口部を埋め込むようにして、前記バリアメタル膜の上に導電層を形成する工程と、
前記開口部の内部を除いて、前記導電層、前記バリアメタル膜および前記第3の絶縁膜並びに前記第2の絶縁膜の一部を化学的機械研磨法により除去し、前記下層配線に電気的に接続する上層の配線を形成する工程と、
露出した前記第2の絶縁膜および前記導電層の表面を還元性プラズマ処理する工程とを有し、
前記第2の絶縁膜を形成する工程は、下記式で表されるアルキルアルコキシシランと非酸化性ガスとを原料ガスに用い、500Pa以下の圧力でプラズマCVD法により成膜する工程であることを特徴とする半導体装置の製造方法
RwSixOy(OR´)z
(但し、RおよびR´はCH3であり、w,x,zは正の整数、yは0または正の整数であって、(w/x)=2である。)。 - 多層配線構造を有する半導体装置の製造方法において、
半導体基板上に形成された下層配線の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜の上に第3の絶縁膜を形成する工程と、
前記第3の絶縁膜、前記第2の絶縁膜および前記第1の絶縁膜をドライエッチングして、前記下層配線に至る開口部を形成する工程と、
前記開口部の内面および前記第3の絶縁膜の上にバリアメタル膜を形成する工程と、
前記開口部を埋め込むようにして、前記バリアメタル膜の上に導電層を形成する工程と、
前記開口部の内部を除いて、前記導電層、前記バリアメタル膜および前記第3の絶縁膜並びに前記第2の絶縁膜の一部を化学的機械研磨法により除去し、前記下層配線に電気的に接続する上層の配線を形成する工程と、
露出した前記第2の絶縁膜および前記導電層の表面を還元性プラズマ処理する工程とを有し、
前記第2の絶縁膜を形成する工程は、下記式で表されるアルキルアルコキシシランと非酸化性ガスとを原料ガスとして、プラズマCVD法により650Pa以上の圧力で所定の膜厚に達するまで成膜した後、圧力を500Pa以下に変えてさらに成膜する工程であることを特徴とする半導体装置の製造方法
RwSixOy(OR´)z
(但し、RおよびR´はCH3であり、w,x,zは正の整数、yは0または正の整数であって、(w/x)=2である。)。 - 多層配線構造を有する半導体装置の製造方法において、
半導体基板上に形成された下層配線の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜の上に第3の絶縁膜を形成する工程と、
前記第3の絶縁膜の上に第4の絶縁膜を形成する工程と、
前記第4の絶縁膜、前記第3の絶縁膜、前記第2の絶縁膜および前記第1の絶縁膜をドライエッチングして、前記下層配線に至る開口部を形成する工程と、
前記開口部の内面および前記第4の絶縁膜の上にバリアメタル膜を形成する工程と、
前記開口部を埋め込むようにして、前記バリアメタル膜の上に導電層を形成する工程と、
前記開口部の内部を除いて、前記導電層、前記バリアメタル膜および前記第4の絶縁膜並びに前記第3の絶縁膜の一部を化学的機械研磨法により除去し、前記下層配線に電気的に接続する上層の配線を形成する工程と、
露出した前記第3の絶縁膜および前記導電層の表面を還元性プラズマ処理する工程とを有し、
前記第2の絶縁膜を形成する工程は、前記第3の絶縁膜より比誘電率の低い絶縁膜を形成する工程であり、
前記第3の絶縁膜を形成する工程は、下記式で表されるアルキルアルコキシシランと非酸化性ガスとを原料ガスに用い、500Pa以下の圧力でプラズマCVD法により成膜する工程であることを特徴とする半導体装置の製造方法
RwSixOy(OR´)z
(但し、RおよびR´はCH3であり、w,x,zは正の整数、yは0または正の整数であって、(w/x)=2である。)。 - 前記非酸化性ガスは、ヘリウムガス、アルゴンガスおよび窒素ガスよりなる群から選ばれる少なくとも1種のガスである請求項12〜14に記載の半導体装置の製造方法。
- 前記還元性プラズマ処理は、アンモニアおよび水素の少なくとも一方を含むプラズマに晒す工程である請求項12〜15に記載の半導体装置の製造方法。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006126536A1 (ja) * | 2005-05-25 | 2006-11-30 | Nec Corporation | 半導体装置及びその製造方法 |
JP2007103850A (ja) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | 半導体装置の製造方法 |
KR100829385B1 (ko) * | 2006-11-27 | 2008-05-13 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
US8043957B2 (en) | 2006-05-17 | 2011-10-25 | Nec Corporation | Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor |
JP2014003148A (ja) * | 2012-06-18 | 2014-01-09 | Central Japan Railway Co | 炭素含有酸化ケイ素膜の製造方法及び炭素含有酸化ケイ素膜 |
WO2020138092A1 (ja) * | 2018-12-28 | 2020-07-02 | 日産化学株式会社 | 水素ガスを用いた前処理によるレジスト下層膜のエッチング耐性を向上する方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8368220B2 (en) * | 2005-10-18 | 2013-02-05 | Taiwan Semiconductor Manufacturing Co. Ltd. | Anchored damascene structures |
JP2011249678A (ja) * | 2010-05-28 | 2011-12-08 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US10755995B2 (en) * | 2018-06-28 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Warpage control of semiconductor die |
US11410879B2 (en) * | 2020-04-07 | 2022-08-09 | International Business Machines Corporation | Subtractive back-end-of-line vias |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11288931A (ja) * | 1998-02-05 | 1999-10-19 | Nippon Asm Kk | 絶縁膜及びその製造方法 |
JP2000294643A (ja) * | 1998-03-26 | 2000-10-20 | Matsushita Electric Ind Co Ltd | 配線構造体の形成方法 |
JP2001053076A (ja) * | 1999-08-10 | 2001-02-23 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2002252228A (ja) * | 2000-12-19 | 2002-09-06 | Canon Sales Co Inc | 半導体装置及びその製造方法 |
JP2002256434A (ja) * | 2001-01-17 | 2002-09-11 | Air Products & Chemicals Inc | 低誘電率層間絶縁膜の形成方法 |
JP2003031580A (ja) * | 2001-07-18 | 2003-01-31 | Toshiba Corp | 半導体装置の製造方法 |
JP2003086679A (ja) * | 2001-06-25 | 2003-03-20 | Nec Corp | 集積回路装置およびその製造方法 |
JP2004023030A (ja) * | 2002-06-20 | 2004-01-22 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6593247B1 (en) * | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US6068884A (en) * | 1998-04-28 | 2000-05-30 | Silcon Valley Group Thermal Systems, Llc | Method of making low κ dielectric inorganic/organic hybrid films |
JP3727818B2 (ja) | 1999-03-19 | 2005-12-21 | 株式会社東芝 | 半導体装置の配線構造及びその形成方法 |
JP3197007B2 (ja) | 1999-06-08 | 2001-08-13 | 日本エー・エス・エム株式会社 | 半導体基板上のシリコン重合体絶縁膜及びその膜を形成する方法 |
JP3615979B2 (ja) | 2000-01-18 | 2005-02-02 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP2001338978A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100926722B1 (ko) | 2001-04-06 | 2009-11-16 | 에이에스엠 저펜 가부시기가이샤 | 반도체 기판상의 실록산 중합체막 및 그 제조방법 |
JP2003142579A (ja) * | 2001-11-07 | 2003-05-16 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP4177993B2 (ja) * | 2002-04-18 | 2008-11-05 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6740602B1 (en) | 2003-03-17 | 2004-05-25 | Asm Japan K.K. | Method of forming low-dielectric constant film on semiconductor substrate by plasma reaction using high-RF power |
-
2004
- 2004-07-06 JP JP2004199709A patent/JP4854938B2/ja active Active
-
2005
- 2005-07-04 TW TW094122545A patent/TWI413212B/zh active
- 2005-07-05 US US11/172,871 patent/US7602063B2/en active Active
- 2005-07-06 CN CNB2005100825221A patent/CN100539116C/zh active Active
- 2005-07-06 KR KR1020050060724A patent/KR101139034B1/ko active IP Right Grant
- 2005-07-06 CN CN2008101454383A patent/CN101330045B/zh active Active
-
2009
- 2009-06-29 US US12/493,347 patent/US7960279B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11288931A (ja) * | 1998-02-05 | 1999-10-19 | Nippon Asm Kk | 絶縁膜及びその製造方法 |
JP2000294643A (ja) * | 1998-03-26 | 2000-10-20 | Matsushita Electric Ind Co Ltd | 配線構造体の形成方法 |
JP2001053076A (ja) * | 1999-08-10 | 2001-02-23 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2002252228A (ja) * | 2000-12-19 | 2002-09-06 | Canon Sales Co Inc | 半導体装置及びその製造方法 |
JP2002256434A (ja) * | 2001-01-17 | 2002-09-11 | Air Products & Chemicals Inc | 低誘電率層間絶縁膜の形成方法 |
JP2003086679A (ja) * | 2001-06-25 | 2003-03-20 | Nec Corp | 集積回路装置およびその製造方法 |
JP2003031580A (ja) * | 2001-07-18 | 2003-01-31 | Toshiba Corp | 半導体装置の製造方法 |
JP2004023030A (ja) * | 2002-06-20 | 2004-01-22 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006126536A1 (ja) * | 2005-05-25 | 2006-11-30 | Nec Corporation | 半導体装置及びその製造方法 |
JPWO2006126536A1 (ja) * | 2005-05-25 | 2008-12-25 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2007103850A (ja) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | 半導体装置の製造方法 |
US8043957B2 (en) | 2006-05-17 | 2011-10-25 | Nec Corporation | Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor |
US8278763B2 (en) | 2006-05-17 | 2012-10-02 | Nec Corporation | Semiconductor device |
KR100829385B1 (ko) * | 2006-11-27 | 2008-05-13 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
JP2014003148A (ja) * | 2012-06-18 | 2014-01-09 | Central Japan Railway Co | 炭素含有酸化ケイ素膜の製造方法及び炭素含有酸化ケイ素膜 |
WO2020138092A1 (ja) * | 2018-12-28 | 2020-07-02 | 日産化学株式会社 | 水素ガスを用いた前処理によるレジスト下層膜のエッチング耐性を向上する方法 |
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