JP2005539403A5 - - Google Patents

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Publication number
JP2005539403A5
JP2005539403A5 JP2004568930A JP2004568930A JP2005539403A5 JP 2005539403 A5 JP2005539403 A5 JP 2005539403A5 JP 2004568930 A JP2004568930 A JP 2004568930A JP 2004568930 A JP2004568930 A JP 2004568930A JP 2005539403 A5 JP2005539403 A5 JP 2005539403A5
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JP
Japan
Prior art keywords
package
packages
substrate
stacked
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004568930A
Other languages
English (en)
Japanese (ja)
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JP2005539403A (ja
JP4800625B2 (ja
Filing date
Publication date
Priority claimed from US10/632,549 external-priority patent/US7064426B2/en
Priority claimed from US10/632,552 external-priority patent/US20040061213A1/en
Priority claimed from US10/632,551 external-priority patent/US6838761B2/en
Priority claimed from US10/632,553 external-priority patent/US7053476B2/en
Priority claimed from US10/632,550 external-priority patent/US6972481B2/en
Priority claimed from US10/632,568 external-priority patent/US7205647B2/en
Application filed filed Critical
Priority claimed from PCT/US2003/028919 external-priority patent/WO2004027823A2/en
Publication of JP2005539403A publication Critical patent/JP2005539403A/ja
Publication of JP2005539403A5 publication Critical patent/JP2005539403A5/ja
Application granted granted Critical
Publication of JP4800625B2 publication Critical patent/JP4800625B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004568930A 2002-09-17 2003-09-15 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法 Expired - Fee Related JP4800625B2 (ja)

Applications Claiming Priority (15)

Application Number Priority Date Filing Date Title
US41159002P 2002-09-17 2002-09-17
US60/411,590 2002-09-17
US10/632,568 US7205647B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US10/632,551 2003-08-02
US10/632,550 US6972481B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US10/632,551 US6838761B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages
US10/632,553 US7053476B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,568 2003-08-02
US10/632,549 2003-08-02
US10/632,550 2003-08-02
US10/632,553 2003-08-02
US10/632,552 2003-08-02
PCT/US2003/028919 WO2004027823A2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011137096A Division JP5602685B2 (ja) 2002-09-17 2011-06-21 マルチパッケージモジュールおよびその形成方法

Publications (3)

Publication Number Publication Date
JP2005539403A JP2005539403A (ja) 2005-12-22
JP2005539403A5 true JP2005539403A5 (zh) 2006-11-02
JP4800625B2 JP4800625B2 (ja) 2011-10-26

Family

ID=32034538

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2004568930A Expired - Fee Related JP4800625B2 (ja) 2002-09-17 2003-09-15 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法
JP2011137096A Expired - Lifetime JP5602685B2 (ja) 2002-09-17 2011-06-21 マルチパッケージモジュールおよびその形成方法
JP2013123601A Expired - Lifetime JP5856103B2 (ja) 2002-09-17 2013-06-12 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2011137096A Expired - Lifetime JP5602685B2 (ja) 2002-09-17 2011-06-21 マルチパッケージモジュールおよびその形成方法
JP2013123601A Expired - Lifetime JP5856103B2 (ja) 2002-09-17 2013-06-12 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール

Country Status (6)

Country Link
EP (1) EP1547141A4 (zh)
JP (3) JP4800625B2 (zh)
KR (1) KR101166575B1 (zh)
AU (1) AU2003272405A1 (zh)
TW (3) TWI378548B (zh)
WO (1) WO2004027823A2 (zh)

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JP3858854B2 (ja) * 2003-06-24 2006-12-20 富士通株式会社 積層型半導体装置
US7429787B2 (en) * 2005-03-31 2008-09-30 Stats Chippac Ltd. Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7394148B2 (en) 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) * 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US8198735B2 (en) 2006-12-31 2012-06-12 Stats Chippac Ltd. Integrated circuit package with molded cavity
US8124451B2 (en) 2007-09-21 2012-02-28 Stats Chippac Ltd. Integrated circuit packaging system with interposer
KR20110124063A (ko) * 2010-05-10 2011-11-16 하나 마이크론(주) 적층형 반도체 패키지
KR101688005B1 (ko) * 2010-05-10 2016-12-20 삼성전자주식회사 이중 랜드를 갖는 반도체패키지 및 관련된 장치
KR20110124065A (ko) 2010-05-10 2011-11-16 하나 마이크론(주) 적층형 반도체 패키지
TWI406377B (zh) * 2010-12-27 2013-08-21 Powertech Technology Inc 方向指示標記立體化之球格陣列封裝構造及其製造方法
US9165906B2 (en) 2012-12-10 2015-10-20 Invensas Corporation High performance package on package
JP6128993B2 (ja) 2013-06-28 2017-05-17 キヤノン株式会社 積層型半導体装置、プリント回路板、電子機器及び積層型半導体装置の製造方法
KR101563910B1 (ko) * 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
US9995641B2 (en) * 2013-10-30 2018-06-12 Honeywell International Inc. Force sensor with gap-controlled over-force protection
JP6357371B2 (ja) * 2014-07-09 2018-07-11 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
US9666730B2 (en) * 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
KR101961377B1 (ko) * 2015-07-31 2019-03-22 송영희 에지에 사이드 패드를 포함하는 ｌｇａ 반도체 패키지
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
WO2018125242A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Microelectronic devices designed with 3d stacked ultra thin package modules for high frequency communications
KR102283390B1 (ko) 2019-10-07 2021-07-29 제엠제코(주) 멀티칩용 반도체 패키지 및 그 제조방법
KR102325217B1 (ko) 2020-05-18 2021-11-11 제엠제코(주) 멀티 다이 스택 반도체 패키지

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