JP2005535118A5 - - Google Patents

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JP2005535118A5
JP2005535118A5 JP2004524962A JP2004524962A JP2005535118A5 JP 2005535118 A5 JP2005535118 A5 JP 2005535118A5 JP 2004524962 A JP2004524962 A JP 2004524962A JP 2004524962 A JP2004524962 A JP 2004524962A JP 2005535118 A5 JP2005535118 A5 JP 2005535118A5
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lines
representation
shield mesh
layer
reference voltage
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JP2004524962A
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JP2005535118A (ja
JP5281731B2 (ja
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Priority claimed from PCT/US2003/023559 external-priority patent/WO2004012107A2/en
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JP2004524962A 2002-07-29 2003-07-24 集積回路デバイスと集積回路デバイスを設計するための方法及び装置 Expired - Lifetime JP5281731B2 (ja)

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US39976002P 2002-07-29 2002-07-29
US60/399,760 2002-07-29
PCT/US2003/023559 WO2004012107A2 (en) 2002-07-29 2003-07-24 Integrated circuit devices and methods and apparatuses for designing integrated circuit devices

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JP2005535118A JP2005535118A (ja) 2005-11-17
JP2005535118A5 true JP2005535118A5 (https=) 2006-08-17
JP5281731B2 JP5281731B2 (ja) 2013-09-04

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JP2004524962A Expired - Lifetime JP5281731B2 (ja) 2002-07-29 2003-07-24 集積回路デバイスと集積回路デバイスを設計するための方法及び装置

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US (3) US7943436B2 (https=)
EP (1) EP1546946A2 (https=)
JP (1) JP5281731B2 (https=)
KR (4) KR101160857B1 (https=)
AU (1) AU2003254227A1 (https=)
WO (1) WO2004012107A2 (https=)

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