KR101160857B1 - 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치 - Google Patents

집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치 Download PDF

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KR101160857B1
KR101160857B1 KR1020117004893A KR20117004893A KR101160857B1 KR 101160857 B1 KR101160857 B1 KR 101160857B1 KR 1020117004893 A KR1020117004893 A KR 1020117004893A KR 20117004893 A KR20117004893 A KR 20117004893A KR 101160857 B1 KR101160857 B1 KR 101160857B1
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lines
mesh
signal
line
shielding
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KR20110039573A (ko
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케니스 에스 맥엘바인
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시놉시스, 인크.
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423Shielding layers

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020117004893A 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치 Expired - Lifetime KR101160857B1 (ko)

Applications Claiming Priority (3)

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US39976002P 2002-07-29 2002-07-29
US60/399,760 2002-07-29
PCT/US2003/023559 WO2004012107A2 (en) 2002-07-29 2003-07-24 Integrated circuit devices and methods and apparatuses for designing integrated circuit devices

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KR1020057001712A Division KR101100049B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및장치

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KR1020117019056A Division KR101278434B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치

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KR20110039573A KR20110039573A (ko) 2011-04-19
KR101160857B1 true KR101160857B1 (ko) 2012-07-02

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KR1020117004893A Expired - Lifetime KR101160857B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치
KR1020117019056A Expired - Lifetime KR101278434B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치
KR1020107019274A Expired - Lifetime KR101100048B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치
KR1020057001712A Expired - Lifetime KR101100049B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및장치

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KR1020117019056A Expired - Lifetime KR101278434B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치
KR1020107019274A Expired - Lifetime KR101100048B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및 장치
KR1020057001712A Expired - Lifetime KR101100049B1 (ko) 2002-07-29 2003-07-24 집적회로 장치 및 집적회로 장치를 설계하기 위한 방법 및장치

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US (3) US7943436B2 (https=)
EP (1) EP1546946A2 (https=)
JP (1) JP5281731B2 (https=)
KR (4) KR101160857B1 (https=)
AU (1) AU2003254227A1 (https=)
WO (1) WO2004012107A2 (https=)

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KR102640248B1 (ko) * 2023-06-16 2024-02-27 주식회사 하이퍼엑셀 생성형 거대 인공지능 모델의 효율적인 하드웨어 매핑을 위한 방법 및 시스템

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KR102640248B1 (ko) * 2023-06-16 2024-02-27 주식회사 하이퍼엑셀 생성형 거대 인공지능 모델의 효율적인 하드웨어 매핑을 위한 방법 및 시스템
US12405814B2 (en) 2023-06-16 2025-09-02 Hyperaccel Co., Ltd. Method and system for efficient hardware mapping of generative giant artificial intelligence model

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US20110214100A1 (en) 2011-09-01
US7943436B2 (en) 2011-05-17
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JP2005535118A (ja) 2005-11-17
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AU2003254227A1 (en) 2004-02-16
US8881086B2 (en) 2014-11-04
JP5281731B2 (ja) 2013-09-04
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KR20110039573A (ko) 2011-04-19
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