JP2005191545A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2005191545A JP2005191545A JP2004334711A JP2004334711A JP2005191545A JP 2005191545 A JP2005191545 A JP 2005191545A JP 2004334711 A JP2004334711 A JP 2004334711A JP 2004334711 A JP2004334711 A JP 2004334711A JP 2005191545 A JP2005191545 A JP 2005191545A
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- Chemical Kinetics & Catalysis (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
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- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】金属元素Mと第1のIV族半導体元素Si1-a Gea(ただし、0≦a≦1)の化合物を有する第1のゲート電極を備えたn型半導体装置と、金属元素Mと第2のIV族半導体元素Si1-c Gec(ただし、0≦c≦1,a≠c)の化合物を有する第2のゲート電極を備えたp型半導体装置が同一基板に形成され、第1及び第2のゲート電極は、
IV族半導体元素の組成比変化(a又はc)と仕事関数の間に安定かつ広範な相関関係を備える。
【選択図】 図1
Description
Jaehoon Lee et al., IEDM Tech. Dig., 2002 p.359-362 J.Kedzierski et al., IEDM Tech. Dig., 2002 p.247-250
第一の実施の形態に係わるCMISFETについて図1を参照して説明する。図1に示すように、p型シリコン基板1上において、n型MISFET2とp型MISFET3は、分離領域4により分離して形成されている。
第二の実施の形態に係わるCMISFETについて、第一の実施の形態と異なる箇所を説明する。第二の実施の形態のCMISFETは、第一の実施形態に係るCMISFETと同じ技術思想に基づくものであるが、ゲート電極にCを添加した点が第1の実施形態と異なる。従って、第二の実施の形態のCMISFETの断面構造は、第一の実施の形態と同様とすることができるので、図1を参照しつつ説明する。
第三の実施の形態に係わるCMISFETについて、第一の実施の形態と異なる箇所を説明する。第三の実施の形態のCMISFETは、第一の実施形態に係るCMISFETのゲート電極の材料M(SiGe)のMに複数の金属元素を用い、かつ、M(SiGe)は同一の結晶構造を備えることを特徴とする。従って、第三の実施の形態のCMISFETの断面構造は、第一の実施の形態と同様とすることができるので、図1を参照しつつ説明する。
第四の実施の形態に係わるCMISFETについて第一の実施の形態と異なる箇所を説明する。第四の実施の形態のCMISFETは、第一の実施形態に係るCMISFETのゲート電極にAs、PまたはBを添加したものである。従って、第四の実施の形態のCMISFETの断面構造は、第一の実施の形態と同様とすることができるので、図1を参照しつつ説明する。
第五の実施の形態に係わるCMISFETについて、図7〜図11を参照して第一の実施の形態と異なる部分を説明する。
2…n型MISFET
3…p型MISFET
4…素子分離
5…p型ウェル(p型不純物領域)
6…n型チャネル領域
7…第1のゲート絶縁膜
8…第1のゲート電極
9…第1のゲート側壁
10…n型ソース・ドレイン領域(n型高濃度不純物領域)
11…第1のコンタクト領域
12…n型ウェル(n型不純物領域)
13…p型チャネル領域
14…第2のゲート絶縁膜
15…第2のゲート電極
15a…M(SiGe)層
15b…高不純物濃度多結晶SiGe層
16…第2のゲート側壁
17…p型ソース・ドレイン領域(p型高濃度不純物領域)
18…第2のコンタクト電極
19…第1のソース・ドレイン電極
20…第2のソース・ドレイン電極
21…シリコン酸化膜
22…p型ウェル上の多結晶SiGe
23…n型ウェル上の多結晶SiGe
24…Ni膜
25…マスク
26…Fin部
27…絶縁層
28…シリコン酸化膜
29…多結晶Si
Claims (11)
- シリコン基板と、前記シリコン基板上に形成されたn型半導体装置とp型半導体装置とを具備し、前記n型半導体装置は、
前記シリコン基板の表面に形成されたn型チャネル領域と、
前記シリコン基板の表面に前記n型チャネル領域を挟んで対向して形成されたn型ソース領域及びn型ドレイン領域と、
前記n型ソース領域及び前記n型ドレイン領域の間の前記n型チャネル領域の前記表面上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された金属元素Mと第1のIV族半導体元素Si1-a Gea(ただし、0≦a≦1)の化合物を有する第1のゲート電極と、
を具備し、前記p型半導体装置は、
前記シリコン基板の前記表面に形成されたp型チャネル領域と、
前記シリコン基板の表面に前記p型チャネル領域を挟んで対向して形成されたp型ソース領域及びp型ドレイン領域と、
前記p型ソース領域及び前記p型ドレイン領域の間の前記p型チャネル領域の前記表面上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された前記金属元素Mと第2のIV族半導体元素Si1-c Gec(ただし、0≦c≦1,a≠c)の化合物を有する第2のゲート電極と、
を具備することを特徴とする半導体装置。 - シリコン基板と、前記シリコン基板上に形成されたn型半導体装置とp型半導体装置とを具備し、前記n型半導体装置は、
前記シリコン基板の表面に形成されたn型チャネル領域と、
前記シリコン基板の表面に前記n型チャネル領域を挟んで対向して形成されたn型ソース領域及びn型ドレイン領域と、
前記n型ソース領域及び前記n型ドレイン領域の間の前記n型チャネル領域の前記表面上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された金属元素Mと第1のIV族半導体元素Si1-a-b Gea Cb(ただし、0≦a≦1,0≦b≦0.02,0≦a+b≦1)の化合物を有する第1のゲート電極と、
を具備し、前記p型半導体装置は、
前記シリコン基板の前記表面に形成されたp型チャネル領域と、
前記シリコン基板の表面に前記p型チャネル領域を挟んで対向して形成されたp型ソース領域及びp型ドレイン領域と、
前記p型ソース領域及び前記p型ドレイン領域の間の前記p型チャネル領域の前記表面上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された前記金属元素Mと第2のIV族半導体元素Si1-c-d GecCd(ただし、0≦c≦1,0≦d≦0.02,0≦c+d≦1,a≠cかつb、dの少なくとも一方が≠0)の化合物を有する第2のゲート電極と、
を具備することを特徴とする半導体装置。 - 前記金属元素Mは、Ni、Pd、Pt、Ta,Er,Ti及びZrから選ばれる1つの金属元素であることを特徴とする請求項1または2のいずれかに記載の半導体装置。
- 前記第1及び第2のゲート電極は、a≦0.3かつc≦0.3を満たすことを特徴とする請求項1乃至3のいずれかに記載の半導体装置。
- 前記金属元素MはNiであり、c>aを満たすことを特徴とする請求項1、2,4のいずれかに記載の半導体装置。
- 前記金属元素Mは、Ni、Pd及びPtから選ばれる2つ以上の金属元素、若しくはTi及びZrを含むことを特徴とする請求項1、2,4のいずれかに記載の半導体装置。
- 前記第1のゲート電極及び前記第2のゲート電極の少なくとも一方は、As,P、Bから選ばれた1つが添加されていることを特徴とする請求項1乃至6のいずれかに記載の半導体装置。
- 前記n型半導体装置及び前記p型半導体装置は、完全に空乏化されるように構成されていることを特徴とする請求項1乃至7のいずれかに記載の半導体装置。
- 前記n型半導体装置及び前記p型半導体装置は、相補型半導体装置を為すことを特徴とする請求項1乃至8のいずれかに記載の半導体装置。
- 前記第1のゲート電極及び前記第2のゲート電極は、共にBが添加されており、前記第1のゲート電極においてa≠0、前記第2のゲート電極においてc=0、b+d>0を満足することを特徴とする請求項1乃至6、8及び9のいずれかに記載の半導体装置。
- 前記第1のゲート電極のGe組成がSiに対して5%以上であることを特徴とする請求項1乃至10のいずれかに記載の半導体装置。
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2004
- 2004-11-18 JP JP2004334711A patent/JP4473710B2/ja not_active Expired - Fee Related
- 2004-11-26 EP EP04257343A patent/EP1538674A3/en not_active Withdrawn
- 2004-11-29 US US10/997,939 patent/US20050127451A1/en not_active Abandoned
- 2004-12-03 CN CNB2004100983502A patent/CN100397657C/zh not_active Expired - Fee Related
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2007
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- 2007-06-11 US US11/761,271 patent/US20070228485A1/en not_active Abandoned
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US7202539B2 (en) | 2004-06-16 | 2007-04-10 | Renesas Technology Corporation | Semiconductor device having misfet gate electrodes with and without GE or impurity and manufacturing method thereof |
WO2007026677A1 (ja) * | 2005-09-01 | 2007-03-08 | Nec Corporation | 半導体装置の製造方法 |
JPWO2007026677A1 (ja) * | 2005-09-01 | 2009-03-05 | 日本電気株式会社 | 半導体装置の製造方法 |
US7723176B2 (en) | 2005-09-01 | 2010-05-25 | Nec Corporation | Method for manufacturing semiconductor device |
JP2011066433A (ja) * | 2005-09-30 | 2011-03-31 | Infineon Technologies Ag | 半導体デバイスおよびその製造方法 |
US8722473B2 (en) | 2005-09-30 | 2014-05-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US9659962B2 (en) | 2005-09-30 | 2017-05-23 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
JP2009540603A (ja) * | 2006-06-15 | 2009-11-19 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 低接触抵抗cmos回路およびその製造方法 |
JP2010073865A (ja) * | 2008-09-18 | 2010-04-02 | Toshiba Corp | 半導体装置、及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070228486A1 (en) | 2007-10-04 |
US7514753B2 (en) | 2009-04-07 |
US20070228485A1 (en) | 2007-10-04 |
CN1624932A (zh) | 2005-06-08 |
EP1538674A2 (en) | 2005-06-08 |
EP1538674A3 (en) | 2007-11-21 |
CN100397657C (zh) | 2008-06-25 |
US20050127451A1 (en) | 2005-06-16 |
JP4473710B2 (ja) | 2010-06-02 |
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