JP2005005721A - 半導体パッケージ用配線基板、その製造方法及びそれを利用した半導体パッケージ - Google Patents
半導体パッケージ用配線基板、その製造方法及びそれを利用した半導体パッケージ Download PDFInfo
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- JP2005005721A JP2005005721A JP2004174651A JP2004174651A JP2005005721A JP 2005005721 A JP2005005721 A JP 2005005721A JP 2004174651 A JP2004174651 A JP 2004174651A JP 2004174651 A JP2004174651 A JP 2004174651A JP 2005005721 A JP2005005721 A JP 2005005721A
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Abstract
【解決手段】絶縁基板100に陰刻形態にインプリントされた回路パターン形成領域を先に作った後、前記回路パターン形成領域を埋め込む金属材質の回路パターン110を形成する半導体パッケージ用の配線基板の製造方法。したがって、LCD駆動用として使われる半導体パッケージの配線基板を製造する過程で写真工程を省略してコスト節減及び生産性の向上効果が得られ、金属材質の回路パターン110を作る過程で発生する欠陥を防止して製品の信頼性を改善し、微細線幅を有する回路パターンをさらに効率的に作られる。
【選択図】図21
Description
図22は、本発明の第1変形例を説明するための断面図であり、図23は、本発明の第1変形例を説明するためのフローチャートである。本変形例は絶縁基板100を準備する段階を他の方法に若干変形したものである。
図24は、本発明の第2変形例を説明するための断面図である。
図24を参照すれば、前述した実施例では回路パターン材質を形成する方法がスパッタリング法、化学気相蒸着法及び電解メッキ法などを混合して使用したが、これは導電性金属を構成成分とするペースト116を前記回路パターン形成領域114にスクイズプレート120を使用して押し込める方法でも形成可能である。すなわち、前記陰刻形状よりなった回路パターン形成領域114にのみ金属材質の回路パターンを埋め込む方法であれば、何れも使用可能である。
図25は、本発明の第3変形例を説明するためのフローチャートである。
図25を参照すれば、前述した実施例ではソルダレジストを先に塗布し、その後にメッキ部を形成する後メッキ方式を採択したが、本変形例はメッキ部を先に形成し、ソルダレジストを形成する先メッキ方式である。詳細に説明すれば、絶縁基板準備段階及び回路パターン形成段階(S100〜S160)は前述した実施例と同じ方式で進める。その後、前記回路パターンにメッキ部を先に形成した(S180)後、外部回路と連結していない回路パターンに対してソルダレジストを塗布する(S170)。
104 シード層
106 銅プレート層
108 ソルダレジスト
110 金属材質の回路パターン
Claims (42)
- 回路パターン形成領域が陰刻形状を有する絶縁基板と、
前記絶縁基板内の陰刻形状の回路パターン形成領域を埋め込む金属材質の回路パターンと、
前記回路パターン上部を覆うメッキ部と、
前記回路パターンの上部を覆うソルダレジストと、
を具備することを特徴とする半導体パッケージ製造用の配線基板。 - 前記絶縁基板の陰刻形状はインプリント技法を利用して形成されたことを特徴とする請求項1に記載の半導体パッケージ製造用の配線基板。
- 前記絶縁基板は可撓性を有することを特徴とする請求項1に記載の半導体パッケージ製造用の配線基板。
- 前記絶縁基板は熱硬化性樹脂あるいは光硬化性樹脂を材質とすることを特徴とする請求項1に記載の半導体パッケージ製造用の配線基板。
- 前記絶縁基板はポリイミドあるいはポリベンズオキサゾールを基本材質とすることを特徴とする請求項4に記載の半導体パッケージ製造用の配線基板。
- 前記ソルダレジストは前記メッキ部が形成された領域を除外した回路パターン上にのみ形成されたことを特徴とする請求項1に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの幅は7〜15μmの範囲であることを特徴とする請求項6に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの高さは前記絶縁基板全体厚さの16〜32%の範囲であることを特徴とする請求項6に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの高さは5〜15μmの範囲であることを特徴とする請求項6に記載の半導体パッケージ製造用の配線基板。
- 前記ソルダレジストは前記メッキ部が形成された領域上を含んで形成されたことを特徴とする請求項1に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの幅は7〜15μmの範囲であることを特徴とする請求項10に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの高さは前記絶縁基板全体厚さの16〜32%の範囲であることを特徴とする請求項10に記載の半導体パッケージ製造用の配線基板。
- 前記回路パターンの高さは5〜15μmの範囲であることを特徴とする請求項10に記載の半導体パッケージ製造用の配線基板。
- 回路パターン形成領域が陰刻形状を有する半導体パッケージ製造用の絶縁基板を準備する段階と、
前記絶縁基板の陰刻形状の回路パターン形成領域に金属材質の回路パターンを形成する段階と、
前記回路パターン上にメッキ部及びソルダレジストを形成する段階と、
を具備することを特徴とする半導体パッケージ用配線基板の製造方法。 - 前記絶縁基板は可撓性を有することを特徴とする請求項14に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記絶縁基板を準備する段階は、
前記絶縁基板に回路パターン形成領域を作るための金型を準備する工程と、
絶縁基板鋳造用の高分子溶液を鋳造容器に塗布する工程と、
前記絶縁基板鋳造用の高分子溶液をプレキュアリングして絶縁基板鋳造用の高分子フィルムを形成する工程と、
前記絶縁基板鋳造用の高分子フィルムに回路パターン形成領域を作るための金型を利用して陰刻形状にインプリントされた回路パターン形成領域を作る工程と、
前記回路パターン形成領域が作られた絶縁基板鋳造用の高分子フィルムにキュアリングを進めて高分子フィルムの硬化度を高める工程と、
前記絶縁基板鋳造用の高分子フィルムにスプロケットホールをあける工程と、
前記スプロケットホールがあけられた絶縁基板鋳造用の高分子フィルムをリールに巻く工程と、
を具備することを特徴とする請求項14に記載の半導体パッケージ用配線基板の製造方法。 - 前記絶縁基板鋳造用の高分子溶液は熱硬化性物質あるいは光硬化性物質を材質とすることを特徴とする請求項16に記載の半導体パッケージ用配線基板の製造方法。
- 前記絶縁基板鋳造用の高分子溶液はポリイミド及びポリベンズオキサゾールのうちから選択された何れか1つを基本材質とすることを特徴とする請求項18に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記陰刻形状にインプリントされた回路パターン形成領域を作る工程は、
金型を押しつつ200〜360℃範囲の高熱を加えて前記高分子フィルムの硬化速度を速めることを特徴とする請求項16に記載の半導体パッケージ用配線基板の製造方法。 - 前記絶縁基板鋳造用の高分子溶液は感光剤が含まれたポリイミド及びポリベンズオキサゾールのうちから選択された何れか1つであることを特徴とする請求項18に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記陰刻形状にインプリントされた回路パターン形成領域を作る工程は、
金型を押しつつ光を照射することによって前記高分子フィルムの硬化速度を速めることを特徴とする請求項20に記載の半導体パッケージ用配線基板の製造方法。 - 前記絶縁基板を準備する段階は、
前記絶縁基板に回路パターン形成領域を作るための金型を準備する工程と、
前記絶縁基板鋳造用の高分子溶液を鋳造容器に1次に塗布する工程と、
前記絶縁基板鋳造用の高分子溶液を乾燥させた後、プレキュアリングを進める工程と、
前記絶縁基板鋳造用の高分子溶液を前記鋳造容器に2次に塗布して乾燥させる工程と、
前記金型を利用して前記2次に塗布された絶縁基板鋳造用の高分子溶液に陰刻形状にインプリントされた回路パターン形成領域を作る工程と、
前記回路パターン形成領域が作られた鋳造容器にキュアリングを進めて絶縁基板鋳造用の高分子フィルムを作る工程と、
前記絶縁基板鋳造用の高分子フィルムに歯車ホールをあける工程と、
前記歯車ホールがあけられた絶縁基板鋳造用の高分子フィルムをリールに巻く工程と、
を具備することを特徴とする請求項14に記載の半導体パッケージ製造用の配線基板の製造方法。 - 前記絶縁基板鋳造用の高分子溶液は熱硬化性あるいは光硬化性物質を材質とすることを特徴とする請求項22に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記絶縁基板鋳造用の高分子溶液はポリイミド及びポリベンズオキサゾールのうちから選択された何れか1つを基本材質とすることを特徴とする請求項23に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記陰刻形状にインプリントされた回路パターン形成領域を作る工程は、
金型を押しつつ200〜360℃範囲の高熱を加えて前記高分子フィルムの硬化速度を速めることを特徴とする請求項23に記載の半導体パッケージ用配線基板の製造方法。 - 前記絶縁基板鋳造用の高分子溶液は感光剤が含まれたポリイミド及びポリベンズオキサゾールのうちから選択された何れか1つを基本材質とすることを特徴とする請求項22に記載の半導体パッケージ製造用の配線基板の製造方法。
- 前記陰刻形状にインプリントされた回路パターン形成領域を作る工程は、
金型を押しつつ光を照射することによって前記高分子フィルムの硬化速度を速めることを特徴とする請求項26に記載の半導体パッケージ用配線基板の製造方法。 - 回路パターン形成領域が陰刻形状を有する絶縁基板と、
前記絶縁基板にある陰刻形状の回路パターン形成領域を満たす金属材質の回路パターンと、
前記回路パターン上部に形成されたメッキ部と、
前記回路パターン上部を覆うソルダレジストと、
前記絶縁基板上に搭載されて前記メッキ部と連結される電極が形成された半導体チップと、
を具備することを特徴とする半導体パッケージ。 - 前記半導体チップの電極はバンプ、ソルダボール、ボンディングワイヤー及びリ―ドからなる導電性連結手段群のうちから選択された何れか1つであることを特徴とする請求項28に記載の半導体パッケージ。
- 前記半導体パッケージは前記半導体チップと前記絶縁基板との間の空間を充填する封止樹脂をさらに具備することを特徴とする請求項28に記載の半導体パッケージ。
- 前記絶縁基板の陰刻形状はインプリント技法を利用して形成されたことを特徴とする請求項28に記載の半導体パッケージ。
- 前記絶縁基板は可撓性を有することを特徴とする請求項28に記載の半導体パッケージ。
- 前記絶縁基板は熱硬化性樹脂あるいは光硬化性樹脂のうちから選択された何れか1つであることを特徴とする請求項28に記載の半導体パッケージ。
- 前記絶縁基板は感光剤が含まれたポリイミド及びポリベンズオキサゾールのうちから選択された1つを基本材質とすることを特徴とする請求項28に記載の半導体パッケージ。
- 前記ソルダレジストは前記メッキ部が形成された領域を除外した回路パターン上に形成されたことを特徴とする請求項28に記載の半導体パッケージ。
- 前記回路パターンの幅は7〜15μmの範囲であることを特徴とする請求項35に記載の半導体パッケージ。
- 前記回路パターンの高さは前記絶縁基板全体厚さの16〜32%の範囲であることを特徴とする請求項35に記載の半導体パッケージ。
- 前記回路パターンの高さは5〜15μmの範囲であることを特徴とする請求項35に記載の半導体パッケージ。
- 前記ソルダレジストは前記メッキ部が形成された領域上を含んで形成されたことを特徴とする請求項28に記載の半導体パッケージ。
- 前記回路パターンの幅は7〜15μmの範囲であることを特徴とする請求項39に記載の半導体パッケージ。
- 前記回路パターンの高さは前記絶縁基板全体厚さの16〜32%の範囲であることを特徴とする請求項39に記載の半導体パッケージ。
- 前記回路パターンの高さは5〜15μmの範囲であることを特徴とする請求項39に記載の半導体パッケージ。
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US10312179B2 (en) | 2014-04-30 | 2019-06-04 | Conti Temic Microelectronic Gmbh | Circuit arrangement, and current transformer |
US9496232B2 (en) | 2014-08-28 | 2016-11-15 | Renesas Electronics Corporation | Semiconductor device and its manufacturing method |
US9929120B2 (en) | 2014-08-28 | 2018-03-27 | Renesas Electronics Corporation | Semiconductor device and its manufacturing method |
Also Published As
Publication number | Publication date |
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US20120102734A1 (en) | 2012-05-03 |
US20040251537A1 (en) | 2004-12-16 |
US8110918B2 (en) | 2012-02-07 |
KR100604819B1 (ko) | 2006-07-28 |
US8796158B2 (en) | 2014-08-05 |
EP1487018A2 (en) | 2004-12-15 |
KR20040107058A (ko) | 2004-12-20 |
EP1487018A3 (en) | 2010-09-01 |
CN1591840A (zh) | 2005-03-09 |
CN100590855C (zh) | 2010-02-17 |
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