JP2004186226A - Ｓｏｉウエーハの製造方法 - Google Patents

Ｓｏｉウエーハの製造方法 Download PDF

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Publication number
JP2004186226A
JP2004186226A JP2002348610A JP2002348610A JP2004186226A JP 2004186226 A JP2004186226 A JP 2004186226A JP 2002348610 A JP2002348610 A JP 2002348610A JP 2002348610 A JP2002348610 A JP 2002348610A JP 2004186226 A JP2004186226 A JP 2004186226A
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JP
Japan
Prior art keywords
wafer
soi
shape
producing
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002348610A
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English (en)
Japanese (ja)
Inventor
Makoto Kobayashi
誠 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2002348610A priority Critical patent/JP2004186226A/ja
Priority to US10/536,428 priority patent/US7435662B2/en
Priority to EP20030774018 priority patent/EP1566830B1/en
Priority to PCT/JP2003/014442 priority patent/WO2004051715A1/ja
Priority to TW092132781A priority patent/TW200423216A/zh
Publication of JP2004186226A publication Critical patent/JP2004186226A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2002348610A 2002-11-29 2002-11-29 Ｓｏｉウエーハの製造方法 Pending JP2004186226A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002348610A JP2004186226A (ja) 2002-11-29 2002-11-29 Ｓｏｉウエーハの製造方法
US10/536,428 US7435662B2 (en) 2002-11-29 2003-11-13 Method for manufacturing SOI wafer
EP20030774018 EP1566830B1 (en) 2002-11-29 2003-11-13 Method for manufacturing soi wafer
PCT/JP2003/014442 WO2004051715A1 (ja) 2002-11-29 2003-11-13 Ｓｏｉウェーハの製造方法
TW092132781A TW200423216A (en) 2002-11-29 2003-11-21 Method for manufacturing SOI wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002348610A JP2004186226A (ja) 2002-11-29 2002-11-29 Ｓｏｉウエーハの製造方法

Publications (1)

Publication Number Publication Date
JP2004186226A true JP2004186226A (ja) 2004-07-02

Family

ID=32462928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002348610A Pending JP2004186226A (ja) 2002-11-29 2002-11-29 Ｓｏｉウエーハの製造方法

Country Status (5)

Country Link
US (1) US7435662B2 (https=)
EP (1) EP1566830B1 (https=)
JP (1) JP2004186226A (https=)
TW (1) TW200423216A (https=)
WO (1) WO2004051715A1 (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007157952A (ja) * 2005-12-05 2007-06-21 Sumco Corp 貼合せ基板の製造方法及びこの方法により製造された貼合せ基板
JP2010245411A (ja) * 2009-04-09 2010-10-28 Hitachi Ltd 半導体装置
KR20120121905A (ko) * 2010-02-25 2012-11-06 엠이엠씨 일렉트로닉 머티리얼즈, 인크. Ｓｏｉ 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 ｓｏｉ 구조체
JP2012238873A (ja) * 2005-11-28 2012-12-06 Soytec 分子接合による結合のためのプロセスおよび装置
KR20190050995A (ko) * 2016-09-27 2019-05-14 신에쯔 한도타이 가부시키가이샤 접합soi웨이퍼의 제조방법

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6926829B2 (en) 2000-03-06 2005-08-09 Kvaerner Process Systems A.S. Apparatus and method for separating fluids through a membrane
US7501303B2 (en) * 2001-11-05 2009-03-10 The Trustees Of Boston University Reflective layer buried in silicon and method of fabrication
WO2004073057A1 (ja) * 2003-02-14 2004-08-26 Sumitomo Mitsubishi Silicon Corporation シリコンウェーハの製造方法
EP1840955B1 (en) * 2006-03-31 2008-01-09 S.O.I.TEC. Silicon on Insulator Technologies S.A. Method for fabricating a compound material and method for choosing a wafer
JP2008028070A (ja) * 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
KR101460993B1 (ko) * 2007-01-31 2014-11-13 신에쯔 한도타이 가부시키가이샤 실리콘 웨이퍼의 면취 장치 및 실리콘 웨이퍼의 제조방법 그리고 에치드 실리콘 웨이퍼
FR2938202B1 (fr) * 2008-11-07 2010-12-31 Soitec Silicon On Insulator Traitement de surface pour adhesion moleculaire
US8377825B2 (en) * 2009-10-30 2013-02-19 Corning Incorporated Semiconductor wafer re-use using chemical mechanical polishing
US8562849B2 (en) * 2009-11-30 2013-10-22 Corning Incorporated Methods and apparatus for edge chamfering of semiconductor wafers using chemical mechanical polishing
US9156705B2 (en) 2010-12-23 2015-10-13 Sunedison, Inc. Production of polycrystalline silicon by the thermal decomposition of dichlorosilane in a fluidized bed reactor
FR2990054B1 (fr) 2012-04-27 2014-05-02 Commissariat Energie Atomique Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif.

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590116A (ja) * 1991-05-22 1993-04-09 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH08264740A (ja) * 1995-03-27 1996-10-11 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造された結合ウェーハ
JPH09232197A (ja) * 1996-02-27 1997-09-05 Sumitomo Sitix Corp 貼り合わせ半導体ウエーハの製造方法
JP2001326197A (ja) * 2000-03-10 2001-11-22 Mitsubishi Materials Silicon Corp 半導体ウェーハの研磨方法およびその装置
JP2001328062A (ja) * 2000-05-22 2001-11-27 Mitsubishi Materials Silicon Corp 半導体ウェーハの研磨方法およびその装置
JP2001345435A (ja) * 2000-03-29 2001-12-14 Shin Etsu Handotai Co Ltd シリコンウェーハ及び貼り合わせウェーハの製造方法、並びにその貼り合わせウェーハ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
EP1189266B1 (en) 2000-03-29 2017-04-05 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and soi wafer, and soi wafer
JP2001338899A (ja) * 2000-05-26 2001-12-07 Shin Etsu Handotai Co Ltd 半導体ウエーハの製造方法及び半導体ウエーハ

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590116A (ja) * 1991-05-22 1993-04-09 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH08264740A (ja) * 1995-03-27 1996-10-11 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造された結合ウェーハ
JPH09232197A (ja) * 1996-02-27 1997-09-05 Sumitomo Sitix Corp 貼り合わせ半導体ウエーハの製造方法
JP2001326197A (ja) * 2000-03-10 2001-11-22 Mitsubishi Materials Silicon Corp 半導体ウェーハの研磨方法およびその装置
JP2001345435A (ja) * 2000-03-29 2001-12-14 Shin Etsu Handotai Co Ltd シリコンウェーハ及び貼り合わせウェーハの製造方法、並びにその貼り合わせウェーハ
JP2001328062A (ja) * 2000-05-22 2001-11-27 Mitsubishi Materials Silicon Corp 半導体ウェーハの研磨方法およびその装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012238873A (ja) * 2005-11-28 2012-12-06 Soytec 分子接合による結合のためのプロセスおよび装置
JP2007157952A (ja) * 2005-12-05 2007-06-21 Sumco Corp 貼合せ基板の製造方法及びこの方法により製造された貼合せ基板
JP2010245411A (ja) * 2009-04-09 2010-10-28 Hitachi Ltd 半導体装置
KR20120121905A (ko) * 2010-02-25 2012-11-06 엠이엠씨 일렉트로닉 머티리얼즈, 인크. Ｓｏｉ 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 ｓｏｉ 구조체
JP2013520838A (ja) * 2010-02-25 2013-06-06 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Ｓｏｉ構造における非結合領域の幅の減少方法ならびにその方法によって製造したウエハおよびｓｏｉ構造
KR20180052773A (ko) * 2010-02-25 2018-05-18 썬에디슨, 인크. Ｓｏｉ 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 ｓｏｉ 구조체
KR101882026B1 (ko) * 2010-02-25 2018-07-25 썬에디슨, 인크. Ｓｏｉ 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 ｓｏｉ 구조체
KR101972286B1 (ko) * 2010-02-25 2019-04-24 썬에디슨, 인크. Ｓｏｉ 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 ｓｏｉ 구조체
KR20190050995A (ko) * 2016-09-27 2019-05-14 신에쯔 한도타이 가부시키가이샤 접합soi웨이퍼의 제조방법
KR102408679B1 (ko) 2016-09-27 2022-06-14 신에쯔 한도타이 가부시키가이샤 접합soi웨이퍼의 제조방법

Also Published As

Publication number Publication date
TW200423216A (en) 2004-11-01
WO2004051715A1 (ja) 2004-06-17
EP1566830A1 (en) 2005-08-24
EP1566830A4 (en) 2010-03-03
US20060024915A1 (en) 2006-02-02
US7435662B2 (en) 2008-10-14
TWI313483B (https=) 2009-08-11
EP1566830B1 (en) 2015-05-06

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