JP2003188252A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JP2003188252A
JP2003188252A JP2001380656A JP2001380656A JP2003188252A JP 2003188252 A JP2003188252 A JP 2003188252A JP 2001380656 A JP2001380656 A JP 2001380656A JP 2001380656 A JP2001380656 A JP 2001380656A JP 2003188252 A JP2003188252 A JP 2003188252A
Authority
JP
Japan
Prior art keywords
insulating film
contact
wiring
wiring layer
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001380656A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003188252A5 (enExample
Inventor
Akira Aida
晃 合田
Mitsuhiro Noguchi
充宏 野口
Yuji Takeuchi
祐司 竹内
Hiroaki Hazama
博顕 間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001380656A priority Critical patent/JP2003188252A/ja
Priority to KR10-2002-0079023A priority patent/KR100478667B1/ko
Priority to US10/318,257 priority patent/US6943453B2/en
Publication of JP2003188252A publication Critical patent/JP2003188252A/ja
Publication of JP2003188252A5 publication Critical patent/JP2003188252A5/ja
Priority to US10/943,250 priority patent/US7026241B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10D64/011—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2001380656A 2001-12-13 2001-12-13 半導体装置及びその製造方法 Pending JP2003188252A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2001380656A JP2003188252A (ja) 2001-12-13 2001-12-13 半導体装置及びその製造方法
KR10-2002-0079023A KR100478667B1 (ko) 2001-12-13 2002-12-12 반도체 장치 및 그 제조 방법
US10/318,257 US6943453B2 (en) 2001-12-13 2002-12-13 Superconductor device and method of manufacturing the same
US10/943,250 US7026241B2 (en) 2001-12-13 2004-09-17 Superconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001380656A JP2003188252A (ja) 2001-12-13 2001-12-13 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2003188252A true JP2003188252A (ja) 2003-07-04
JP2003188252A5 JP2003188252A5 (enExample) 2004-08-26

Family

ID=19187214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001380656A Pending JP2003188252A (ja) 2001-12-13 2001-12-13 半導体装置及びその製造方法

Country Status (3)

Country Link
US (2) US6943453B2 (enExample)
JP (1) JP2003188252A (enExample)
KR (1) KR100478667B1 (enExample)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005057127A (ja) * 2003-08-06 2005-03-03 Renesas Technology Corp 半導体記憶装置およびその製造方法
JP2005317580A (ja) * 2004-04-27 2005-11-10 Fujitsu Ltd 半導体装置
JP2005354029A (ja) * 2004-06-09 2005-12-22 Hynix Semiconductor Inc 低いコンタクト抵抗を有する半導体素子及びその製造方法
JP2006216960A (ja) * 2005-02-03 2006-08-17 Seoul National Univ Industry Foundation 複数層のドーピング層を有する電荷トラップメモリセルとこれを利用したメモリアレイ及びその動作方法
JP2006228798A (ja) * 2005-02-15 2006-08-31 Oki Electric Ind Co Ltd アライメントマークの形成方法および半導体装置の製造方法
JP2007158066A (ja) * 2005-12-06 2007-06-21 Ulvac Japan Ltd 絶縁膜、その製造方法及びその絶縁膜を用いた多層配線構造
JP2007318065A (ja) * 2006-05-26 2007-12-06 Hynix Semiconductor Inc フラッシュメモリ素子の製造方法
JP2008205493A (ja) * 2008-04-04 2008-09-04 Toshiba Corp 不揮発性半導体記憶装置の製造方法
US7429765B2 (en) 2003-09-30 2008-09-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
JP2009109581A (ja) * 2007-10-26 2009-05-21 Toshiba Corp 半導体装置の製造方法
JP2009259975A (ja) * 2008-04-15 2009-11-05 Toshiba Corp 半導体集積回路装置
US7622762B2 (en) 2003-07-15 2009-11-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and method for fabricating the same
JP2010062369A (ja) * 2008-09-04 2010-03-18 Toshiba Corp 半導体記憶装置
JP2012178618A (ja) * 2012-06-21 2012-09-13 Toshiba Corp 半導体装置
JP2013168687A (ja) * 2007-06-15 2013-08-29 Samsung Electronics Co Ltd 半導体素子の製造方法
US8759983B2 (en) 2008-01-31 2014-06-24 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4102112B2 (ja) * 2002-06-06 2008-06-18 株式会社東芝 半導体装置及びその製造方法
JP2004281631A (ja) * 2003-03-14 2004-10-07 Renesas Technology Corp 半導体装置の設計方法
KR100555514B1 (ko) * 2003-08-22 2006-03-03 삼성전자주식회사 저 저항 텅스텐 배선을 갖는 반도체 메모리 소자 및 그제조방법
JP4455017B2 (ja) * 2003-11-10 2010-04-21 株式会社東芝 不揮発性半導体記憶装置
KR20050056348A (ko) * 2003-12-10 2005-06-16 매그나칩 반도체 유한회사 반도체소자의 금속배선 형성방법
JP2005311131A (ja) * 2004-04-22 2005-11-04 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP2006073939A (ja) * 2004-09-06 2006-03-16 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
JP2006114550A (ja) * 2004-10-12 2006-04-27 Renesas Technology Corp 半導体装置およびその製造方法
DE102004059668B3 (de) * 2004-12-10 2006-07-13 Infineon Technologies Ag Halbleitertechnologieverfahren zur Herstellung einer leitfähigen Schicht
JP4713936B2 (ja) * 2005-05-09 2011-06-29 株式会社東芝 半導体装置
US7615448B2 (en) * 2005-12-06 2009-11-10 Sandisk Corporation Method of forming low resistance void-free contacts
WO2007067860A2 (en) * 2005-12-06 2007-06-14 Sandisk Corporation Low- resistance void-free contacts for eeprom devices
US7737483B2 (en) * 2005-12-06 2010-06-15 Sandisk Corporation Low resistance void-free contacts
JP4155587B2 (ja) * 2006-04-06 2008-09-24 株式会社東芝 半導体装置の製造方法
KR100843941B1 (ko) * 2006-12-26 2008-07-03 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7462038B2 (en) * 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
US20080296778A1 (en) * 2007-05-30 2008-12-04 Qimonda Ag Interconnection Structure and Integrated Circuit
KR100873894B1 (ko) * 2007-06-29 2008-12-15 삼성전자주식회사 반도체 장치의 제조 방법
JP4909912B2 (ja) * 2008-01-10 2012-04-04 株式会社東芝 パターン形成方法
JP4907563B2 (ja) * 2008-01-16 2012-03-28 パナソニック株式会社 半導体記憶装置
KR20090081119A (ko) * 2008-01-23 2009-07-28 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 및 그의 형성 방법
JP2009289949A (ja) * 2008-05-29 2009-12-10 Toshiba Corp 不揮発性半導体記憶装置
US20110042722A1 (en) * 2009-08-21 2011-02-24 Nanya Technology Corp. Integrated circuit structure and memory array
CN102593064B (zh) * 2012-03-11 2014-01-22 复旦大学 一种栅控二极管半导体存储器器件的制造方法
JP2013197537A (ja) * 2012-03-22 2013-09-30 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
KR20140004343A (ko) * 2012-07-02 2014-01-13 삼성전자주식회사 반도체 소자 및 그 제조 방법
DE102013109759B4 (de) 2013-03-12 2025-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren zum Strukturieren von Vias in einem Chip und Chipstruktur mit Vias
US9589974B2 (en) * 2013-09-11 2017-03-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacturing same
CN105612589B (zh) * 2013-12-27 2018-08-28 Lg化学株式会社 导电膜及其制造方法
US10090167B2 (en) * 2014-10-15 2018-10-02 Taiwan Semiconductor Manufacturing Company Semiconductor device and method of forming same
US10312192B2 (en) * 2016-06-02 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit having staggered conductive features
CN110729231A (zh) * 2018-07-17 2020-01-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法及半导体器件
CN111146201B (zh) * 2020-01-15 2021-04-30 长江存储科技有限责任公司 三维存储器及其制备方法
CN113893846B (zh) * 2021-11-18 2022-06-28 广东粤绿环境工程有限公司 一种锡、铈-钛酸锶固溶体压电制氢催化剂及其制备方法与应用
CN114822627B (zh) * 2022-02-23 2025-08-26 江南大学 一种降低IR Drop的存算阵列折叠布局方法

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JPH02265243A (ja) * 1989-04-05 1990-10-30 Nec Corp 多層配線およびその形成方法
US5589413A (en) 1995-11-27 1996-12-31 Taiwan Semiconductor Manufacturing Company Method of manufacturing self-aligned bit-line during EPROM fabrication
US6071810A (en) * 1996-12-24 2000-06-06 Kabushiki Kaisha Toshiba Method of filling contact holes and wiring grooves of a semiconductor device
JP3600393B2 (ja) 1997-02-10 2004-12-15 株式会社東芝 半導体装置及びその製造方法
KR100223914B1 (ko) * 1997-02-17 1999-10-15 구본준 다층배선 형성방법
JP4392867B2 (ja) * 1998-02-06 2010-01-06 株式会社ルネサステクノロジ 半導体装置およびその製造方法
KR100259075B1 (ko) * 1998-03-14 2000-06-15 김영환 반도체 소자 및 그의 제조 방법
US6411548B1 (en) 1999-07-13 2002-06-25 Kabushiki Kaisha Toshiba Semiconductor memory having transistors connected in series
JP2001332621A (ja) * 2000-03-13 2001-11-30 Toshiba Corp 半導体装置及びその製造方法

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7622762B2 (en) 2003-07-15 2009-11-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and method for fabricating the same
US8253182B2 (en) 2003-07-15 2012-08-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and method for fabricating the same
JP2005057127A (ja) * 2003-08-06 2005-03-03 Renesas Technology Corp 半導体記憶装置およびその製造方法
US7883964B2 (en) 2003-09-30 2011-02-08 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US7429765B2 (en) 2003-09-30 2008-09-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
JP2005317580A (ja) * 2004-04-27 2005-11-10 Fujitsu Ltd 半導体装置
JP2005354029A (ja) * 2004-06-09 2005-12-22 Hynix Semiconductor Inc 低いコンタクト抵抗を有する半導体素子及びその製造方法
JP2006216960A (ja) * 2005-02-03 2006-08-17 Seoul National Univ Industry Foundation 複数層のドーピング層を有する電荷トラップメモリセルとこれを利用したメモリアレイ及びその動作方法
JP2006228798A (ja) * 2005-02-15 2006-08-31 Oki Electric Ind Co Ltd アライメントマークの形成方法および半導体装置の製造方法
JP2007158066A (ja) * 2005-12-06 2007-06-21 Ulvac Japan Ltd 絶縁膜、その製造方法及びその絶縁膜を用いた多層配線構造
JP2007318065A (ja) * 2006-05-26 2007-12-06 Hynix Semiconductor Inc フラッシュメモリ素子の製造方法
JP2013168687A (ja) * 2007-06-15 2013-08-29 Samsung Electronics Co Ltd 半導体素子の製造方法
JP2009109581A (ja) * 2007-10-26 2009-05-21 Toshiba Corp 半導体装置の製造方法
US8759983B2 (en) 2008-01-31 2014-06-24 Kabushiki Kaisha Toshiba Semiconductor device
JP2008205493A (ja) * 2008-04-04 2008-09-04 Toshiba Corp 不揮発性半導体記憶装置の製造方法
JP2009259975A (ja) * 2008-04-15 2009-11-05 Toshiba Corp 半導体集積回路装置
JP2010062369A (ja) * 2008-09-04 2010-03-18 Toshiba Corp 半導体記憶装置
US7982244B2 (en) 2008-09-04 2011-07-19 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
US8377814B2 (en) 2008-09-04 2013-02-19 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
JP2012178618A (ja) * 2012-06-21 2012-09-13 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
US7026241B2 (en) 2006-04-11
KR100478667B1 (ko) 2005-03-28
US20050037612A1 (en) 2005-02-17
KR20030048349A (ko) 2003-06-19
US20030111732A1 (en) 2003-06-19
US6943453B2 (en) 2005-09-13

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