CN102593064B - 一种栅控二极管半导体存储器器件的制造方法 - Google Patents
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Abstract
本发明属于半导体存储器器件制造技术领域，具体公开了一种栅控二极管半导体存储器器件的制造方法。本发明采用低温工艺制备栅控二极管半导体存储器器件，工艺过程简单、制造成本低，而且所制造的栅控二极管存储器器件具有大驱动电流、小亚阈值摆幅的优点。本发明所提出的栅控二极管半导体存储器器件的制造方法特别适用于平板显示、浮栅存储器以及基于柔性衬底的存储器器件的制造中。
Description
技术领域
本发明属于半导体存储器器件制造技术领域，具体涉及一种半导体存储器器件的制造方法，特别涉及一种栅控二极管半导体存储器器件的制造方法。
背景技术
自从浮栅存储器结构提出以来，经过几十年的发展，浮栅存储器已在工业界得到了普遍应用。但是随着半导体器件尺寸的不断缩小，浮栅存储器缩小能力的不足逐渐显露出来，传统的浮栅存储器的结构如图1所示，包括在衬底101内形成的漏极102和源极103以及在衬底101之上形成的多晶硅栅极105、107，其中多晶硅栅极107与电气连接，称为控制栅，多晶硅栅极105是浮空的，称之为“浮栅”。浮栅105通过绝缘介质层104与衬底101隔离，并通过绝缘介质层106与控制栅107隔离。
浮栅存储器的工作原理是利用浮栅上是否储存有电荷或储存电荷的多少来改变晶体管的阈值电压，从而改变晶体管的外部特性，目前已经成为非易失性半导体存储器的基础器件结构。如今的集成电路器件技术节点已经处于45纳米左右，MOSFET的源、漏极之间的漏电流，随着沟道长度的缩小而迅速上升，这使得电子在浮栅上的保持特性受到严重影响，伴随反复地擦写，通道绝缘膜会发生损伤，这一损伤部分可能会使浮动栅内的电子出现泄漏的现象。而且，传统MOSFET的最小亚阈值摆幅(SS)被限制在60mv/dec，这限制了晶体管的开关速度。
发明内容
本发明的目的在于提出一种可减小浮栅存储器器件漏电流以及SS值，从而可以提升浮栅存储器器件的性能的栅控二极管半导体存储器器件的制造方法。
本发明提出的栅控二极管半导体存储器器件的制造方法，具体步骤包括：
在p型衬底之上形成第一种绝缘薄膜；
刻蚀所述第一种绝缘薄膜形成有源区窗口；
在所述第一种绝缘薄膜及有源区接触孔之上淀积n型材料，作为有源区，在所述有源区窗口处与p型衬底接触；
在所述n型有源区之上形成第二种绝缘薄膜；
在所述第二种绝缘薄膜之上淀积第一种导电材料并刻蚀形成器件的浮栅；
覆盖所述浮栅形成第三种绝缘薄膜；
刻蚀所述第三种、第二种、第一种绝缘薄膜，在所述有源区窗口的两侧分别形成漏极接触窗口和源极接触窗口，漏极接触孔处p型衬底被暴露，源极接触孔处n型有源区被暴露；
淀积形成第二种导电薄膜并刻蚀所述第二种导电薄膜形成漏极电极、栅极电极、源极电极，漏极电极位于漏极接触孔之上并充满所述漏极接触孔，源极电极位于源极接触孔之上并充满所述源极接触孔，并且，栅极电极处于源极电极和所述有源区窗口之间，有源区窗口处于漏极电极和栅极极电极之间，栅极电极和有源区窗口间距为20纳米至1微米。
进一步地，所述的p型有源区包括但不局限于重掺杂的p型硅衬底、在硅衬底内形成的p型掺杂区、在绝缘基底上形成的掺杂有p型杂质离子的ZnO或者NiO材料。所述的第一种绝缘薄膜为氧化硅或者氮化硅。所述的第二种、第三种绝缘薄膜为SiO2或者HfO2等高介电常数材料。所述的第二种导电薄膜为铜、钨、铝、氮化钛或者为氮化钽。
更进一步地，所述的n型有源区由ZnO材料形成，其厚度范围为5-10纳米。所述的浮栅包括但不局限于多晶硅材料。
本发明采用低温工艺制备栅控二极管半导体存储器器件，工艺过程简单、制造成本低，而且所制造的栅控二极管存储器器件具有大驱动电流、小亚阈值摆幅的优点。本发明所提出的栅控二极管半导体存储器器件的制造方法特别适用于平板显示、浮栅存储器以及基于柔性衬底的存储器器件的制造中。
附图说明
图1为传统的浮栅存储器的结构示意图。
图2-图7为本发明所公开的栅控二极管半导体存储器器件的制造方法的一个实施例的工艺流程图。
具体实施方式
下面将参照附图对本发明的一个示例性实施方式作详细说明。在图中，为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不能完全准确的反映出器件的实际尺寸，但是它们还是完整的反映了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。
参考图是本发明的理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。例如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中，均以矩形表示，图中的表示是示意性的，但这不应该被认为是限制本发明的范围。
首先，取NaOH和水，以1:20的比例配成溶液，加热至80℃后，泡洗聚酰亚胺（PI）衬底表面20分钟。然后将PI衬底泡于异丙醇溶液中，超声清洗10分钟。最后将PI衬底放入去离子水中，超声清洗10分钟，并用N2将PI衬底表面吹干。
在处理好后的PI衬底201上淀积一层二氧化硅薄膜202，接着在二氧化硅薄膜202上淀积一层掺杂有p型杂质离子的NiO材料，并刻蚀所淀积的NiO材料形成p型有源区203，如图2所示。
接下来，再次淀积一层二氧化硅薄膜204，接着淀积一层光刻胶并掩膜、曝光、显影形成图形，然后刻蚀二氧化硅薄膜204形成窗口，剥除光刻胶后如图3所示。
接下来，采用原子层淀积的方法淀积一层约5-10纳米后的ZnO材料并刻蚀所淀积的ZnO材料形成n型有源区205，如图4所示。
接着淀积一层高介电常数材料206，比如为HfO2，继续在高介电常数材料206之上淀积一层多晶硅，并刻蚀所淀积的多晶硅材料形成器件的浮栅207，如图5所示。
接下来，淀积一层绝缘薄膜208，比如为氧化硅，并淀积一层光刻胶并掩膜、曝光、显影形成图形，然后刻蚀氧化硅薄膜208、高介电常数材料206、绝缘薄膜204定义出漏极与源极的位置，如图6所示。
最后，淀积一层金属导电薄膜，比如为铝，然后通过光刻工艺与刻蚀工艺形成漏极电极209、栅极电极210、源极电极211，如图7所示。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。
Claims (7)
1. 一种栅控二极管半导体存储器器件的制造方法，其特征在于具体步骤包括：
在p型衬底之上形成第一种绝缘薄膜；
刻蚀所述第一种绝缘薄膜形成有源区窗口；
在所述第一种绝缘薄膜及有源区窗口之上淀积n型材料，作为n型有源区，在所述有源区窗口处与p型衬底接触；
在所述n型有源区之上形成第二种绝缘薄膜；
在所述第二种绝缘薄膜之上淀积第一种导电材料并刻蚀形成器件的浮栅；
覆盖所述浮栅形成第三种绝缘薄膜；
刻蚀所述第三种、第二种、第一种绝缘薄膜，在所述有源区窗口的两侧分别形成漏极接触孔和源极接触孔，漏极接触孔处p型衬底被暴露，源极接触孔处n型有源区被暴露；
淀积形成第二种导电薄膜并刻蚀所述第二种导电薄膜形成漏极电极、栅极电极、源极电极，漏极电极位于漏极接触孔之上并充满所述漏极接触孔，源极电极位于源极接触孔之上并充满所述源极接触孔，并且，栅极电极处于源极电极和所述有源区窗口之间，有源区窗口处于漏极电极和栅极极电极之间，栅极电极和有源区窗口间距为20纳米至1微米。
2. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的p型有源区包括重掺杂的p型硅衬底、在硅衬底内形成的p型掺杂区、在绝缘基底上形成的掺杂有p型杂质离子的ZnO或者NiO材料。
3. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的第一种绝缘薄膜为氧化硅或者氮化硅。
4. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的第二种、第三种绝缘薄膜为SiO2或者HfO2。
5. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的n型有源区由ZnO材料形成，其厚度范围为5-10纳米。
6. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的浮栅为多晶硅材料。
7. 根据权利要求1所述的栅控二极管半导体存储器器件的制造方法，其特征在于，所述的第二种导电薄膜为铜、钨、铝、氮化钛或者为氮化钽。
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| CN111477624B (zh) * | 2020-04-27 | 2022-10-11 | 复旦大学 | 一种基于纵向隧穿晶体管的半浮栅存储器及其制备方法 |
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| JP2987884B2 (ja) * | 1990-06-04 | 1999-12-06 | 日産自動車株式会社 | 半導体装置 |
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