JP2002542622A - エピプロセスを用いたｓｏｉ基板の表面仕上げ - Google Patents

エピプロセスを用いたｓｏｉ基板の表面仕上げ

Info

Publication number
JP2002542622A
JP2002542622A JP2000612989A JP2000612989A JP2002542622A JP 2002542622 A JP2002542622 A JP 2002542622A JP 2000612989 A JP2000612989 A JP 2000612989A JP 2000612989 A JP2000612989 A JP 2000612989A JP 2002542622 A JP2002542622 A JP 2002542622A
Authority
JP
Japan
Prior art keywords
substrate
silicon
wafer
hydrogen
cleavage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000612989A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002542622A5 (enExample
Inventor
カン・シェン・ジー
マリク・イゴー・ジェイ
Original Assignee
シリコン ジェネシス コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シリコン ジェネシス コーポレイション filed Critical シリコン ジェネシス コーポレイション
Publication of JP2002542622A publication Critical patent/JP2002542622A/ja
Publication of JP2002542622A5 publication Critical patent/JP2002542622A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Magnetic Heads (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2000612989A 1999-04-21 2000-04-20 エピプロセスを用いたｓｏｉ基板の表面仕上げ Pending JP2002542622A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13042399P 1999-04-21 1999-04-21
US60/130,423 1999-04-21
US09/399,985 1999-09-20
US09/399,985 US6287941B1 (en) 1999-04-21 1999-09-20 Surface finishing of SOI substrates using an EPI process
PCT/US2000/010872 WO2000063954A1 (en) 1999-04-21 2000-04-20 Surface finishing of soi substrates using an epi process

Publications (2)

Publication Number Publication Date
JP2002542622A true JP2002542622A (ja) 2002-12-10
JP2002542622A5 JP2002542622A5 (enExample) 2007-06-14

Family

ID=26828477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000612989A Pending JP2002542622A (ja) 1999-04-21 2000-04-20 エピプロセスを用いたｓｏｉ基板の表面仕上げ

Country Status (8)

Country Link
US (3) US6287941B1 (enExample)
EP (2) EP1887616A3 (enExample)
JP (1) JP2002542622A (enExample)
KR (2) KR20060126629A (enExample)
AT (1) ATE372590T1 (enExample)
AU (1) AU4483300A (enExample)
DE (1) DE60036286T2 (enExample)
WO (1) WO2000063954A1 (enExample)

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JP2001168046A (ja) * 1999-09-17 2001-06-22 Applied Materials Inc シリコン膜表面仕上のための装置及び方法
JP2005129825A (ja) * 2003-10-27 2005-05-19 Sumitomo Chemical Co Ltd 化合物半導体基板の製造方法
JP2007281166A (ja) * 2006-04-06 2007-10-25 Matsushita Electric Ind Co Ltd 接合方法および接合装置ならびに接合基板
JP2008300617A (ja) * 2007-05-31 2008-12-11 Ihi Corp レーザアニール方法及びレーザアニール装置
JP2010500761A (ja) * 2006-08-09 2010-01-07 アプライド マテリアルズ インコーポレイテッド シリコン・オン・インシュレータ構造に使用されるプラズマ浸漬イオン注入処理による表面活性化のための方法
JP2014007421A (ja) * 2005-02-28 2014-01-16 Silicon Genesis Corp レイヤ転送プロセス用の基板強化方法および結果のデバイス

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US6171965B1 (en) 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US6287941B1 (en) 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
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US8507361B2 (en) * 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
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ATE372590T1 (de) 2007-09-15
US6287941B1 (en) 2001-09-11
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US20070259526A1 (en) 2007-11-08
US20020022344A1 (en) 2002-02-21
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EP1194949B1 (en) 2007-09-05
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