JP2002176137A - 積層型半導体デバイス - Google Patents

積層型半導体デバイス

Info

Publication number
JP2002176137A
JP2002176137A JP2001288048A JP2001288048A JP2002176137A JP 2002176137 A JP2002176137 A JP 2002176137A JP 2001288048 A JP2001288048 A JP 2001288048A JP 2001288048 A JP2001288048 A JP 2001288048A JP 2002176137 A JP2002176137 A JP 2002176137A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
stacked
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001288048A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002176137A5 (https=
Inventor
Mie Matsuo
美恵 松尾
Nobuo Hayasaka
伸夫 早坂
Tsunetoshi Arikado
経敏 有門
Yasushi Sakui
康司 作井
Hidemi Ishiuchi
秀美 石内
Tomoaki Takubo
知章 田窪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001288048A priority Critical patent/JP2002176137A/ja
Priority to DE10147084A priority patent/DE10147084A1/de
Priority to US09/961,332 priority patent/US6717251B2/en
Publication of JP2002176137A publication Critical patent/JP2002176137A/ja
Publication of JP2002176137A5 publication Critical patent/JP2002176137A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
JP2001288048A 2000-09-28 2001-09-21 積層型半導体デバイス Pending JP2002176137A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001288048A JP2002176137A (ja) 2000-09-28 2001-09-21 積層型半導体デバイス
DE10147084A DE10147084A1 (de) 2000-09-28 2001-09-25 Halbleitervorrichtung vom gestapelten Typ
US09/961,332 US6717251B2 (en) 2000-09-28 2001-09-25 Stacked type semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-296822 2000-09-28
JP2000296822 2000-09-28
JP2001288048A JP2002176137A (ja) 2000-09-28 2001-09-21 積層型半導体デバイス

Publications (2)

Publication Number Publication Date
JP2002176137A true JP2002176137A (ja) 2002-06-21
JP2002176137A5 JP2002176137A5 (https=) 2005-08-11

Family

ID=26600976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001288048A Pending JP2002176137A (ja) 2000-09-28 2001-09-21 積層型半導体デバイス

Country Status (3)

Country Link
US (1) US6717251B2 (https=)
JP (1) JP2002176137A (https=)
DE (1) DE10147084A1 (https=)

Cited By (9)

* Cited by examiner, † Cited by third party
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WO2004102663A1 (ja) * 2003-05-15 2004-11-25 Kumamoto Technology & Industry Foundation 半導体チップ実装体およびその製造方法
JP2006173388A (ja) * 2004-12-16 2006-06-29 Matsushita Electric Ind Co Ltd 多段構成半導体モジュールおよびその製造方法
KR100737162B1 (ko) 2006-08-11 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR100807050B1 (ko) 2006-08-23 2008-02-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
CN100446244C (zh) * 2003-05-15 2008-12-24 财团法人熊本高新技术产业财团 半导体芯片安装体及其制造方法
JP2010109264A (ja) * 2008-10-31 2010-05-13 Hitachi Ltd 半導体集積回路装置
JP2010206118A (ja) * 2009-03-06 2010-09-16 Canon Inc 積層型半導体装置
JP2011146527A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
JP2012244110A (ja) * 2011-05-24 2012-12-10 Canon Inc 半導体装置

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JP2003110091A (ja) * 2001-09-28 2003-04-11 Toshiba Corp 半導体装置及び半導体装置の製造方法
US7041355B2 (en) * 2001-11-29 2006-05-09 Dow Global Technologies Inc. Structural reinforcement parts for automotive assembly
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
CA2472727C (en) * 2002-01-22 2010-10-26 Dow Global Technologies Inc. Reinforced structural body and manufacturing method thereof
KR100931762B1 (ko) 2002-04-15 2009-12-14 다우 글로벌 테크놀로지스 인크. 발포체 제품 및 이를 사용한 발포체 충전 차량 중공 부재 형성 방법
DE10227305A1 (de) * 2002-06-19 2003-09-04 Siemens Dematic Ag Elektrisches Mehrschicht-Bauelement-Modul und Verfahren zu dessen Herstellung
US6891447B2 (en) * 2002-07-12 2005-05-10 Massachusetts Institute Of Technology Electromagnetic coupling connector for three-dimensional electronic circuits
US7056810B2 (en) * 2002-12-18 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance
CA2509629A1 (en) * 2002-12-27 2004-07-22 Dow Global Technologies Inc. Heat activated epoxy adhesive and use in a structural foam insert
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4938445B2 (ja) * 2003-03-05 2012-05-23 ダウ グローバル テクノロジーズ エルエルシー 構造用強化物品及びその製造方法
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
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US8471263B2 (en) * 2003-06-24 2013-06-25 Sang-Yun Lee Information storage system which includes a bonded semiconductor structure
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP3896112B2 (ja) * 2003-12-25 2007-03-22 エルピーダメモリ株式会社 半導体集積回路装置
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
KR100618838B1 (ko) * 2004-06-24 2006-09-01 삼성전자주식회사 상하 연결 능력을 개선할 수 있는 스택형 멀티칩 패키지
JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7588963B2 (en) * 2004-06-30 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming overhang support for a stacked semiconductor device
US7166924B2 (en) * 2004-08-17 2007-01-23 Intel Corporation Electronic packages with dice landed on wire bonds
US7602618B2 (en) * 2004-08-25 2009-10-13 Micron Technology, Inc. Methods and apparatuses for transferring heat from stacked microfeature devices
US7462925B2 (en) * 2004-11-12 2008-12-09 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using via to provide interconnection
JP4433298B2 (ja) * 2004-12-16 2010-03-17 パナソニック株式会社 多段構成半導体モジュール
JP4577688B2 (ja) 2005-05-09 2010-11-10 エルピーダメモリ株式会社 半導体チップ選択方法、半導体チップ及び半導体集積回路装置
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
TWI429066B (zh) 2005-06-02 2014-03-01 新力股份有限公司 Semiconductor image sensor module and manufacturing method thereof
US7432592B2 (en) * 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
JP4799157B2 (ja) 2005-12-06 2011-10-26 エルピーダメモリ株式会社 積層型半導体装置
JP4753725B2 (ja) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
US7462509B2 (en) * 2006-05-16 2008-12-09 International Business Machines Corporation Dual-sided chip attached modules
JP4910512B2 (ja) * 2006-06-30 2012-04-04 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US20080023824A1 (en) * 2006-07-28 2008-01-31 Texas Instruments Double-sided die
KR100809696B1 (ko) * 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US7514775B2 (en) * 2006-10-09 2009-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US20080157322A1 (en) * 2006-12-27 2008-07-03 Jia Miao Tang Double side stacked die package
US7605477B2 (en) * 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US7598523B2 (en) * 2007-03-19 2009-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for stacking dies having through-silicon vias
KR100843243B1 (ko) * 2007-04-18 2008-07-02 삼성전자주식회사 신호의 전송파워를 최적화한 반도체 메모리 장치 및 그파워 초기화 방법
JP2008294367A (ja) * 2007-05-28 2008-12-04 Nec Electronics Corp 半導体装置およびその製造方法
US7880310B2 (en) * 2007-09-28 2011-02-01 Intel Corporation Direct device attachment on dual-mode wirebond die
US7952183B2 (en) * 2007-10-29 2011-05-31 Kabushiki Kaisha Toshiba High capacity memory with stacked layers
JP2010080801A (ja) * 2008-09-29 2010-04-08 Hitachi Ltd 半導体装置
JP5331427B2 (ja) * 2008-09-29 2013-10-30 株式会社日立製作所 半導体装置
US20100237481A1 (en) * 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US7923290B2 (en) * 2009-03-27 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system having dual sided connection and method of manufacture thereof
US8294240B2 (en) * 2009-06-08 2012-10-23 Qualcomm Incorporated Through silicon via with embedded decoupling capacitor
CN102668050B (zh) * 2009-11-25 2015-12-02 英特尔公司 穿硅过孔保护环
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KR102439761B1 (ko) * 2017-12-22 2022-09-02 삼성전자주식회사 전자 장치 및 전자 장치의 제조 방법
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JP2019220621A (ja) 2018-06-21 2019-12-26 キオクシア株式会社 半導体装置及びその製造方法
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004102663A1 (ja) * 2003-05-15 2004-11-25 Kumamoto Technology & Industry Foundation 半導体チップ実装体およびその製造方法
JP2004363573A (ja) * 2003-05-15 2004-12-24 Kumamoto Technology & Industry Foundation 半導体チップ実装体およびその製造方法
CN100446244C (zh) * 2003-05-15 2008-12-24 财团法人熊本高新技术产业财团 半导体芯片安装体及其制造方法
JP2006173388A (ja) * 2004-12-16 2006-06-29 Matsushita Electric Ind Co Ltd 多段構成半導体モジュールおよびその製造方法
KR100737162B1 (ko) 2006-08-11 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR100807050B1 (ko) 2006-08-23 2008-02-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
JP2010109264A (ja) * 2008-10-31 2010-05-13 Hitachi Ltd 半導体集積回路装置
US8253227B2 (en) 2008-10-31 2012-08-28 Hitachi, Ltd. Semiconductor integrated circuit device
JP2010206118A (ja) * 2009-03-06 2010-09-16 Canon Inc 積層型半導体装置
JP2011146527A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
JP2012244110A (ja) * 2011-05-24 2012-12-10 Canon Inc 半導体装置

Also Published As

Publication number Publication date
US20020036338A1 (en) 2002-03-28
DE10147084A1 (de) 2002-06-27
US6717251B2 (en) 2004-04-06

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