IT1255920B - Memoria di sola lettura a maschera di tipo nand - Google Patents

Memoria di sola lettura a maschera di tipo nand

Info

Publication number
IT1255920B
IT1255920B ITMI922458A ITMI922458A IT1255920B IT 1255920 B IT1255920 B IT 1255920B IT MI922458 A ITMI922458 A IT MI922458A IT MI922458 A ITMI922458 A IT MI922458A IT 1255920 B IT1255920 B IT 1255920B
Authority
IT
Italy
Prior art keywords
string selection
reading memory
transistors
depletion
series
Prior art date
Application number
ITMI922458A
Other languages
English (en)
Italian (it)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of ITMI922458A0 publication Critical patent/ITMI922458A0/it
Publication of ITMI922458A1 publication Critical patent/ITMI922458A1/it
Application granted granted Critical
Publication of IT1255920B publication Critical patent/IT1255920B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
ITMI922458A 1991-10-29 1992-10-27 Memoria di sola lettura a maschera di tipo nand IT1255920B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR910019085 1991-10-29

Publications (3)

Publication Number Publication Date
ITMI922458A0 ITMI922458A0 (it) 1992-10-27
ITMI922458A1 ITMI922458A1 (it) 1994-04-27
IT1255920B true IT1255920B (it) 1995-11-17

Family

ID=19321940

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI922458A IT1255920B (it) 1991-10-29 1992-10-27 Memoria di sola lettura a maschera di tipo nand

Country Status (7)

Country Link
JP (1) JPH05218328A (zh)
KR (1) KR960005564B1 (zh)
CN (1) CN1072040A (zh)
DE (1) DE4229129A1 (zh)
FR (1) FR2683078A1 (zh)
GB (1) GB2261090A (zh)
IT (1) IT1255920B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100358148B1 (ko) * 1995-05-15 2003-01-08 주식회사 하이닉스반도체 마스크롬
KR100358139B1 (ko) * 1995-07-11 2003-01-15 주식회사 하이닉스반도체 마스크롬
KR980005033A (ko) * 1996-06-27 1998-03-30 김주용 마스크 롬 디바이스
JP2001506409A (ja) * 1996-12-17 2001-05-15 シーメンス アクチエンゲゼルシヤフト メモリセル装置の並列な導線を駆動するための装置
JP2005243127A (ja) * 2004-02-25 2005-09-08 Sanyo Electric Co Ltd 紫外線消去型半導体メモリ装置
KR101094840B1 (ko) * 2005-07-12 2011-12-16 삼성전자주식회사 낸드형 플래시 메모리 장치 및 그 제조 방법
CN102214485B (zh) * 2010-04-02 2016-03-30 台湾积体电路制造股份有限公司 只读存储器与只读存储器操作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305139A (en) * 1979-12-26 1981-12-08 International Business Machines Corporation State detection for storage cells
US4980861A (en) * 1987-01-16 1990-12-25 Microchip Technology Incorporated NAND stack ROM
JPH01276757A (ja) * 1988-04-28 1989-11-07 Fujitsu Ltd 半導体記憶装置の製造方法
KR910004166B1 (ko) * 1988-12-27 1991-06-22 삼성전자주식회사 낸드쎌들을 가지는 전기적으로 소거 및 프로그램 가능한 반도체 메모리장치
JP2509707B2 (ja) * 1989-09-04 1996-06-26 株式会社東芝 半導体装置の製造方法
KR940004609B1 (ko) * 1991-09-04 1994-05-25 삼성전자 주식회사 마스크 리드 온리 메모리

Also Published As

Publication number Publication date
ITMI922458A0 (it) 1992-10-27
CN1072040A (zh) 1993-05-12
JPH05218328A (ja) 1993-08-27
KR930009080A (ko) 1993-05-22
FR2683078A1 (fr) 1993-04-30
KR960005564B1 (ko) 1996-04-26
DE4229129A1 (de) 1993-05-06
GB9222728D0 (en) 1992-12-09
GB2261090A (en) 1993-05-05
ITMI922458A1 (it) 1994-04-27

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