CN1072040A - 与非型掩码只读存储器 - Google Patents

与非型掩码只读存储器 Download PDF

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Publication number
CN1072040A
CN1072040A CN92112534A CN92112534A CN1072040A CN 1072040 A CN1072040 A CN 1072040A CN 92112534 A CN92112534 A CN 92112534A CN 92112534 A CN92112534 A CN 92112534A CN 1072040 A CN1072040 A CN 1072040A
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character string
mask rom
read
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CN92112534A
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崔正达
李炯坤
李一宽
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1072040A publication Critical patent/CN1072040A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Abstract

一与非型掩码只读存储器包含一串联连于比特 线的耗尽型和增强型第一和第二字符串选择晶体管， 且多个单元晶体管串联连接于字符串选择晶体管和 接地电压端之间，其中增强型字符串选择晶体管的沟 道长度长于耗尽型字符串选择晶体管，这样避免了漏 电流进入未选的字符串。

Description

本发明涉及一半导体存储器，特别是一与非型掩码（mask）只读存储器（以下称为掩码ROM）的字符串（string）选择晶体管。
一掩码ROM通常包含多个耗尽型晶体管，通过扩散层与多个增强型晶体管串联连接。在一比特线和接地电压端之间串联连接的一组地址单元定义为一个字符串。
图1示出了与非型掩码ROM等效电路的一部分，它包含串联于比特线的第一和第二字符串选择晶体管和串联在字符串选择晶体管源极与接地电压端之间的n-MOS晶体管，该晶体管作为存储单元。同行的字符串选择晶体管的门共享一条字符串选择线，而同行的存储单元的门占用同一字码线。
与非型掩码ROM的作用描述如下。为了读出给定所选的存储单元，分别向电压源Vcc施加1V的读电压，和向所选的比特和字码线施加0V地电压。按照字符串选择晶体管是耗尽型还是增强型而向字符串选择晶体管的门施加0（零）电压或Vcc。未选中的字码线接收Vcc。因此，所述的耗尽型存储单元被加到门的地电压所导通，以使比特线传送代表逻辑“1”的读出电压。相反地，所选的增强型存储单元被加到门上的接地电压关闭，以使比特线被表示逻辑“0”的读出电压所切断。换句话说，通过向所选的存储单元门施加接地电压，通常利用耗尽型晶体管的通和增强型晶体管的断来分别表示逻辑“1”和“0”。
参阅图2所示展开了的图1等效电路图，该电路包含一在半导体底基中构成n+扩散区的作用（active）线20，该线在第一方向上扩展;沿着第一方向相互平行且跨越作用线20设置的字符串选择线22、23，字码线24、25、26和地线28在第二方向上扩展，比特线30在第一方向上跨越字码线24、25、26扩展，接触区32用以使作用线20和比特线30相接触。参考序号34、35、36示出耗尽型MOS晶体管。
同时，随着对大容量存储装置需求的增加，单元阵列中的字符串选择晶体管和单元（cell）晶体管的沟道长度减少至亚微米量级。因此，常会出现漏电流进入未选的字符串选择晶体管，这就引起逻辑混乱。换句话说，随着单元尺寸的减小，在例如成形、蚀刻多晶硅和用于调节阈值电压的离子注入等制造过程中，单元的沟通长度和掺杂浓度分布会对这种环境变化很敏感。相应地，如图2所示，若字符串选择晶体管与单元晶体管有同样的尺寸，漏电流进入未选的字符串选择晶体管，当读一关断的单元时会引起逻辑混乱。当寻求一用于高速读操作的带有Vcc的比特线时，这个问题就更突出了。
本发明的目的在于提供一与非型掩码ROM，它既使在单元晶体管的尺寸减至亚微米量级时仍准确地执行读出功能。
按照本发明，在连于一串掩码ROM的第一和第二字符串选择晶体管中，增强型字符串选择晶体管的沟道长度大于耗尽型和单元晶体管的沟道长度。
为了更好地理解本发明，并展示它是怎样起作用的，通过一例子并附以示意图对此作出说明，其中：
图1画出了一与非型掩码ROM等效电路一部分的原理图;
图2是依照现有技术的图1中与非型掩码ROM的展开;
图3是依照本发明的图1中与非型掩码ROM的展开。
参阅图3，展示在半导体底基中构成了n+扩散区的作用线40，它在第一方向上扩展。沿着第一方向相互平行且跨越作用线40设置的字符串选择线42、43和字码线44、45、46在第二方向上扩展。在第一方向上扩展的比特线50跨越字码线而成。制成一接触区52用以使作用线40和比特线50相接触。参考序号54、55、56示出了耗尽型MOS晶体管。如图所示，由于增强型晶体管的设计宽度在第一方向上增加了，所以增强型字符串选择晶体管的沟道长度大于其它的晶体管。扩展的沟道长度做得足够长，以便既使在漏极电压超出Vcc时也不引起击穿。在超过16M且装置采用的工作电压在2.5-3.5V的情况下，增强型字符串选择晶体管制成的沟道长度比其它字符串选择晶体管长约0.1μm。另一情况下，也即低于4M，装置有4.5-5.5V电压时，增强型字符串选择晶体管制成的沟道长度需长出约0.2μm。这样就防止了击穿未选的字符串选择晶体管，也因此防止了由于漏电流引起的逻辑混乱。
如上所述，依据本发明的与非型掩码ROM有沟道长度大于其它字符串选择晶体管的增强型字符串选择晶体管，以便既使晶体管的有效沟道长度和用于调节阈值电压的沟道中掺杂的剂量浓度分布，由于制造掩码ROM的过程变量而稍微变化的话，也可防止击穿增强型字符串选择晶体管。因此漏电流进入不了未选的字符串，也就避免了逻辑混乱。另外，只有两个字符串选择晶体管之一具有扩展的沟道长度，因而不需增加字符串长度方向上的展开面积便可保证存储器的可靠性。
尽管本发明参考选出的特定实施例作了图示和描述，但很明显对于技术熟练者来说，在不背离本发明的精神和范围的情况下，可作出上述形式和细节上的改变。

Claims (3)

1、一与非型掩码只读存储器包括：
一第一和第二字符串选择晶体管，各自包含耗尽型和增强型，串联连接于一比特线，其中，所说的增强型字符串选择晶体管的沟道长度要长于所说的耗尽型字符串选择晶体管；且
多个单元晶体管串联连接于所说的字符串选择晶体管和接地电压端之间。
2、如权利要求1中的与非型掩码只读存储器，其中，所说的增强型字符串选择晶体管的沟道长度长于所说的单元晶体管。
3、如权利要求1中的与非型掩码只读存储器，其中所说的增强型字符串选择晶体管的沟道长度设计得足够长，以便在既使漏电压超出电源电压时也不出现击穿。
CN92112534A 1991-10-29 1992-10-29 与非型掩码只读存储器 Pending CN1072040A (zh)

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KR910019085 1991-10-29
KR19085/91 1991-10-29

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JP (1) JPH05218328A (zh)
KR (1) KR960005564B1 (zh)
CN (1) CN1072040A (zh)
DE (1) DE4229129A1 (zh)
FR (1) FR2683078A1 (zh)
GB (1) GB2261090A (zh)
IT (1) IT1255920B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426509C (zh) * 2004-02-25 2008-10-15 三洋电机株式会社 紫外线擦除型半导体存储装置
CN102214485A (zh) * 2010-04-02 2011-10-12 台湾积体电路制造股份有限公司 只读存储器与只读存储器操作方法

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KR100358148B1 (ko) * 1995-05-15 2003-01-08 주식회사 하이닉스반도체 마스크롬
KR100358139B1 (ko) * 1995-07-11 2003-01-15 주식회사 하이닉스반도체 마스크롬
KR980005033A (ko) * 1996-06-27 1998-03-30 김주용 마스크 롬 디바이스
JP2001506409A (ja) * 1996-12-17 2001-05-15 シーメンス アクチエンゲゼルシヤフト メモリセル装置の並列な導線を駆動するための装置
KR101094840B1 (ko) * 2005-07-12 2011-12-16 삼성전자주식회사 낸드형 플래시 메모리 장치 및 그 제조 방법

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US4305139A (en) * 1979-12-26 1981-12-08 International Business Machines Corporation State detection for storage cells
US4980861A (en) * 1987-01-16 1990-12-25 Microchip Technology Incorporated NAND stack ROM
JPH01276757A (ja) * 1988-04-28 1989-11-07 Fujitsu Ltd 半導体記憶装置の製造方法
KR910004166B1 (ko) * 1988-12-27 1991-06-22 삼성전자주식회사 낸드쎌들을 가지는 전기적으로 소거 및 프로그램 가능한 반도체 메모리장치
JP2509707B2 (ja) * 1989-09-04 1996-06-26 株式会社東芝 半導体装置の製造方法
KR940004609B1 (ko) * 1991-09-04 1994-05-25 삼성전자 주식회사 마스크 리드 온리 메모리

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426509C (zh) * 2004-02-25 2008-10-15 三洋电机株式会社 紫外线擦除型半导体存储装置
CN102214485A (zh) * 2010-04-02 2011-10-12 台湾积体电路制造股份有限公司 只读存储器与只读存储器操作方法
CN102214485B (zh) * 2010-04-02 2016-03-30 台湾积体电路制造股份有限公司 只读存储器与只读存储器操作方法

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JPH05218328A (ja) 1993-08-27
DE4229129A1 (de) 1993-05-06
GB9222728D0 (en) 1992-12-09
GB2261090A (en) 1993-05-05
KR960005564B1 (ko) 1996-04-26
ITMI922458A1 (it) 1994-04-27
FR2683078A1 (fr) 1993-04-30
KR930009080A (ko) 1993-05-22
ITMI922458A0 (it) 1992-10-27
IT1255920B (it) 1995-11-17

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