IT1247303B - Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso - Google Patents
Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di essoInfo
- Publication number
- IT1247303B IT1247303B ITMI911161A ITMI911161A IT1247303B IT 1247303 B IT1247303 B IT 1247303B IT MI911161 A ITMI911161 A IT MI911161A IT MI911161 A ITMI911161 A IT MI911161A IT 1247303 B IT1247303 B IT 1247303B
- Authority
- IT
- Italy
- Prior art keywords
- source
- dram
- well
- conductive layers
- pitch
- Prior art date
Links
- 230000002093 peripheral effect Effects 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000463 material Substances 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Transistor MOS (30a, 30b) incluso in un circuito periferico di una DRAM, il quale ha strati conduttori (16, 17) per l'interconnessione su superfici rispettive di una coppia di regioni sorgente-pozzo (33a, 33b). Gli strati (18) di interconnessione sorgente-pozzo sono collegati elettricamente alle regioni di sorgente-pozzo attraverso degli strati conduttori (16, 17). Uno della coppia di strati conduttori è formato nella medesima fase con una linea (15) di bit di una cella di memoria, mediante il medesimo materiale della linea di bit. L'altro della coppia di strati conduttori è formato nella medesima fase come un nodo di immagazzinamento (11) di un condensatore (10) della cella di memoria, impiegando il medesimo materiale del nodo di immagazzinamento. La coppia di strati conduttori impedisce connessione diretta tra lo strato di interconnessione sorgente-pozzo e le regioni di sorgente-pozzo, in modo tale che può essere realizzata riduzione nelle dimensioni delle regioni di sorgente-pozzo.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2115642A JP2524862B2 (ja) | 1990-05-01 | 1990-05-01 | 半導体記憶装置およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI911161A0 ITMI911161A0 (it) | 1991-04-29 |
ITMI911161A1 ITMI911161A1 (it) | 1992-10-29 |
IT1247303B true IT1247303B (it) | 1994-12-12 |
Family
ID=14667697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI911161A IT1247303B (it) | 1990-05-01 | 1991-04-29 | Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso |
Country Status (5)
Country | Link |
---|---|
US (4) | US5486712A (it) |
JP (1) | JP2524862B2 (it) |
KR (1) | KR940005889B1 (it) |
DE (1) | DE4113932A1 (it) |
IT (1) | IT1247303B (it) |
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JP3230696B2 (ja) * | 1992-06-12 | 2001-11-19 | ソニー株式会社 | 半導体記憶装置の製造方法 |
DE4221431A1 (de) * | 1992-06-30 | 1994-01-05 | Siemens Ag | Herstellverfahren für einen Schlüsselkondensator |
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US5994730A (en) | 1996-11-21 | 1999-11-30 | Alliance Semiconductor Corporation | DRAM cell having storage capacitor contact self-aligned to bit lines and word lines |
JP3331910B2 (ja) | 1997-06-20 | 2002-10-07 | 日本電気株式会社 | 半導体装置及びその製造方法 |
KR100269317B1 (ko) * | 1997-12-09 | 2000-12-01 | 윤종용 | 평탄화를위한반도체장치및그제조방법 |
JPH11121710A (ja) * | 1997-10-09 | 1999-04-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
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US6015733A (en) * | 1998-08-13 | 2000-01-18 | Taiwan Semiconductor Manufacturing Company | Process to form a crown capacitor structure for a dynamic random access memory cell |
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FR2785720B1 (fr) * | 1998-11-05 | 2003-01-03 | St Microelectronics Sa | Fabrication de memoire dram et de transistors mos |
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KR100363099B1 (ko) * | 2001-01-12 | 2002-12-05 | 삼성전자 주식회사 | 주변회로부의 소오스/드레인 영역에 컨택패드를 갖는반도체 장치의 형성방법 |
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KR100475084B1 (ko) * | 2002-08-02 | 2005-03-10 | 삼성전자주식회사 | Dram 반도체 소자 및 그 제조방법 |
KR100513719B1 (ko) * | 2002-08-12 | 2005-09-07 | 삼성전자주식회사 | 하프늄 산화막 형성용 전구체 및 상기 전구체를 이용한하프늄 산화막의 형성방법 |
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US5236855A (en) * | 1990-11-06 | 1993-08-17 | Micron Technology, Inc. | Stacked V-cell capacitor using a disposable outer digit line spacer |
US5262343A (en) * | 1991-04-12 | 1993-11-16 | Micron Technology, Inc. | DRAM stacked capacitor fabrication process |
US5327994A (en) * | 1993-08-05 | 1994-07-12 | Smith Michael P | Tree seat |
-
1990
- 1990-05-01 JP JP2115642A patent/JP2524862B2/ja not_active Expired - Fee Related
-
1991
- 1991-03-04 KR KR1019910003474A patent/KR940005889B1/ko not_active IP Right Cessation
- 1991-04-29 DE DE4113932A patent/DE4113932A1/de not_active Ceased
- 1991-04-29 IT ITMI911161A patent/IT1247303B/it active IP Right Grant
-
1994
- 1994-04-25 US US08/232,315 patent/US5486712A/en not_active Expired - Lifetime
-
1995
- 1995-06-01 US US08/456,331 patent/US5659191A/en not_active Expired - Lifetime
- 1995-10-31 US US08/558,584 patent/US5612241A/en not_active Expired - Lifetime
-
1997
- 1997-06-18 US US08/877,800 patent/US5949110A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5659191A (en) | 1997-08-19 |
KR910020904A (ko) | 1991-12-20 |
US5949110A (en) | 1999-09-07 |
US5612241A (en) | 1997-03-18 |
ITMI911161A1 (it) | 1992-10-29 |
JP2524862B2 (ja) | 1996-08-14 |
JPH0412564A (ja) | 1992-01-17 |
KR940005889B1 (ko) | 1994-06-24 |
US5486712A (en) | 1996-01-23 |
DE4113932A1 (de) | 1991-11-14 |
ITMI911161A0 (it) | 1991-04-29 |
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0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
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