IL170511A - Critical dimension variation compensation across a wafer by means of local wafer temperature control - Google Patents

Critical dimension variation compensation across a wafer by means of local wafer temperature control

Info

Publication number
IL170511A
IL170511A IL170511A IL17051105A IL170511A IL 170511 A IL170511 A IL 170511A IL 170511 A IL170511 A IL 170511A IL 17051105 A IL17051105 A IL 17051105A IL 170511 A IL170511 A IL 170511A
Authority
IL
Israel
Prior art keywords
wafer
preset
etching
preset locations
heating
Prior art date
Application number
IL170511A
Other languages
English (en)
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of IL170511A publication Critical patent/IL170511A/en

Links

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D99/00—Subject matter not provided for in other groups of this subclass
    • F27D99/0001—Heating elements or systems
    • F27D99/0006—Electric heating elements or system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27B—FURNACES, KILNS, OVENS OR RETORTS IN GENERAL; OPEN SINTERING OR LIKE APPARATUS
    • F27B17/00—Furnaces of a kind not covered by any of groups F27B1/00 - F27B15/00
    • F27B17/0016—Chamber type furnaces
    • F27B17/0025—Chamber type furnaces specially adapted for treating semiconductor wafers
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27B—FURNACES, KILNS, OVENS OR RETORTS IN GENERAL; OPEN SINTERING OR LIKE APPARATUS
    • F27B5/00—Muffle furnaces; Retort furnaces; Other furnaces in which the charge is held completely isolated
    • F27B5/06—Details, accessories or equipment specially adapted for furnaces of these types
    • F27B5/14—Arrangements of heating devices
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D19/00—Arrangements of controlling devices
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D21/00—Arrangement of monitoring devices; Arrangement of safety devices
    • F27D21/0014—Devices for monitoring temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Control Of Temperature (AREA)
  • Constitution Of High-Frequency Heating (AREA)
IL170511A 2003-02-27 2005-08-25 Critical dimension variation compensation across a wafer by means of local wafer temperature control IL170511A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/376,498 US6770852B1 (en) 2003-02-27 2003-02-27 Critical dimension variation compensation across a wafer by means of local wafer temperature control
PCT/US2004/004134 WO2004077505A2 (en) 2003-02-27 2004-02-12 Critical dimension variation compensation across a wafer by means of local wafer temperature control

Publications (1)

Publication Number Publication Date
IL170511A true IL170511A (en) 2010-04-15

Family

ID=32771493

Family Applications (1)

Application Number Title Priority Date Filing Date
IL170511A IL170511A (en) 2003-02-27 2005-08-25 Critical dimension variation compensation across a wafer by means of local wafer temperature control

Country Status (10)

Country Link
US (1) US6770852B1 (enExample)
EP (1) EP1599891B1 (enExample)
JP (3) JP2006519497A (enExample)
KR (1) KR101047823B1 (enExample)
CN (1) CN1777974B (enExample)
AT (1) ATE480003T1 (enExample)
DE (1) DE602004028910D1 (enExample)
IL (1) IL170511A (enExample)
TW (1) TWI338917B (enExample)
WO (1) WO2004077505A2 (enExample)

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Also Published As

Publication number Publication date
TW200428505A (en) 2004-12-16
TWI338917B (en) 2011-03-11
DE602004028910D1 (de) 2010-10-14
KR20050106457A (ko) 2005-11-09
JP5844757B2 (ja) 2016-01-20
JP2006519497A (ja) 2006-08-24
WO2004077505A3 (en) 2005-03-31
KR101047823B1 (ko) 2011-07-08
CN1777974B (zh) 2011-02-16
EP1599891A2 (en) 2005-11-30
JP2013077859A (ja) 2013-04-25
US6770852B1 (en) 2004-08-03
CN1777974A (zh) 2006-05-24
WO2004077505A2 (en) 2004-09-10
JP2015130539A (ja) 2015-07-16
EP1599891B1 (en) 2010-09-01
ATE480003T1 (de) 2010-09-15

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