WO2004077505A2 - Critical dimension variation compensation across a wafer by means of local wafer temperature control - Google Patents

Critical dimension variation compensation across a wafer by means of local wafer temperature control Download PDF

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Publication number
WO2004077505A2
WO2004077505A2 PCT/US2004/004134 US2004004134W WO2004077505A2 WO 2004077505 A2 WO2004077505 A2 WO 2004077505A2 US 2004004134 W US2004004134 W US 2004004134W WO 2004077505 A2 WO2004077505 A2 WO 2004077505A2
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
etching
preset
locations
measuring device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/004134
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English (en)
French (fr)
Other versions
WO2004077505A3 (en
Inventor
Robert J. Steger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to KR1020057015921A priority Critical patent/KR101047823B1/ko
Priority to AT04710651T priority patent/ATE480003T1/de
Priority to JP2006503525A priority patent/JP2006519497A/ja
Priority to CN2004800096795A priority patent/CN1777974B/zh
Priority to EP04710651A priority patent/EP1599891B1/en
Priority to DE602004028910T priority patent/DE602004028910D1/de
Publication of WO2004077505A2 publication Critical patent/WO2004077505A2/en
Publication of WO2004077505A3 publication Critical patent/WO2004077505A3/en
Priority to IL170511A priority patent/IL170511A/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D99/00—Subject matter not provided for in other groups of this subclass
    • F27D99/0001—Heating elements or systems
    • F27D99/0006—Electric heating elements or system
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27B—FURNACES, KILNS, OVENS OR RETORTS IN GENERAL; OPEN SINTERING OR LIKE APPARATUS
    • F27B17/00—Furnaces of a kind not covered by any of groups F27B1/00 - F27B15/00
    • F27B17/0016—Chamber type furnaces
    • F27B17/0025—Chamber type furnaces specially adapted for treating semiconductor wafers
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27B—FURNACES, KILNS, OVENS OR RETORTS IN GENERAL; OPEN SINTERING OR LIKE APPARATUS
    • F27B5/00—Muffle furnaces; Retort furnaces; Other furnaces in which the charge is held completely isolated
    • F27B5/06—Details, accessories or equipment specially adapted for furnaces of these types
    • F27B5/14—Arrangements of heating devices
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D19/00—Arrangements of controlling devices
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F27—FURNACES; KILNS; OVENS; RETORTS
    • F27D—DETAILS OR ACCESSORIES OF FURNACES, KILNS, OVENS OR RETORTS, IN SO FAR AS THEY ARE OF KINDS OCCURRING IN MORE THAN ONE KIND OF FURNACE
    • F27D21/00—Arrangement of monitoring devices; Arrangement of safety devices
    • F27D21/0014—Devices for monitoring temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring

Definitions

  • the present invention relates to a method and apparatus for varying a temperature profile for a wafer of material undergoing plasma processing in order to compensate for other non-temperature effects that cause dimensional variation of etched features across the substrate during plasma processing.
  • a typical plasma etching apparatus comprises a reactor in which there is a chamber through which reactive gas or gases flow. Within the chamber, the gases are ionized into a plasma, typically by radio frequency energy. The highly reactive ions of the plasma gas are able to react with material, such as a polymer mask on a surface of a semiconductor wafer being processed into integrated circuits (IC's). Prior to etching, the wafer is placed in the chamber and held in proper position by a chuck or holder, which exposes a top surface of the wafer to the plasma. The chuck provides an isothermal surface and serves as a heat sink for the wafer.
  • chucks also sometimes called susceptors
  • a semiconductor wafer is held in place for etching by a mechanical clamp.
  • a semiconductor wafer is held in place by an electrostatic force generated by an electric field disposed between the chuck and the wafer.
  • the present invention is applicable to both these types of chucks.
  • CD's critical dimension features
  • a measurement of these CD's after the photo imaging process can be used to determine the "CD shift" from the lithography operation.
  • a measurement of the CD's in the photoresist can be compared to the etched features that they define after the etching process, and a CD shift can be calculated and attributed to the etch process. It is desirable that these CD shifts be stable from wafer to wafer and uniform over a wafer surface, so that a simple correction bias to the original mask image can be used to compensate out the systematic CD shift.
  • a primary purpose of the present invention is to solve these needs and provide further, related advantages.
  • An etching system for etching a wafer of a material has a measuring device, an etching chamber, and a controller.
  • the measuring device measures the critical dimension test feature (CD) along the profile of the wafer at a plurality of preset locations.
  • the etching chamber receives the wafer from the measuring device.
  • the etching chamber includes a chuck supporting the wafer and a plurality of heating elements disposed within the chuck. Each heating element is positioned adjacent to each preset location on the wafer.
  • the etching system controller is coupled to the measuring device to receive the actual measured CD's for a particular wafer.
  • the etching system controller is also connected to the plurality of heating elements. The controller adjusts the temperature of each heating element during a process to reduce the variation of critical dimensions among the plurality of preset locations by using temperature dependent etching characteristics of the etch process to compensate for CD variation introduced by the lithography process preceding the etch process.
  • FIG. 1 is a schematic diagram illustrating a system for controlling the temperature and etch rate of the wafer under process in accordance with one embodiment of the present invention.
  • FIG. 2 is a graph of an example of the relationship between etch process induced CD shift and wafer temperature in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic diagram illustrating different regions on a chuck in accordance with one embodiment of the present invention.
  • FIG. 4 is a schematic diagram illustrating a system for controlling the temperature and etch rate of the wafer under process in accordance with another embodiment of the present invention.
  • FIG. 5 is a schematic diagram illustrating a system for controlling the temperature and etch rate of the wafer under process in accordance with another embodiment of the present invention.
  • FIG. 6 is a flow diagram illustrating a method for controlling the temperature and etch rate of a wafer under process in accordance with another embodiment of the present invention.
  • this temperature dependant CD shift in the etching process can be used to compensate the photolithographic induced CD shifts in each wafer or lot of wafers to generally improve the final CD's fidelity to the intended dimensions.
  • FIG. 1 illustrates an etching system 100 for controlling the temperature and etch rate of a wafer 104 in accordance with one embodiment of the present invention.
  • An etching system 100 comprises a chamber 102 through which reactive gas or gases flow (not shown). Within the chamber 102, the gases are ionized into a plasma 106, by radio frequency energy generated by an RF antenna (not shown) disposed above and adjacent to a top window (not shown) of the chamber 102. The highly reactive ions of the plasma 106 are able to react with the surface of a semiconductor wafer 104 being processed. Prior to etching, the wafer 104 is placed in the chamber 102 and held in proper position by a chuck 108 that exposes a top surface of the wafer 104 to the plasma 106.
  • the heating elements 110 may include film heaters, or any other type of heaters small enough to fit in the chuck 108. Those of ordinary skills in the art will recognize that there are many other ways to heat the chuck 108. An example of the arrangement of the heating elements 110 is further illustrated below in FIG. 3.
  • the heating elements 110 are coupled to a controller 112 that adjusts the temperature of each heating element 110.
  • a measuring device 114 coupled to the controller 112 measures critical dimension test feature dimensions (CDs) on each wafer prior to processing.
  • Critical Dimensions metrology tools may be used to detect and measure changes in feature profiles.
  • the measuring device 114 may include a spectroscopic CD metrology tool that is based on spectroscopic ellipsometry (SE) which is an optical technique for measuring film thickness and film properties.
  • SE spectroscopic ellipsometry
  • the measuring device 114 may determine the CD (at any point on the profile), line height or trench depth, and sidewall angle from spectroscopic CD measurements on special grating targets.
  • the cross-section profile of a wafer may also be determined.
  • the measuring device 114 sends data containing measurements at several preset locations on the wafer 104 to the controller 112.
  • the locations of the measurements may be chosen according to the number of measurements.
  • the preset locations on the wafer 104 correspond to independent thermal regions on the chuck 108.
  • the controller 112 includes an algorithm containing the relationship between a feature dimension measurement and the temperature of a wafer under process.
  • FIG. 2 is a graph of an example of the relationship between CD shift and wafer temperature. Such relationship may be obtained, for example, from empirical data.
  • the controller 112 receives the data from the measuring device 114, the controller 112 applies the above algorithm to translate the measured data into temperature data. Therefore, the data containing measurements at several locations on the wafer 104 may be used to produce a custom temperature profile for the measured wafer 104.
  • the controller 112 adjusts the temperature of the heating element 110 corresponding to that particular location on the wafer in accordance with the above-defined relationship.
  • the etching system 100 includes a feedforward system in which it dynamically alters in real-time the temperature profile for each wafer after accepting information about the particular feature dimensions on the wafer.
  • the controller 112 adjusts the temperature of each heating element 110 before and/or during the process to reduce the variation of Critical Dimensions on the wafer 104 among the preset locations on the wafer 104.
  • the measuring device 114 measures feature dimensions at preset locations on the wafer 104.
  • the preset locations may be spread over the surface of the wafer 104.
  • Each preset location or a group of preset locations may represent a region on the wafer 104 and the chuck 110.
  • FIG. 3 is a schematic diagram illustrating different regions on a chuck in accordance with one embodiment of the present invention.
  • FIG. 3 illustrates a chuck 300 having seven regions: one central hexagonal region 302 in the center on the chuck 300, six adjacent regions 304 around the central region 302.
  • the regions on the chuck shown are not intended to be limiting and that other configurations of regions or zones can be used without departing from the inventive concepts herein disclosed.
  • Each region on the chuck 300 may correspond to a region on the wafer since the wafer sits on top of the chuck 300.
  • Each region on the chuck 300 may include its own heating element (not shown) and its own controller (not shown) such that the temperature of each region on the chuck 300 may be controlled independently.
  • the measuring device 114 may measure feature dimensions from several preset locations on the wafer 104. Each region may include at least one preset location from which the measuring device 114 measures feature dimensions on the wafer 104. If more than one preset location exists for a region, the measurements from that region are included in a sample average that represents the average measurement from that region.
  • the etching system 100 may function as follows:
  • the measuring device 114 measures feature dimensions on the wafer 104 at preset locations. Each preset location may define a region on the wafer 104.
  • the controller 112 receives data from the measuring device 114 about the wafer 104 containing feature dimensions at preset locations. The controller 112 translates the data into a temperature profile based on known relationship between the feature dimension differences and the temperature of the wafer during processing.
  • the temperature profile includes a specific temperature for each measured preset location on the wafer 104 and thus for each corresponding region on the chuck 110. The controller 112 thus adjusts the temperature of each region by adjusting its corresponding heating element 110.
  • FIG. 4 illustrates an etching system 400 for controlling the temperature and etch rate of a wafer 404.
  • the etching system 400 comprises a chamber 402 through which reactive gas or gases flow (not shown). Within the chamber 402, the gases are ionized into a plasma 406, by radio frequency energy generated by an RF antenna (not shown) disposed above and adjacent to a top window (not shown) of the chamber 402. The highly reactive ions of the plasma 406 are able to react with the surface of a semiconductor wafer 404 being processed. Prior to etching, the wafer 404 is placed in the chamber 402 and held in proper position by a chuck 408 that exposes a top surface of the wafer 404 to the plasma 406.
  • the heating elements 410 may include film heaters, or any other type of heaters small enough to fit in the chuck 408.
  • the heating elements 410 are coupled to a controller 412 that adjusts the temperature of each heating element 410.
  • the interferometer 416 samples the etch depth at several preset locations periodically by means of switch 420 which sequentially directs light from one of the several fiber optics 418 to an interferometer 416. Since the time to acquire a spectrum is less than 0.1 seconds, the wafer can be sampled over e.g. seven sites in less than a second.
  • the controller 412 receives data from the interferometer 416 during processing.
  • the interferometer 416 measures etch depth of the wafer 404 during an etching process.
  • a number of optical fibers 418 aimed at the wafer 404 are positioned on top of the chamber 402.
  • the number of optical fibers 418 corresponds to the number of heating elements 410 in the chuck 408 or to the number of thermal regions in the chuck 408 as illustrated above in FIG. 3.
  • An optical switch 420 relays the information from the fiber optics 18 to the interferometer 416.
  • the optical switch time multiplexes the signals from the wafer 404, region by region, by taking a scan every few milliseconds, for example, 0.1 second.
  • the etching system 400 includes an in-situ feedback system in which it dynamically alters in real-time the temperature profile for each wafer based on the information from the interferometer 416.
  • the controller 412 adjusts the temperature of each heating element 410 before and/or during the process to locally modify the etch rates and thereby to reduce the variation of trench etch depth on the wafer 404 among the preset locations on the wafer 404.
  • FIG. 5 is a schematic diagram illustrating a system for controlling the temperature and etch rate of the wafer in accordance with another embodiment of the present invention.
  • An etching system 500 controls the temperature and etch rate of a wafer 504.
  • the etching system 500 comprises a chamber 502 through which reactive gas or gases flow (not shown). Within the chamber 502, gases are ionized into a plasma 506, by radio frequency energy generated by an RF antenna (not shown) disposed above and adjacent to a top window (not shown) of the chamber 502.
  • the highly reactive ions of the plasma 506 are able to react with the surface of a semiconductor wafer 504 being processed.
  • the wafer 504 Prior to etching, the wafer 504 is placed in the chamber 502 and held in proper position by a chuck 508 that exposes a top surface of the wafer 504 to the plasma 506.
  • the chuck 508 may include several distinct regions through which fluid may flow.
  • the temperature of each region may be adjusted independently by controlling the temperature of the fluid passing through each region with a temperature controller 510.
  • Each region may be arranged to correspond with each preset location on the chuck 508.
  • Each temperature controller 510 is coupled to a controller 512 that adjusts each temperature controller 510.
  • a measuring device 514 coupled to the controller 512 measures critical dimension test feature dimensions (CDs) on each wafer prior to processing.
  • the measuring device 514 sends data containing the measurements at several preset locations on the wafer 504 to the controller 512.
  • the preset locations on the wafer 504 correspond to the different regions on the chuck 508.
  • the controller 512 includes an algorithm containing the relationship between a feature dimension measurement and the temperature of a wafer under process, similar to the relation shown in Figure 2. Once the controller 512 receives the data from the measuring device 514, the controller 512 applies the above algorithm to translate the measured data into temperature data. Therefore, the data containing measurements at several locations on the wafer 504 may be used to produce a custom temperature profile for the measured wafer 504. Thus, for a particular measurement at a particular location on the wafer 504, the controller 512 adjusts the temperature of the heating element 510 corresponding to that particular location on the wafer in accordance with the above-defined relationship.
  • the etching system 500 includes a feedforward system in which it dynamically alters in real-time the temperature profile for each wafer after accepting information about the particular feature dimensions on the wafer.
  • the controller 512 adjusts the temperature of each heating element 510 before and/or during the process to reduce the variation of Critical Dimensions on the wafer 504 among the preset locations on the wafer 504.
  • FIG. 6 illustrates a method for utilizing the etching system of FIG. 1.
  • the measuring device measures critical dimensions or other dimensions at a plurality of locations on a wafer. Each location is associated with a region as discussed above.
  • the controller generates a temperature profile based on the measured critical dimensions on the wafer.
  • the plasma etching system processes the wafer positioned on a chuck that has heating elements corresponding with the plurality of locations on the wafer. During the process, the controller adjusts the temperature of the heating elements based on the generated temperature profile.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Control Of Temperature (AREA)
  • Constitution Of High-Frequency Heating (AREA)
PCT/US2004/004134 2003-02-27 2004-02-12 Critical dimension variation compensation across a wafer by means of local wafer temperature control Ceased WO2004077505A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1020057015921A KR101047823B1 (ko) 2003-02-27 2004-02-12 국부적인 웨이퍼 온도 제어에 의한 웨이퍼에 걸친 임계 치수 변동 보상
AT04710651T ATE480003T1 (de) 2003-02-27 2004-02-12 Kompensation der variation von kritischen dimensionen auf einer waveroberfläche mit hilfe von lokaler temperaturkontrolle
JP2006503525A JP2006519497A (ja) 2003-02-27 2004-02-12 局所的なウェーハの温度調節によるウェーハ全体における微細寸法のばらつき補正
CN2004800096795A CN1777974B (zh) 2003-02-27 2004-02-12 通过局部晶片温度控制对晶片上的临界尺寸变化的补偿
EP04710651A EP1599891B1 (en) 2003-02-27 2004-02-12 Critical dimension variation compensation across a wafer by means of local wafer temperature control
DE602004028910T DE602004028910D1 (de) 2003-02-27 2004-02-12 Nen auf einer waveroberfläche mit hilfe von lokaler temperaturkontrolle
IL170511A IL170511A (en) 2003-02-27 2005-08-25 Critical dimension variation compensation across a wafer by means of local wafer temperature control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/376,498 US6770852B1 (en) 2003-02-27 2003-02-27 Critical dimension variation compensation across a wafer by means of local wafer temperature control
US10/376,498 2003-02-27

Publications (2)

Publication Number Publication Date
WO2004077505A2 true WO2004077505A2 (en) 2004-09-10
WO2004077505A3 WO2004077505A3 (en) 2005-03-31

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PCT/US2004/004134 Ceased WO2004077505A2 (en) 2003-02-27 2004-02-12 Critical dimension variation compensation across a wafer by means of local wafer temperature control

Country Status (10)

Country Link
US (1) US6770852B1 (enExample)
EP (1) EP1599891B1 (enExample)
JP (3) JP2006519497A (enExample)
KR (1) KR101047823B1 (enExample)
CN (1) CN1777974B (enExample)
AT (1) ATE480003T1 (enExample)
DE (1) DE602004028910D1 (enExample)
IL (1) IL170511A (enExample)
TW (1) TWI338917B (enExample)
WO (1) WO2004077505A2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
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WO2006068805A1 (en) * 2004-12-02 2006-06-29 Lam Research Corporation Method and apparatus for controlling spatial temperature distribution
US7274004B2 (en) 2001-04-30 2007-09-25 Lam Research Corporation Method and apparatus for controlling the spatial temperature distribution across the surface of a workpiece support
US10056225B2 (en) 2009-12-15 2018-08-21 Lam Research Corporation Adjusting substrate temperature to improve CD uniformity
EP1697986B1 (en) * 2003-12-24 2020-07-08 Lam Research Corporation Process control method for improved wafer uniformity using integrated or standalone metrology

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873087B1 (en) * 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
SG142150A1 (en) * 2000-07-16 2008-05-28 Univ Texas High-resolution overlay alignment systems for imprint lithography
JP4740518B2 (ja) 2000-07-17 2011-08-03 ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム 転写リソグラフィ・プロセスのための自動液体ディスペンス方法およびシステム
WO2002067055A2 (en) 2000-10-12 2002-08-29 Board Of Regents, The University Of Texas System Template for room temperature, low pressure micro- and nano-imprint lithography
US6964793B2 (en) 2002-05-16 2005-11-15 Board Of Regents, The University Of Texas System Method for fabricating nanoscale patterns in light curable compositions using an electric field
US20050064344A1 (en) * 2003-09-18 2005-03-24 University Of Texas System Board Of Regents Imprint lithography templates having alignment marks
US7037639B2 (en) 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US6926929B2 (en) 2002-07-09 2005-08-09 Molecular Imprints, Inc. System and method for dispensing liquids
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6900881B2 (en) 2002-07-11 2005-05-31 Molecular Imprints, Inc. Step and repeat imprint lithography systems
US7019819B2 (en) * 2002-11-13 2006-03-28 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US6908861B2 (en) * 2002-07-11 2005-06-21 Molecular Imprints, Inc. Method for imprint lithography using an electric field
US6916584B2 (en) 2002-08-01 2005-07-12 Molecular Imprints, Inc. Alignment methods for imprint lithography
US7027156B2 (en) 2002-08-01 2006-04-11 Molecular Imprints, Inc. Scatterometry alignment for imprint lithography
US7070405B2 (en) 2002-08-01 2006-07-04 Molecular Imprints, Inc. Alignment systems for imprint lithography
US7071088B2 (en) 2002-08-23 2006-07-04 Molecular Imprints, Inc. Method for fabricating bulbous-shaped vias
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US6980282B2 (en) * 2002-12-11 2005-12-27 Molecular Imprints, Inc. Method for modulating shapes of substrates
US6871558B2 (en) * 2002-12-12 2005-03-29 Molecular Imprints, Inc. Method for determining characteristics of substrate employing fluid geometries
AU2003300865A1 (en) * 2002-12-13 2004-07-09 Molecular Imprints, Inc. Magnification corrections employing out-of-plane distortions on a substrate
US7452574B2 (en) 2003-02-27 2008-11-18 Molecular Imprints, Inc. Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer
US7122079B2 (en) 2004-02-27 2006-10-17 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7186656B2 (en) * 2004-05-21 2007-03-06 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7150622B2 (en) * 2003-07-09 2006-12-19 Molecular Imprints, Inc. Systems for magnification and distortion correction for imprint lithography processes
US7136150B2 (en) 2003-09-25 2006-11-14 Molecular Imprints, Inc. Imprint lithography template having opaque alignment marks
US8211214B2 (en) 2003-10-02 2012-07-03 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US7090716B2 (en) 2003-10-02 2006-08-15 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7906180B2 (en) 2004-02-27 2011-03-15 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US20050270516A1 (en) * 2004-06-03 2005-12-08 Molecular Imprints, Inc. System for magnification and distortion correction during nano-scale manufacturing
US7785526B2 (en) 2004-07-20 2010-08-31 Molecular Imprints, Inc. Imprint alignment method, system, and template
US7566181B2 (en) * 2004-09-01 2009-07-28 Tokyo Electron Limited Controlling critical dimensions of structures formed on a wafer in semiconductor processing
US7547504B2 (en) 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7252777B2 (en) * 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7205244B2 (en) 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7041604B2 (en) * 2004-09-21 2006-05-09 Molecular Imprints, Inc. Method of patterning surfaces while providing greater control of recess anisotropy
US7241395B2 (en) * 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
US20070231421A1 (en) 2006-04-03 2007-10-04 Molecular Imprints, Inc. Enhanced Multi Channel Alignment
US7630067B2 (en) 2004-11-30 2009-12-08 Molecular Imprints, Inc. Interferometric analysis method for the manufacture of nano-scale devices
US7292326B2 (en) * 2004-11-30 2007-11-06 Molecular Imprints, Inc. Interferometric analysis for the manufacture of nano-scale devices
US8038796B2 (en) 2004-12-30 2011-10-18 Lam Research Corporation Apparatus for spatial and temporal control of temperature on a substrate
US20060222975A1 (en) * 2005-04-02 2006-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated optical metrology and lithographic process track for dynamic critical dimension control
US7851234B2 (en) 2007-11-29 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for enhanced control of copper trench sheet resistance uniformity
KR101365202B1 (ko) 2009-11-02 2014-02-20 엘아이지에이디피 주식회사 화학기상증착장치의 온도제어방법
EP2498277A4 (en) * 2009-11-02 2013-03-20 Lig Adp Co Ltd CVD DEVICE AND TEMPERATURE CONTROL PROCEDURE FOR A CVD DEVICE
US8410393B2 (en) 2010-05-24 2013-04-02 Lam Research Corporation Apparatus and method for temperature control of a semiconductor substrate support
JP5640894B2 (ja) * 2011-05-26 2014-12-17 東京エレクトロン株式会社 温度測定装置、温度測定方法、記憶媒体及び熱処理装置
US8949057B1 (en) 2011-10-27 2015-02-03 Kla-Tencor Corporation Method for compensating for wafer shape measurement variation due to variation of environment temperature
US8852964B2 (en) 2013-02-04 2014-10-07 Lam Research Corporation Controlling CD and CD uniformity with trim time and temperature on a wafer by wafer basis
CN104008957B (zh) * 2013-02-22 2016-10-05 中微半导体设备(上海)有限公司 基片补偿刻蚀的方法
KR20180110213A (ko) * 2013-08-06 2018-10-08 어플라이드 머티어리얼스, 인코포레이티드 국부적으로 가열되는 다-구역 기판 지지부
CN104750140B (zh) * 2013-12-31 2017-09-01 北京北方微电子基地设备工艺研究中心有限责任公司 反应腔加热控制方法及装置
US9378992B2 (en) * 2014-06-27 2016-06-28 Axcelis Technologies, Inc. High throughput heated ion implantation system and method
WO2016014790A1 (en) * 2014-07-23 2016-01-28 Georgia Tech Research Corporation Electrically short antennas with enhanced radiation resistance
WO2016190905A1 (en) * 2015-05-22 2016-12-01 Applied Materials, Inc. Azimuthally tunable multi-zone electrostatic chuck
JP6212092B2 (ja) * 2015-10-02 2017-10-11 東京エレクトロン株式会社 基板処理システム、フォーカスリングの温度制御方法及び基板のエッチング方法
US9466538B1 (en) 2015-11-25 2016-10-11 Globalfoundries Inc. Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
US9966316B2 (en) 2016-05-25 2018-05-08 Toshiba Memory Corporation Deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device
US10522377B2 (en) * 2016-07-01 2019-12-31 Lam Research Corporation System and method for substrate support feed-forward temperature control based on RF power
JP6817168B2 (ja) * 2017-08-25 2021-01-20 東京エレクトロン株式会社 被処理体を処理する方法
KR102487551B1 (ko) * 2017-09-13 2023-01-11 삼성전자주식회사 플라즈마 식각 장치를 이용한 반도체 소자의 제조 방법
JP7066438B2 (ja) 2018-02-13 2022-05-13 東京エレクトロン株式会社 冷却システム
CN109473381A (zh) * 2018-10-31 2019-03-15 上海华力微电子有限公司 湿法刻蚀清洗设备和方法
US11367645B2 (en) 2019-03-13 2022-06-21 Applied Materials, Inc. Temperature tunable multi-zone electrostatic chuck
US11533783B2 (en) * 2019-07-18 2022-12-20 Applied Materials, Inc. Multi-zone heater model-based control in semiconductor manufacturing
CN110752171B (zh) * 2019-11-01 2022-07-29 长江存储科技有限责任公司 晶圆弯曲度调整装置及方法
US20220319818A1 (en) * 2021-03-31 2022-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Laser array system for improved local cd uniformity
CN116153768A (zh) * 2021-11-22 2023-05-23 联华电子股份有限公司 晶片处理方法
JP7724977B2 (ja) 2023-07-10 2025-08-18 株式会社日立ハイテク エッチングシステム及びエッチング方法
WO2025187424A1 (ja) * 2024-03-04 2025-09-12 東京エレクトロン株式会社 基板処理装置

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4518848A (en) 1981-05-15 1985-05-21 Gca Corporation Apparatus for baking resist on semiconductor wafers
US5059770A (en) * 1989-09-19 1991-10-22 Watkins-Johnson Company Multi-zone planar heater assembly and method of operation
JP3238925B2 (ja) 1990-11-17 2001-12-17 株式会社東芝 静電チャック
US6008133A (en) * 1991-04-04 1999-12-28 Hitachi, Ltd. Method and apparatus for dry etching
EP0511448A1 (en) * 1991-04-30 1992-11-04 International Business Machines Corporation Method and apparatus for in-situ and on-line monitoring of a trench formation process
US5200023A (en) * 1991-08-30 1993-04-06 International Business Machines Corp. Infrared thermographic method and apparatus for etch process monitoring and control
US5294778A (en) 1991-09-11 1994-03-15 Lam Research Corporation CVD platen heater system utilizing concentric electric heating elements
JPH07201822A (ja) * 1993-12-28 1995-08-04 Hiroshima Nippon Denki Kk ドライエッチング装置
JPH0845909A (ja) * 1994-07-26 1996-02-16 Sony Corp 試料台
JP3246707B2 (ja) * 1994-07-27 2002-01-15 シャープ株式会社 強誘電体膜のエッチング方法
US5795493A (en) * 1995-05-01 1998-08-18 Motorola, Inc. Laser assisted plasma chemical etching method
US5854468A (en) 1996-01-25 1998-12-29 Brooks Automation, Inc. Substrate heating apparatus with cantilevered lifting arm
JP3537269B2 (ja) 1996-05-21 2004-06-14 アネルバ株式会社 マルチチャンバースパッタリング装置
JP3703918B2 (ja) * 1996-09-20 2005-10-05 株式会社東芝 パターン形成方法
US5846375A (en) * 1996-09-26 1998-12-08 Micron Technology, Inc. Area specific temperature control for electrode plates and chucks used in semiconductor processing equipment
JP3665826B2 (ja) 1997-05-29 2005-06-29 Ｓｍｃ株式会社 基板熱処理装置
JPH1154482A (ja) * 1997-08-05 1999-02-26 Hitachi Ltd 半導体装置の製造方法および装置ならびにワークの処理方法
EP0915499B1 (en) 1997-11-05 2011-03-23 Tokyo Electron Limited Semiconductor wafer holding apparatus
US6046116A (en) * 1997-11-19 2000-04-04 Tegal Corporation Method for minimizing the critical dimension growth of a feature on a semiconductor wafer
JPH11162697A (ja) * 1997-11-28 1999-06-18 Mc Electronics Kk プラズマ生成用の螺旋共振装置
JP3477062B2 (ja) 1997-12-26 2003-12-10 京セラ株式会社 ウエハ加熱装置
US6020262A (en) 1998-03-06 2000-02-01 Siemens Aktiengesellschaft Methods and apparatus for chemical mechanical planarization (CMP) of a semiconductor wafer
US6310755B1 (en) 1999-05-07 2001-10-30 Applied Materials, Inc. Electrostatic chuck having gas cavity and method
US6225639B1 (en) * 1999-08-27 2001-05-01 Agere Systems Guardian Corp. Method of monitoring a patterned transfer process using line width metrology
JP2001093885A (ja) * 1999-09-22 2001-04-06 Olympus Optical Co Ltd エッチング監視装置
US6706541B1 (en) * 1999-10-20 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for controlling wafer uniformity using spatially resolved sensors
JP3774094B2 (ja) * 1999-12-02 2006-05-10 株式会社日立製作所 膜厚、加工深さ測定装置及び成膜加工方法
JP2001203257A (ja) 2000-01-20 2001-07-27 Sumitomo Electric Ind Ltd 半導体製造装置用ウェハ保持体
JP2002048519A (ja) * 2000-08-03 2002-02-15 Toshiba Corp 段差測定方法とその装置、および半導体装置の製造方法
JP3817414B2 (ja) * 2000-08-23 2006-09-06 株式会社日立製作所 試料台ユニットおよびプラズマ処理装置
JP3872304B2 (ja) * 2001-03-07 2007-01-24 株式会社日立製作所 半導体製造装置および半導体製造方法
US6561706B2 (en) * 2001-06-28 2003-05-13 Advanced Micro Devices, Inc. Critical dimension monitoring from latent image
JP3708031B2 (ja) * 2001-06-29 2005-10-19 株式会社日立製作所 プラズマ処理装置および処理方法
WO2004068722A2 (en) * 2003-01-24 2004-08-12 Coco Communications Corp. Method and apparatus for secure communications and resource sharing between anonymous non-trusting parties with no central administration

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7274004B2 (en) 2001-04-30 2007-09-25 Lam Research Corporation Method and apparatus for controlling the spatial temperature distribution across the surface of a workpiece support
US8536494B2 (en) 2001-04-30 2013-09-17 Lam Research Corporation Method and apparatus for controlling the spatial temperature distribution across the surface of a workpiece support
US8921740B2 (en) 2001-04-30 2014-12-30 Lam Research Corporation Method and apparatus for controlling the spatial temperature distribution across the surface of a workpiece support
US8963052B2 (en) 2001-04-30 2015-02-24 Lam Research Corporation Method for controlling spatial temperature distribution across a semiconductor wafer
US9824904B2 (en) 2001-04-30 2017-11-21 Lam Research Corporation Method and apparatus for controlling spatial temperature distribution
EP1697986B1 (en) * 2003-12-24 2020-07-08 Lam Research Corporation Process control method for improved wafer uniformity using integrated or standalone metrology
WO2006068805A1 (en) * 2004-12-02 2006-06-29 Lam Research Corporation Method and apparatus for controlling spatial temperature distribution
US10056225B2 (en) 2009-12-15 2018-08-21 Lam Research Corporation Adjusting substrate temperature to improve CD uniformity

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US6770852B1 (en) 2004-08-03

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