IL146274A0 - Programming and erasing methods for a reference cell of an nrom array - Google Patents

Programming and erasing methods for a reference cell of an nrom array

Info

Publication number
IL146274A0
IL146274A0 IL14627401A IL14627401A IL146274A0 IL 146274 A0 IL146274 A0 IL 146274A0 IL 14627401 A IL14627401 A IL 14627401A IL 14627401 A IL14627401 A IL 14627401A IL 146274 A0 IL146274 A0 IL 146274A0
Authority
IL
Israel
Prior art keywords
programming
reference cell
erasing methods
nrom array
threshold voltage
Prior art date
Application number
IL14627401A
Other languages
English (en)
Original Assignee
Saifun Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/730,586 external-priority patent/US6928001B2/en
Application filed by Saifun Semiconductors Ltd filed Critical Saifun Semiconductors Ltd
Publication of IL146274A0 publication Critical patent/IL146274A0/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
IL14627401A 2000-12-07 2001-11-01 Programming and erasing methods for a reference cell of an nrom array IL146274A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/730,586 US6928001B2 (en) 2000-12-07 2000-12-07 Programming and erasing methods for a non-volatile memory cell
US09/827,596 US6490204B2 (en) 2000-05-04 2001-04-05 Programming and erasing methods for a reference cell of an NROM array

Publications (1)

Publication Number Publication Date
IL146274A0 true IL146274A0 (en) 2002-07-25

Family

ID=27112077

Family Applications (1)

Application Number Title Priority Date Filing Date
IL14627401A IL146274A0 (en) 2000-12-07 2001-11-01 Programming and erasing methods for a reference cell of an nrom array

Country Status (6)

Country Link
US (2) US6490204B2 (de)
EP (1) EP1225596B1 (de)
JP (1) JP2002319289A (de)
AT (1) ATE354167T1 (de)
DE (1) DE60126582D1 (de)
IL (1) IL146274A0 (de)

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US20040027871A1 (en) 2004-02-12
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EP1225596A2 (de) 2002-07-24
ATE354167T1 (de) 2007-03-15
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JP2002319289A (ja) 2002-10-31

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