GB2157489A - A semiconductor integrated circuit memory device - Google Patents

A semiconductor integrated circuit memory device Download PDF

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Publication number
GB2157489A
GB2157489A GB08507524A GB8507524A GB2157489A GB 2157489 A GB2157489 A GB 2157489A GB 08507524 A GB08507524 A GB 08507524A GB 8507524 A GB8507524 A GB 8507524A GB 2157489 A GB2157489 A GB 2157489A
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data
coupled
data line
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GB8507524D0 (en
Inventor
Hiroshi Ishii
Masahiro Ogata
Shinji Shimizu
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Hitachi Microcomputer System Ltd
Hitachi Ltd
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Hitachi Microcomputer System Ltd
Hitachi Ltd
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Priority to JP5428684A priority Critical patent/JPS60201594A/en
Priority to JP5603984A priority patent/JPS60200526A/en
Application filed by Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi Microcomputer System Ltd
Publication of GB8507524D0 publication Critical patent/GB8507524D0/en
Publication of GB2157489A publication Critical patent/GB2157489A/en
Application status is Withdrawn legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • G11C11/5635Erasing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising plural independent storage sites which store independent data
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887Programmable transistors with more than two possible different levels of programmation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/04Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using optical elements using other beam accessed elements, e.g. electron, ion beam

Abstract

In a semiconductor memory device provided with a plurality of memory cells each comprised of an insulated gate field effect transistor having first and second semiconductor regions of a first conductivity type formed separately from one another in a substrate of a second conductivity type, two bits can be stored in each transistor. The threshold voltages of the portions adjacent to the first region and/or the second region are raised by writing data. Since data can be written in at either the first or second regions, two bits can be effectively stored in each insulated gate field effect transistor. The first bit is read out under the state in which the first region serves as the drain and the second region, as the source, and the second bit is read out under the state in which the first region serves as the source and the second region, as the drain. <IMAGE>

Description

SPECIFICATION A semiconductor integrated circuit device The present invention relates to a technique which is effective'when applied to a semiconductor integrated circuit device and, more particularly, to a technique which is especially effective when applied to a semiconductor integrated circuit having a read only memoryfuction (which devicewill be shortly referred to asa "memory IC"), although not necessarilylimitedthereto.

In recent years, there has been a strong tendency for memory ICs such as ROMs (i.e., read only memory) or EPROMs (i.e., erasable and programmable ROM) to be hign lv integrated so asto increase the storage capacity thereof. In such memory ICs,the memory cells are generally each composed of an insulated gate type field effect transistor (which will be hereinafter referred to as a "MISFET"} which can only store data of only 1 (bit). As a result, in orderto increase the storage capacity up to about 1 (Mbit), for example, there is required an ultrafine lithography technique which has a minimum lithography size of less than 1 (calm) in the fabrication process.However, since such ultrafine lithography generally cannot be executed due to the limits of present day photolithography depending upon optical resolving power, and since the so-called short channel effect is induced when an effective channel length comes to about 2 (um), we have found as a result of our investigations that there is presently a limit to the degree of integration possible with conventional MlSFETs, and this makes it highly difficult to effect high integration ofthe memory IC.

It is an object of the present invention to provide an arrangement which is capable of highly increasing the capacity of a memory IC.

Another object ofthe present invention is to provide an arrangement capable of writing a plurality of bits of data into each memory cell composing a memory IC.

A further object ofthe present invention is to provide an arrangementwhich is capable of both writing a plurality of data bits into each memory cell composing a memory IC and holding the data stably within each such memory cell.

The above and other objects and novel features of the present invention will become apparentfrom the following description taken with reference to the accompanying drawings.

A representative example ofthe invention to be disclosed hereinafter will now be briefly described.

Specifically, depending upon whether threshold voltage a M ISFET fo r p rovid ing a memory cell is high orlow atthe side orsides ofthe source and/or drain regions ofthe MISFET, one memory cell can hold a plurality of data bits so that the capacity of the memory IC can be increased to a high value.

Yaddresssignalsaredividedintoafirstgroup consisting of one or a plurality of address signals and a second group consisting of the rest, a plurality of data lines are selected by the second group for memory cell selection, and the condition of the data lines selected bythefirst group is determined. According to this arrangement, read-out and/orwrite-in of a plurality of data in and from one memory cell becomes possible.

Figs. 1 and 2 are schematic sectional views showing the essential portions of a MISFET constructing a memory cell for explaining the principle of the present invention; Figs. 3(A) to 3(D) are schematic sectional views showing the essential portions of a MISFET construct ing the memory cell underdifferentwrite-incondi- tions for explaining the combination of the principles of the present invention to permit storage of two bits of information in one memory cell; Fig. 4 is a schematic block diagram showing a system of the memory IC for operation in conjunction with memory cells such as shown in Figs. 1 to3for explaining the embodiment I ofthe present invention; Fig. 5 is a top plan view showing the essential portion ofthe memory cell array for explaining the embodiment I of the present invention;; Fig. 6 is a sectional view taken along line VI-VI of Fig.

5; Fig. 7 is a top plan view showing the essential portion of the memory cell array for explaining the embodimentil of the present invention; Fig. 8 is a sectional view taken along line VIII-VIII of Fig. 7; Figs. 9 to 13 are sectional views showing the essential portionsofthe memory cell arrayatthe individual fabrication steps for explaining thefabrica tion process ofthe embodiment II ofthe present invention; Fig. 14 is a top plan view showing the essential portion of the memory cell array for explaining the embodiment Ill ofthe present invention; Fig. 15 is a sectional view taken along line XV-XV of Fig. 14;; Figs. 16 and 17 are sectional views showing the essential portions of the memory cell array at the individual fabrication steps for explaining the fabrication process ofthe embodiment III ofthe present invention; Figs. 18 are schematic sectional views showing the essential portions of a MlSFETconstructing a memory cell for explaining the principle ofthe present invention; Figs. 19(A) to 19(D) are schematic sectional views showing the essential portions of a MISFET constructing the memory cell underdifferentwrite-in conditions for explaining the combination of the principles ofthe present invention to permit storage of two bits of information in one memory cell; Fig. 20 is a top plan view showing the essential portion of the memory cell array for explaining the embodiment IV ofthe present invention;; Fig. 21 is a sectional viewtaken along line XXI-XXI of Fig. 20; and Fig. 22 is a schematic block diagram showing a system of the memory IC for operation in conjunction with memory cells such as shown in Figs. 18 to 21 for explaining the embodiment IV ofthe present invention; The present invention will be described in the following in connection with the embodiments thereof.

Embodimentl: First of all, the principle of the present invention will be explained.

Figs. 1 and 2 are schematic sectional views showing essential portions of a MlSFETcomposing a memory cell for explaining the principle ofthe present invention.

In Figs. 1 and 2, reference letters Sub indicate a p-type semiconductor substrate; letter D indicates an n-type drain region; and letter S indicates an n-type source region. Reference letter G indicates a gate electrode which is formed over a semiconductor substrate through a gate insulating film (not shown).

Letters DL indicate a data line which is connected with the drain region, and letters SL indicate a select line which is connected with the source region. Letters dl indicate a depletion layer which is formed to extend from the drain region D and the source region S into the semiconductor substrate Sub, and letters ch indicate a channel region which is formed at the side of the source region S by the gate electrode. Letters e indicate hotcarrierswhich are injected during a write-in operation into the gate insulating film atthe side ofthe drain region D orthe source region S thereby to hold a plurality of data bits in the memory cell in a manner which will hereinafter be described.

Now, the gate electrode G is set at a potential of high level (which will be referred to as an "H level"), and the data line DL is set atthe H level whereas the select line SL is set at a potential of low level (which will be referred to as an "L level") . Then, as shown in Fig. 1, there is established through a writing operation a state in which the hot carriers e- exist in advance ofthe reading operation inside the gate insulating film atthe side ofthe source region S. As a result, a threshold voltage (Vth) of a region to be formed with the channel region ch is raised to a higher value than that which existed before the hot carriers were injected. As a result, the MISFET is not rendered conductive, even if the gate electrode G is atthe H level. Therefore the data line DL is held at the H level.

Next, as shown in Fig. 2, the data line DL and the select line SLare interchanged while the hot carriers e- remain nexttothe left region (which now becomes the drain due to the data line DL). Then,the inside of the gate insulating film atthe side of the source region is in the state having no hot carriers e- existing, and the threshold voltage (Vth) ofthe region to be formed with the channel region ch is not increased from its original level before injection ofthe hot carriers e-. As a result, the MISFET is in an ON state when the gate electrode G is atthe H level so that the data line DL level drops from the H level substantiallytothe level of the select line SL, i.e., the L level.

In otherwords, it is assumed that the state of Fig. 1, in which the data line DL is atthe H level, is a data bit of 1 1 whereas the state of Fig. 2, in which the data line DL is atthe L level, is a data bit of 0. With this arrangement, two bits of data can be held by means of the single memory cell simply by considering one bit with the select and data lines in a first position and considering the other bitwith the select and data lines interchanged.

On the basis of this principle, the write-in and read-out ofthe data in and from the memory cell are shown and tabulated in respect of their combination in Figs. 3(A) to 3(D) and in Table 1, respectively.

TABLE 1 <img class="EMIRef" id="027182486-00020001" />

<tb> Readino <SEP> <SEP> Method <SEP> Data <tb> <SEP> Left <SEP> ! <SEP> Right <SEP> <SEP> <SEP> (A) <SEP> | <SEP> <SEP> (B) <SEP> r <SEP> (C) <SEP> (D) <tb> <SEP> 1 <SEP> <SEP> d <SEP> <tb> <SEP> D <SEP> S <SEP> <SEP> | <SEP> <SEP> 0 <SEP> <SEP> <SEP> l <SEP> 9 <SEP> 1 <SEP> 1 <SEP> <tb> Comb.<SEP> <SEP> Data <SEP> | <SEP> 0,0 <SEP> <SEP> 1,0 <SEP> | <SEP> <SEP> 0,1 <SEP> <SEP> 1,1 <tb> As shown in Figs. 3(A) to 3(D) and tabulated in Table 1, in the MISFET shown in Fig. 3(A), the data line DL is held atthe L level, no matterwhich ofthe n-type semiconductor regions at the right or left side might be made of the drain region D, so that the data 0 and 0 can be read out. In the MlSFETshown in Fig. 3(B) (which corresponds to Figs. 1 and 2), the data line DL is held atthe H level, if the right-hand side is made of the drain region D, and is changed from the H level to the L level, if the left-hand side is made of the drain region D, so that the data 1 and 0 can be read out.In the MISFET shown in Fig. 3(C), the data line DL is changed from the H level to the L level, if the right-hand side is made of the drain region D, and is held atthe H level, if the left-hand side is made ofthe drain region D, so that the data 0 and 1 can be read out. In the MISFET shown in Fig. 3(D), the data line DL is held atthe H level, no matter which of the right-hand side or the left-hand side regions might be madeofthedrain region D,sothatthedata 1 and 1 can be read out.

Next, an emboidment I of the present invention will be described in the following in connection with the specific construction thereof.

Fig. 4 is a schematic block diagram showing a system of the memory IC for explaining the embodimentl ofthe present invention.

In all the figures, incidentally, the units having the samefunctions are indicated atthe same reference characters, and their repeated explanations are omitted.

In Fig. 4, reference numeral 1 indicates a memory array which is composed of a plurality of memory cells, ~QM6 arrayed in the form of a matrix to hold ON16 arrayed in the form of a matrix to hold data. Indicated at numeral 2 is an X-decoderfor selecting a predetermined one of a plurality of word lines WO ~ Wx, which extend in a row direction in the memory cell array 1. (In the following, the direction in which the word lines extend will be called the "row direction".) Numeral 3 indicates aY-decoderfor selecting a predetermined pair of a plurality of data lines Do which extend in a column direction in the memory cell array 1 (In thefollowing, the direction in which the data lines extend will be called the "Column direction".) Each memory cell comprises of MISFET QM, and is disposed so asto correspond to a point of intersection between a word line and a data line. The gate electrode of MISFET QM is connected to a word line Wo ~ Wx, and its source or drain region, to a data line Do~ D3 Symbols Qs1 ~ 057 represent column switches each consisting of MISFET that receives the output of the Y decoder 3 at its gate electrode. Either one of the source and drain regions of MISFET Os is connected to the data line. In order to pair two adjacent data lines, the same output of the Y decoder is applied to the gate electrodes of the column switches to be connected to the adjacent data lines. The data lines having two adjacent data lines are connected to two column switches.

Indicated at numeral 4 is a data line selective switching circuitforswitching one ofthe paired data lines, which has been selected by the Y-decoder 3, into a select line.

The other ofthe source and drain regions of MISFETQs is connected ttthe selective switch 4. The output of the Y decoder3 is also applied to the selective switch 4, whose detail will be described elsewhere.

Numeral 5 indicates an address buffer circuit for assigning the address of the data line or the select line ofthey-decoder3 and the data line selective switching circuit4 in response to address signals Ao to Aj. Whether the wiring connected with the memory cell isto be used as the data line ortheselect line may be determined by one ofthe address signals Aoto Aj, e.g., the most significant digits0. Numeral 6 indicates an address buffer circuit for assigning the address of the word lines of the X-decoder 2 in responseto address signals Aj to An.Numeral 8 indicates a sense amplifierforjudging the minute data 1 and 0 of the selected memory cell to amplify the same. Indicated at numeral 9 is an output buffer circuit which is connected to a terminal I/O, and from which the output data is to be read. Numeral 7 indicates an input buffer circuit which is connected to the terminal I/O, and from which the input data is to be write.

The selective switch 4 comprises of a plurality of units disposed so asto correspond to two column switches connected to the same outputterminal of the Y decoder, an exclusive OR gate EX and an inverter IV1 for inverting the output of the gate EX.

The unit comprises of AND gates G1 and G2, and N-channel MOSFETs Qi -- 04. The output of the inverter IV1 is applied to one of the inputterminals of the gate G1, and the output of the gate EX is applied to one ofthe input terminals ofthe gate G2. The output of theY decoder is applied to the other terminal each ofthe gates 61 and 62.

On the other hand, MOSFETs Q1 and 02 are connected in series with the column switch hand MOSFETs 03 and 04are connected in series with the column switch Qs2. The output ofthe gate G1 is applied to the gate electrodes of MOSFETs Q1 and 03, and the output of the gate 62, to the gate electrodes of MOSFETs Q2 and 04. One ofthe source and drain regions of each of MOSFETs Q1 and 04 is connected to a common sense amplifier 8 orto an input buffer 7.

One of the source and drain regions of each of MOSFETs Q2 and 03 is connected to the ground potential ofthe circuit. The units consisting of the AND gates G3 ~ G6 and N-channel MOSFETs 06 #- #12 are disposed in such a manner as to correspond to the two column switches connected to the same output terminal of the Y decoder, that is, to the paired data line, in the same way as the unit consisting ofthe gates G1 and G2 and MOSFETs Q1 ~ Q4 described above. The AND gates 61 66 G, can be constituted, for example, by conventional NAND gates consisting of four N-channel MOSFETs and an inverterconsisting of two N-channel MOSFETs and receiving the output ofthe NAND gates as its input.The afore-mentioned address signal Ao is applied from the address buffer circuit to one of the inputterminals of the exclusive OR gate EX, and a write enable signal (write control signal) WE is applied to the other input terminal.

Upon receiving the write enable signal WE ,the gate EX produces the inverted signal of the address signal A0 at the time of read-out, and produces as such the address signal Ao atthe time of write-in. The role of the gate EX will be described elsewhere.

On the other hand, the data bits of the memory cell selected are written in and read out again by interchanging the selected data and select lines after the write-in and read-out of the same have once been executed with the originally selected data and select lines to allow for obtaining 2 bits of data from each memory cell, as previously discussed.

Next, the memory cell array will be described in the following in connection with the specific construction thereof.

Fig. 5 is a top plan view showing an essential portion of the memory cell array for explaining the embodiment I ofthe present invention, and Fig. 6 is a sectional viewtaken along lineVI-VI of Fig. 5. In Fig. 5, incidentally, the insulating films formed between the individual conductive layers are omitted so that the figure may be seen clearly.

In Figs. 5 and 6, reference numeral 9 indicates a p--type semiconductor substrate which is made of a single crystal silicon for constructing the memory IC.

Indicated at numeral 10 is a field insulating film over the main surface of the semiconductorsubstrate 9 between regions, which are to be formed with the semiconductor element, so as to isolate the same electrically. Indicated at numeral 11 is an insulating film which is formed on the main surface of the semiconductor substrate 9 in the reg ions, which are to be formed with the semiconductor element, thereby to construct mainly the gate insulating film of the MISFET. The hot carriers can be injected into the insulating film 11 atthesideorsidesofthesource region S and/orthe drain region D ofthe MISFET.

Numeral 12 indicates a conductive layer which is formed on a predetermined portion of the insulating film 11 thereby to construct the gate electrode of the MISFET. Indicated at numeral 13 is a conducting layer which is connected electrically with the conducting layer 12 located in the vicinity thereto in the row direction and which is formed over the field insulating film 10 thereby to construct word lines WL. Indicated at numeral l4aren±typesemiconductorregions which are formed in the main surface of the semiconductor substrate 9 across the insulating film 11 at both sides of the conductive layer 12 and which are used asthesource region S orthe drain region D thereby to constructthe MISFET. Thus, the MISFET constructing the memory cell is composed mainly of the semiconductor substrate 9, the insulating film 11, the conducting layer 12 and the paired semiconductor regions 14. Indicated at numeral 15 are insulating films which are formed to coverthe semiconductor elementtherebyto effect electrical isolation from conducting layers to be formed thereabove. Indicated atnumeral 16 are connecting holeswhich are formed by selectively removing the insulating films 11 and 15 over predetermined portions of the semiconductor regions 14.Indicated at numeral 17 are conductive layers which are connected electrically with the semiconductor regions 14th rough the connecting holes 16 and which are formed to extend in the column direction over the insulating films 15 and which are used as the data lines DL orthe select lines SL.

Next, the specific operations ofthe present embodiments will be described briefly with reference to Figs. 4to 6.

First of all, the operation forwriting data 1 and 1 into the memory cell ofthe M ISFET will be described.

During the operation for writing, the input impedance and output impedance of the output buffer circuit 9 and the sense amplifier8 are raised extremely high by the write enable signal WE, for example. As a result, these circuits 8 and 9 are cut off from the other circuit portions. The data that is applied to the input/outputterminai I/O and is to be written into the memory cell is applied to the input beffercircuit7.

During the operation forwriting, a write-in voltage Vpp (e.g., about 12 volts, although a voltage as high as 17 to 20 volts could be used) is supplied to the input buffer circuit. The input buffer circuit 7 produces the write-in voltage Vpp when the data is at the H level (typically the power supply voltage Vcc level of 5 volts), and produces as such the L level when the data is atthe L level (typically about the ground potential Vss level of 0 volts). The outputvoltageofthe input buffer circuit 7 is supplied to the selective switch 4.

The write enablesignal WE is atthe L level during the operation for writing. When the L level signal WE is applied to one of the input terminals of the gate EX, the gate EX produces as such the address signal Ao that is applied thereto during the operation for writing.

The (X) address signals Alto An are applied to the address buffer circuit 6, and the H level (e.g.1 aztut 5 (V)) is applied to the word lineWL0 (i.e., the conducting layer 13),which is selected bythe x-decoder 2, so that the MISFET connected with said word lineWL0 is turned on.

While one data line such as Woo, for example, is keptfixed atthe H level, the function and potentials of the data lines Do through D3 are sequentially set as tabulated in Table 2 below.

TABLE 2 <img class="EMIRef" id="027182486-00040001" />

<tb> <SEP> cycle <tb> <SEP> 1 <SEP> 2 <SEP> 3 <SEP> 4 <SEP> 5(1) <SEP> 6(2) <tb> <SEP> Dg <SEP> DL <SEP> SL <tb> <SEP> D1 <SEP> SL <SEP> DL <SEP> SL <SEP> DL <tb> <SEP> D2 <SEP> DL <SEP> SL <SEP> DL <SEP> SL <tb> <SEP> D3 <SEP> SL <SEP> DL <tb> C <tb> current <SEP> f,# <SEP> J}tQni <SEP> S <SEP> S <SEP> A <tb> direction <SEP> 5515 < 5I' <SEP> - <SEP> - <tb> <SEP> S <SEP> S <tb> Among theY address signals A0 th rough A applied to the address buffer circuit, one address signal, e.g., the most significant digitAo, is applied to the selective switch 4whilethe rest A1 through Ai are applied to the Ydecoder3.

In orderto select one paired data line, e.g., Do and D1, the Y decoder 3 applies the H level signal to the gate electrodes of MOSFETs Qs1 and 0s2 and the L level signals to the other MOSFETs Qs3 through Q57 on the basis of the address signals A1 through Aj. As a result, MOSFETs Qs1 and Qs2 become conductive, thereby connecting the data lines Do and D1 to the selective switch 4. On the other hand, MOSFETs Qs3 through Q57 become non-conductive, and the other data lines D2 and D3 are cut offfrom the selective switch 4. Let's consider the selective switch 4.Due to the outputoftheYdecoder3 described above, the H level is applied to one ofthe input terminals of each of the gates G1 and 62, and the L level is applied to one of the inputterminals of each of the gates 63 th rough Gs As a result, the gates 63 through G6 produced the L level even though either of the H and L levels is applied to the other inputterminals. In consequence, MOSFETs Q5through Q12 become non-conductive.

On the other hand, the L level address signal Ao and the H level inverted address signal A0 inverted by the inverter IV1 are applied to the other input terminals of the gates 6Q!E1/4ĂND G1.As a result, the gates G and G2 produce the H and L levels, respectively.

Therefore, MOSFETs Q1 and Q3 become conductive, while MOSFETs Q2 and Q4 become non-conductive.

The data line Do is connected to the input buffer circuit7through MOSFET5Qsi and 01 duetothe operations of the Y decoder 3 and selective switch 4 described above, and the data line D1 is connected to the ground potential of the circuit through MOSFETs 0s2 and 03. As a result, MISFET QM1 as one memory cell is selected. Then, the data line Do becomes adata line DL connected to the drain region D of MOSFET QM1 (i.e., the semiconductor region 14; this also holds true of Table 2 and so on). The data line D1 becomes a data line SL connected to the source region S of MISFET QMt (i.e, semiconductor region 14; this also holds true of Table 2 and so on).

The write-in voltage Vpp is delivered from the input buffer circuit 7 to the data line DL (Do) in response to the write-in data (H level). As a result, the hot carriers e- are injected into the insulating film 11 at the side of the drain region D, and the data 1 is thus written into the memory cell QM1- ln the manner described above, thefirstcycle of the operationforwriting shown in Table 2 is completed.

Incidentally, when the data 0 is written, the L level is delivered from the input buffer circuit7 to the data line DL (Do) in response to the write-in data 0 (L level).

Therefore, the data 0 is written because the hot carriers e- are not injected into the insulating film 11.

Next, other one-bit data forthe same memory cell (0M1) is written. This means that the second cycle shown in Table 2 is carried out.

Firstofall,a newYaddresssignal istaken into the address buffer circuit 5. In practice, since the same memory cell QM1 is selected, the Y address signals A1 through A are the same as those in the cycle 1. Since the functions ofthe data lines Do and D1 are interchanged,the address signal Ao changes from the L level tothe H leveI#Thernforn,the data line Do is connected to the ground potential of the circuit through MOSFETs Qs1 and Q2 and becomes the data line SL. The data line D1 is connected to the input buffercircuit7 through MOSFETsQ2and 04 and becomes the data line DL.The write-in voltage Vpp is delivered from the input buffer ci rcuit 7 to the data line DL (D1) in responseto the write-in data 1 (H level), and hence the other data 1 is written into the memory cell QM1- In the manner described above, the write-in operation ofthe data bits 1 and 1 to one memory cell is completed.

In the practical operation forwriting, it is better to scan the Y address while one word line such as WL0, for example, kept fixed at the H level. In otherwords, it is betterto sequentially carry out the procedures of the third cycle and so forth shown in Table 2. While the column switches Q53 and as4 are selected by theY decoder 3, the address signal A0 is set to the H level to carry out the third cycle, and the address signal Ao is then set to the L level to carry outthefourth cycle.As shown in Table 2, thefifth and sixth cycles have the same patterns as those ofthe first and second cycles, and the seventh and eighth cycles have the same patterns as the third and fourth cycles, though they are not shown in Table 2. In otherwords, the same pattern appears in every four cycles. After scanning of all the Yaddresses is completed forthe word line Woo, the procedures are repeated sequentially up to theword lines,.

Next, the operations of reading out the data 1 and 1 ofthe MISFET for providing the memory cell will be described inthefollowing.

During the operation of reading, the input and output impedance ofthe input buffer circuit7 are raised by the write enable signal WE, for example, and are cut off from the other circuits. During this period, the signal WE is at the H level, and hence the gate EX produces an inverted signal Ao obtained by inverting the input signal Ao applied thereto.

Now, the case in which the data bits 1 and 1 written into the memory cell 0M1 is read out will be described.

In orderto read out the data written during the cycle 1 of Table 2, the same address signals AOthrough An as those in the cycle 1 are applied. In the same way as in the cycle 1, the word line WL0 is selected (is raised to the H level) by the X decoder 2, and the paired data lines Do and D1 are selected by the Y decoder 3. (The H level is applied to the gate electrodes of the column switches 0s1 and Qs2.) The L level address signal Ao which is the same as when the cycle 1 is carried out is turned into the inverted signal 0,that is, H level and is produced from the gate EX. The output of the gate G1 falls to the L level and the output ofthe gate G2 rises to the H level.Therefore, the data line Do is connected to the ground potential ofthe circuitthrough MOSFETs 0s1 and Qs2 The data line D1 is connected to the sense amplifier 8 and to the output buffer circuit 9 through MOSFETs 0s1 and 04. In other words, the relation between the data lines Do and D1 is opposite to the relation when the data is written in the cycle 1.

Here, it is to be noted that the data written in the cycle 1 can not be read out if the relation betweeen the data lines Do and D1 is the same as the relation in the cycle 1. It will be assumed, for example, that the cycle 1 is carried out underthe state shown in Fig. 2 and the hot carrier e- is injected to the left semiconductor region of Fig. 2. In this writing operation, the left semicon ductor region is the drain region D (to be connected to the data line Do) and the right semiconductor region is the source region S (to be connected to the data line D1). Next, when the read-out operation is carried out underthe same condition, the written hot carrier e does not exist on the channel region (inverted layer) CH (the state shown in Fig. 2).Therefore, the threshold voltage of the region, in which the channel region is to be formed, does not rise. As a result, the overall threshold voltage (Vth) of MISFET 0M1 hardly rises. If the H level is applied to the word line WL0 underthis state, MISFET Ohn, becomes conductive, and the potential of the data line Do drops to the potential of the data line D1, that is, the ground potential ofthe circuit. Sincethiscorrespondstothe state of the data bit 0, the data 0 is written although the data 1 is written into the address described above.

In contast, if the data, which is written by carrying out the write-in cycle 1 underthe state shown in Fig. 2, is read out under the state shown in Fig. 1, the data 1 is read out. That is, in Fig. 1,the left semiconductor region connected to the data line Do is the source I region S, and the right semiconductor region con nected to the data line D1 is the drain region. Under this state, since the written hot carrier e- exists on the channel region CH, the threshold voltage at this portion becomes high, so that MISFET QM1 does not become conductive even if the word line WL0 is raised to the H level, and the data line D1 holds the original level (H level).

The data bit written using the data line Do as DL and the data line D1 as SLmust be readoutwhile changing the data line Do to SL and the data line D1 to DL. Since read-out and write-in must be made by the same address signal,the gate EX is provided.

For the reason described above, the data 1 written into the memory cell QM1 in the cycle 1 is read out by setting the word line WLOtothe H level, the data line Doto SL and the data line D1 to DL. The data line D1 is pre-charged to the H level, orthe H level is supplied thereto from the sense amplifier 8. Since the data written in the cycle 1 is 1, MISFET QM1 is not conductive and the data line D1 keeps the H level.

Incidentally, if written data is O, MISFET ON11 becomes conductive, and the potential of the data line D1 drops to the L level. The potential of the data line D1 (DL) is sensed bythe sense amplifier8, and is delivered to the output buffer circuit 9.

Next, the address signal after the cycle 2 is carried out is taken, and the other data bit 1 written into MISFET Ohnl is read out in the same way as described above.

It should be noted at this pointthatthe present invention can operate as an EPROM or an EEPROM (electricallyerasableand programmable ROM).To this end, information written into the insulating film in the manner described previoiusly can be erased by suchtechneques as using ultraviolet rays or electric signals. When either of these methods is used, it is convenientto erase all the bits altogether. The ultraviolet rays may be radiated to the chip as a whole in the same wayyy as EPROM. When the electrical erasing method is employed, the semiconductor substrate 9 is kept at the Vpp potential, for example, and all the word lines are kept atthe ground potential ofthe circuit.

As has been described hereinbefore, according to the present invention, the data of 2 (bits) can be held in the signal MISFET by injecting the hot carriers into the gate insulating film atthe side or sides of the source region and/orthe drain region of the MISFET constructing the memory cell of the memory IC and by writing the data by mutually inerchanging the data lines and the select lines. Since the data of 2 (bits) can be held bythe single MISFET, moreover, the capacity ofthe memory IC can be increased to a remarkable value.

Embodiment!!: Next, an embodiment II of the present invention will be described in the following in connection with the specific construction thereof.

The present embodiment and a later-described embodiment III are presented for holding stably the hot carriers which are injected into the gate insulating film atthe side or sides of the source region and/orthe drain region ofthe MISFET.

Fig. 7 is a top plan view showing an essential portion of a memory cell array for explaining the embodiment II ofthe present invention, and Fig. 8 is a sectional viewtaken along line VIII-VIII of Fig. 7. In Fig.

7, incidentally, the insulating films to be formed between the individual conducting layers are omitted so that the same figure may be seen clearly.

In Figs. 7 and 8, reference numeral 18 indicates an insulating film which is formed overthe insulating film 11 atthe central portion between the semiconductor region 14 (i.e., between the source region S and the drain region D) thereby to hold the hot carriers e- to be injected stably in the gate insulating film atthe side or sides ofthe source region and/or the drain region D ofthe MISFET. More specifically, the thickness of the central portion ofthe insulating film 11 betweenthe semiconductor regions 14 is substantially increased by the insulating film 18 to prevent the occurrence of ,. soft error which can be induced as a result ofthe hot carriers e- injected into the source region S being caused to migrate to the drain region D by external circumstances, for example.Indicated at numeral 19 is an insulating film which is formed over both the insulating film 11 for providing the gate insulating film 18 thereby to provide the gate insulating film. The gate insulating film ofthe MISFET is composed ofthe insulating films 11, t8and 19,and the hot carriers e- are held in the intervening portion between the insulating film 11 and the insulating film 19.

Next, the specific process for fabricating the presentembodimentwill be described in the following.

Figs. 9 to 13 are sectional views showing the essential portion ofthe memory cell arrayatindividual fabrication steps for explaining the fabrication method of the embodiment li of the present invention.

First of all, thep-type semiconductor substrate 9 is prepared. After the field insulating film 10 has been formed, moreover, the insulating film 11 is formed.

This insulating film 11 may be made of a silicon oxide film prepared by thermal oxidation, for example, to have a thickness of about 150 to 250(A). Next, in order to form the insulating film 18, a polycrystalline silicone film 20 is formed and is patterend by using a photoresistfilm 21 as an etching-resisting mask such that its end portion is positioned atthe middle portion between the source region Sand the drain region D, as shown in Fig. 9.

After the step shown in Fig. 9, an insulating film 1 8A is formed all overthe surface, as shown in Fig. 10. The insulating film 1 8A may be made of a silicon oxide film prepared ata high temperature and under a low pressure, for example, to have a thickness of about 0.3 to 0.6 (pom).

Afterthe step shown in Fig. 10, the whole surface is etched anisotropicallyto form the insulating film 18 in self-alignment at the end portion ofthe polycrystalline silicon film 20. As shown in Fig.11, moreover, all ofthe polycrystalline silicon film 20 is removed atthis time. The insulating film 18 may be formed to have a thickness of about 0.3 to 0.6 (pom) and a width of about 0.1 to 0.2 (pom).

After the step shown in Fig. 11, the whole surface is covered with such an insulating film as can provide the gate insulating film. The insulating film may be made of a silicon nitridefllm prepared by chemical vapor deposition (which will be abbreviated as "CVD"), for example, to have a thickness of about 1,000 to 2,0QQ ( ). Moreover, the whole surface is covered with such a conductive layer as can provide the word I i nes WL and the gate electrode.

The conductive layer may be made of a polycrystalline silicon film prepared bythe CVD, for example, to have a thickness of about 2,000 to 3,000 (A). After that, as shown in Fig. 12, the insulating films and the conductive layers are patterned selectively to form the insulating film 19, the conductive layer 12 and the conductive layer 13, which is not shown.Incidentally, the conductive layers 12 and 13 should not be limited to the polycrystalline silicon film but may be either made of a metal layer having a high melting point such as molybdenum or tungsten ora layerofa silicide, i.e., the compound of the high-melting point metal and silicon, or constructed to a two-layered construction of the polycrystalline silicon film and the silicide Iayerofthe metal of high melting point.

After the step shown in Fig. 12, the n±type semiconductor regions 14 are formed in the main surface of the semiconductor substrate 9 across the insulating film 11, as shown in Fig. 13, by using the conductive layer 12 as a mask for introducing the resisting impurity. The semiconductor regions 14 may be formed by ion implantation, for example.

Afterthestepshown in Fig. 13, the insulating film 15, the connecting holes 16 and the conductive layer 17 areformed, as shown in Fig. 8. The insulatingfilm 15 may be made of a phosphosilicate glass film, for example, and the conductive layer 17 may be made of an aluminum film, for example. The memory IC ofthe present embodiment is completed bythe series fabrication steps thus far described.

Afterthat, incidentally, the memory IC may be covered with a protective film.

Moreover, a conducting layer made of aluminum, for example, may be formed overthe conducting layer 17 across the insulating film and connected electrically with the conductive layer 13 to extend in the same direction therebyto reducethe resistance of the conductive layer 13.

As has been described hereinbefore, according to the present embodiment, effects similartothose of the foregoing embodiment I can be attained.

Thanks to the provision of the thick insulating film 18 at the middle portion between the source region and the drain region of embodiment II, moreover, the hot carriers injected can be held more stably in the gate insulating film atthe side or sides ofthe source drain region and/orthe drain region ofthe MISFET.

Embodiment!!!: Next, an embodiment Ill of the present invention will be described in thefollowing in connection with the specific construction thereof.

Fig. is a top plan view showing an essential portion of a memory cell array for explaining the embodiment III of the present invention, and Fig. 15 is a sectional viewtaken along line XV-XV of Fig. 14. In Fig. 14, incidentally, the insulating films to be formed between the individual conductive layers are omitted so that the same figure maybe seen clearly.

In Figs. 14 and 15, reference character 1 2A indicates conductive layers which are formed in self-alignment overthe insulating film 11 at both the sides of and relative to the insulating film 18 thereby provide floating gate electrodesforthe MISFET. Indicated at numeral 22 is an insulating film which is an insulating film which is formed to cover the conductive layer 1 2Athereby to provide an inter-layer insulating film between the floating gate electrodes and control gate electrodes. Indicated at characters 12B is a conduc tive layer which is formed to coverthe insulating film 22 thereby to provide the control gate electrode of the MISFET.Indicated at characters 13A is a conducting layer which is connected electrically with the conductive layer 12B in the vicinity thereof in the row directionandformedoverthefield insulating film 10 therebyto provide the word linesWL.

Next, the specific fabrication process ofthe present embodiment will be described in the following.

Figs. 16 and 17 a re sectional views showing essential portions ofthe memory cell arrayatthe individual fabrication steps for explaining the fabrica- tion process of the embodiment Ill ofthe present invention.

First of all, afterthefield insulating film 10 has been formed over the main surface ofthe semiconductor substrate 9, an insulating film having a thickness of about 0.3 to 0.6 (ism) is formed. By the photolithography and the anisotropic etching, moreover, the insulating film is patterned to form the insulating film 18 at the middle portion between the source region S and the drain region D.Afterthat,asshown in Fig.16, the insulating film 11 is formed over the main surface of the semiconductor substrate 9 other than the insulating film 18 by the thermal oxidation.

After the step shown in Fig.16, the conductive layers 12A are formed, as shown in Fig. 17. The conductive layers 12A may be made of a polycrystal line silicon film, for example, by the technique which is similarto that used atthe step offorming the insulating film 18 in the foregoing embodiment II.

After the step shown in Fig. 17, the insulating films 12A are formed by the thermal oxidation, and the conductive layer 12B and the conductive layer 13A are formed thereover. By the step sihilarto that of the foregoing embodiment II, moreover, the memory IC ofthe present embodiment is completed, as shown in Fig. 15.

As has been described hereinbefore, according to the present embodiment Ill, effects similarto those of the foregoing embodiments land II can be attained.

EmbodimentlV: The present invention can be applied not only to an erasable ROM but also to a non-erasable ROM, that is, a mask ROM. The principle when the present invention is applied to the mask ROM will be described with reference to Fig. 18.

Fig. l8showsthestructureofan N-channel MOSFET. N±type regions 14a and 14bthatareto serve as the source or drain are shown disposed on the main surface of a Fe#type semiconductor subs- trate 9 on both sides of a gate electrode 12 that is formed on the main surface ofthe substrate 9 via a gate oxide film 11. A P±type region 30 having the same conductivity type as that ofthe substrate 9 but having a higherconcentration is formed in advance by ion implantation orthe like around the N±type region 14b on the right of the gate electrode 12 before the N'-type region 14b is formed. The N'-type region 14b is then formed inside this P±type region 30, thereby forming a double structure.

In the MOSFETstructure described above, the left N'-type region 14a, for example, is connected to the L level (the ground potential ofthe circuit) and the H level is applied to the right N±type region 14b (hereinafter, the H level will be referred to as the "drain voltage"). In otherwords, a case in which the N±type regions 14a and 14b are used as the source and drain regions, respectively, will be considered.

The drain voltage expands the depletion layer at the boundary portion between the N'-type region 14b and the P'-type region 30. In this case, the depletion layer can be arranged to expand outside the P±type region 30 as represented by dotted line A in the drawing by suitably setting the drain voltage and the impurity concentration ofthe P±type region 30.

Underthis state, when the H level is applied tothe gate electrode 12 (hereinafter, this will be referred to as the "gate voltage"), a depletion layer is formed below the gate oxide film. At this time, the direction of the field inside the gate oxide film 11 is opposite on the drain side and the source side duetothe influence ofthe drain voltage, so that an inversion layer CH is formed on the source side ofthe channel and extends towards the drain side. When the inversion layer reaches the depletion layer on the drain side, the electrons flowing through the inversion layer pass through the depletion layer and reach the drain region 14b, thus causing the drain current to flow.

On the other hand, in the MOSFETstructure shown in Fig. 18, it will be assumed that the right N±type region 14b is connected to the ground potential and the drain voltage is applied to the left N±type region 14a, that is, the N ±type regions 14a and 14b are used as the drain and source, respectively. Then, the expansion of the depletion layer becomes greater in the N±type region 14a asthedrainthan in Fig. 18, but the width ofthe depletion layer becomes smaller in the N±type region 14b as the source in which the inversion layer is formed, and becomes more inward than the boundary between the P±type region 30 and the substrate 9.

Therefore, it becomes difficult for the inversion layerto beformed inthechannel portion which comes into contact with the gate oxide film 11 of the P±type region 30. In otherwords,the gate threshold voltage becomes higherwhenthe leftN±type region 14b is used as the source than when the N±type region 14b is used as the drain, as shown in Fig. 18.

As a result, in the MOSFET having the structure shown in Fig. 18,thethresholdvoltagecomesto possess directivity. As a result of experiments, the inventors ofthe present invention confirmed that the threshold voltages vary depending upon the direc tion in the MOSFETs having the structure shown in Fig. 18.

If MOSFETs having four kinds of structures such as shown in Fig. 19 (A) through (D) are constituted as the memory cells using the MOSFETstructure of Fig. 18 which can be constituted in such a mannerthatthe threshold voltage can have the directivity as de scribed above, two data can be stored in one memory cell.

The memory cell having the same structure as in the prior art cell such as shown in Fig. 19 (A) exhibits a low threshold voltage in both directions when both of the N+4ype regions 14a and 14b are used as the source or drain, and the data that becomes "0" and "0" of a binary signal can be stored.

If the right N±type region 14b has a double structure in which the P±type region 30 is formed around the N±type region 14b as shown in Fig. 19 (B),thethresholdvoltage is lowwhen the N±type region 14b is used as the drain as described above, but becomes high when itis used as the source.

Therefore, the memory cell shown in Fig. 19 (B) stores the data "0" and "1" in accordance with the read-out direction.

Similarly, if the left N±type region 14a has a double structure in which the P±type region 30 is formed around the N±type region, the threshold voltage is low when the N'-type region 14a is used as the drain, and becomes high when it is used as the source.

Therefore, the memory cell shown in Fig. (C) stores the data "1" and "0" in accordance with the read-out direction.

Furthermore, if the P'-type regions 30 are formed around the right and left N'-type regions 14b andl4a, respectively, as shown in Fig. (D), the threshold voltage is high even when eitherofthese regions is used as the drain region, so that they can not turn on at the selection level of a suitable word line.

Therefore, the data "I" and "1 " forthe two read-out direction is stored in the memory cell.

Forthe reasons described above, the memory capacity of the memory such as shown in Fig. 1 can be easily increased about twice without increasing the occupation area ofthe memory array in the memory by use ofthe MOSFETs having the directivity as described above.

Next, the memory cell array will be described in the following in connection with the specific construction thereof.

Fig. 20 is a top plan view showing an essential portion ofthe memory cell arrayfor explaining the embodiment I of the present invention, and Fig. 21 is a sectional viewtaken along line XXl-XXl of Fig. 20. In Fig. 20 incidentally, the insulating films formed between the individual conductive layers are omitted so thatthe figure may be seen clearly.

In Figs. 20 and 21, like reference numerals are used to identify like portions as in Figs. and 6, and the explanation of such portions will be omitted.

A P±type region 30 is formed on a P--type semiconductor substrate 9 to write in the data 1. The area ofthe P±type region 30 is reduced as much as possible in orderto prevent any adverse influences upon the threshold values of three MISFETs among four MISFETs sharing an N±type region 14. The P±type region 30 can be formed, for example, by implanting boron ions as a P-type impurity before or afterthe N±type region 14isformed.

When the present invention is applied to the mask ROM, the data write-in operation becomes unneces sary, and hence the complicated circuit such as shown in Fig. 4 is not necessary. In otherwords, it is not necessary that the paired data line is selected by the decoder and the function of the selected data line is interchanged between the read-out operation and the write-in operation. This eliminates the necessity of the gate EX, and the function of selecting the paired data line becomes also unnecessary.

As a mask ROM circuit shown in Figs. 20 and 21, it is possible to obtain such a circuit by deleting the gate EX in Fig .4 and then applying directly the address signal Ao from the address buffer circuit 5 to the inverter lV1 and to the AND gates 62,64 and 66.

Needless to say, the input buffer circuit7 is not necessary.

It is also possible to use a circuit shown in Fig. 22. In Fig.22, symbols 013 through Q22 represent N-channel MOSFETs, symbol 67through G11 are AND gates, symbols 612 through G14 are OR gates, and a symbol lV2 is an inverter. Symbols Through D4 represent the data lines, CD is a common data line and symbols C0 through C4 are output lines of the Y decoder 3. Next, the read-out operation ofthe data written into the memory cell 0M1 in Fig. 22 will be described.

The Y decoder3 sets only the output line C0 to the H level and the other output lines C1 ~ C4 -- Cn to the L level or the basis ofthe address signals A1 ~ Ai. a result, since MOSFETQ13 becomes conductive, the data line Do is connected to the common data line CD, and since MOSFETs Q14through 017 become nonconductive,the data lines D1 through D4ar cut off from the common data line CD. Among the gates 612 through G16, itis onlythegate G15 to which the H level is applied. Therefore, the gate G15 produces the H level, and the rest G12 ~ G14 and G16 produce the L level.Sincethegates 67,69 G11 produce the L level irrespective of the level of the address signal Ao, MOSFETs 018 and Q20 ~ Q22 become non-conductive.

The L level is applied as the address signal Ao and is inverted bythe inverter lV2, and the H level is applied to one oftheterminalsofthe gate 68. In consequence, since the gate 6aproducesthe H level, MOSFET 019 becomes it euctive and the data line D1 is set to the ground potential ofthecircuit.

The sense amplifier8 detects whether or not the potential of the data line Do, which is pre-charged to the H level, drops by setting the word line Woto the H level.

Next, in orderto read outthe other one bit data written into the memory cell QM1, onlythe output line C1 is raised to the H level by new address signals A1 through Aj with the other output lines being set to the L level. As a result, since MOSFET 014 becomes conductive, the date line D1 is connected to the common data line CD, and since MOSFETs Q 3 and 015 through Q17 become non-conductive, the data lines Do, D2 D4 are cutofffrom the common data line CD. It is only the gates 612 and 613 to which the H level is applied among the gates 612through 616.

Therefore, these gates 612 and 613 produce the H level, while the rest produce the L level. Since the gates Gs, G10 and 611 produce the L level irrespective ofthe level of the address signal Ao, MOSFETs 019, Q21 and 022 become non-conductive. As a result, the data lines D3 and D4 attain the floating state. Since the H level is applied as the address signal A0, the H level is applied to the gate 67 while the L level inverted by the inverter IV2 is applied to the gate G9.In consequence, the gate G7 produces the H level, thereby rendering MOSFET Q18 conductive and setting the data line Do to the ground potential of the circuit. On the other hand, since the gate Gg produces the L level, MOSFET Q20 becomes non-conductive and the data line D2 attains the floating state.

The sense amplifier 8 detects whether or not the potential ofthe data line D1, which is pre-charged to the H level, drops by setting the word line W0 to the H level.

Next, new address signals Ao ~ A1 are applied in orderto read out the data written into the memory cell OM2.This address signal isto setthe data line D1 to the drain side and the data line D2to the source side. That is, theY decoder3 sets onlythe output line C1 to the H level. The address signal Ao is set to the L level.

Therefore, the gate 67, produces the L level, and the gate 69 produces the H level, with the result that MOSFET 0is becomes non-conductive, the data line Do attains the floating state, MOSFET Q20 becomes conductive and the data line D2 is connected to the ground potential of the circuit. The sense amplifier 8 detects whether or not the potential of the data line D drops.

As can be appreciated from the description given above, this is the system which determines the condition of the adjacent data lines by use of one of the address signals while one ortwo data lines adjacent to the data line connected to the memory cell are underthe selectable state by use ofthe output of the Y decoder.

Moreover, as has been described hereinbefore, the following effects can be attained bythe novel technical arrangement which is disclosed by the present application: (1) Data of 2 (bits) can be held in a single MISFET by setting threshold voltage high or low at the side or sides of the source region and/or the drain region of the M ISFET constructi n g the memory cell of the memory IC.

(2) Datafor2 (bits) can be held in a single MISFET by executing the writing of the data by alternately interchanging the data lines and the select lines.

Read-out ofthe 2 (bits) can be effected by reading the first bit with the data and select lines in a first position and reading the second bit with the data and select lines interchanged.

(3) Since the data of 2 (bits) can be held in the single MISFETthanks to the foregoing effect (Q( AND (2), the capacity of the memory IC can be increased to the remarkably high value.

(4) Datafor2 (bits) can be easily write in a single MISFET by implanting the hot carriers into the gate insulating film.

(5) By forming the thick insulating film 18 atthe middle portion between the source region and the drain region, the hot carriers injected can be held stably in the gate insulating film atthe side or sides of the source region and/orthedrain region of the MISFET.

(6) Since, thanks to the foregoing effect (3), the hot carriers injected can be held stably in the gate insulating film at the side or sides of the source region and/orthe drain region ofthe MISFET, it is possible to improve the reliabilityofthewriting and reading operations ofthe data of the memory IC.

Although the invention conceived by us has been described specifically in connection with the embodiments thereof, the present invention should not be limited to the foregoing embodiments but can naturally be modified in various manners without departing from the gist thereof.

For example, although the invention has been described with particular reference to storing 2 bits per memory cell with the interchanging of the select line and data line to accomplish this, it should be noted that the arrangement ofthe present invention could be used to store 1 bit per memory cell with a fixed data line coupled to the drain and a fixed select line coupled to the source so that no line interchange occurs.

Also, although various voltage levels, layer thicknesses, etc. have been given, it should be noted that othervalues could be used while stillfalling within the scope of the present invention. Besides the change of the threshold voltage, it is also possible to use a cell having a directivity in the mutual conductance 9m as the memory cell. Other means can be used as means for detecting the change of the potential of the data line besides the system using the sense amplifier described above.

Claims (28)

1. Asemiconductormemorvdevice comprising: a plurality of memory cells each comprised of an insulated field effecttransistorhavingfirstand second semiconductor regions of a first conductivity type formed separately from one another in a substrate of a second conductivity type, an insulating film, a gate electrode on the insulating film, wherein each portion adjacentto said first region or said second region has one ofthefirstthreshold voltage and the second threshold voltage higherthan said firstthreshold voltage in accordance with the data to bewritten in two bits into each of said memory cells.
2. A semiconductor memory device according to claim 1 wherein said second region having said second conductivity type is formed at said portion having said second threshold voltage.
3. Asemiconductor memory device according to claim 1 wherein said second conductivitytype is a p-type.
4. A semiconductor memory device according to claim 1 wherein carriers are injected to said insulating film of said portion having said second threshold voltage.
5. A semiconductor memory device according to claim 4, wherein said carriers are electrons.
6. A semiconductor memory device according to claim 5, wherein said memory cell has a read only memoryfunctionwhich can be erased by ultraviolet rays.
7. A semiconductor memory device according to claim 5, wherein said memory cell has a read only memoryfunction which can be erased by an electrical signal.
8. A semiconductor memory device according to claim 4, wherein each of said insulated gate field effect transistors further comprises an additional insulating layerformed between said insulating film and said late electrode, said additional insulating layer being formed over a central portion of said insulating film over a portion of the substrate located between said portions adjacent to said first or second regions, and wherein said additional insulating layer has a greaterthickness than said first insulating film.
9. A semiconductor memory device according to claim 4, wherein each insulated gate field effect transistorfurther comprises a floating gate electrode formed between said insulating film and said gate electrode, said floating gate electrode being separated from said gate electrode by a second insulating film.
10. A semiconductor memory device according to claim 1 which further comprises: a first line coupled to said first region; a second line coupled to said second region; and means coupled to said insulated gate field effect transistorsforsupplying a high voltage to one of said first and second lines, a low voltage to the other of said first and second lines and a predetermined gate voltage to said gate electrode for a selected memory cell to read data out of said selected memory cell in accordance with whether the voltage level at said first or second line receiving the high voltage remains at the high voltage or drops when the predetermined gate voltage is applied to the gate in accordance with whetherthewritten-in data has increased the threshold voltage of said insulated gate field effect transistor or not.
11. A semiconductor memory device according to claim 10 wherein the first bit ofthe selected memory cell is read out after said first and second lines are set to the high and low voltages, respectively, and wherein the second bit of the selected memory cell is read out aftersaidfirst and second lines are set to the low and high voltages, respectively.
12. A semiconductor memory device according to claim 12 which further comprises: a first line coupled to said first region; a second line coupled to said second region; and heans coupled to said insulated gate field effect transistors for supplying a first high voltageto one of said first and second lines, a low voltage to the other of said first and second lines and a predetermined gate voltage to said gate electrode for a selected memory cell to write data in to said selected memory cell, and means coupled to said insulated gate field effect transistors for supplying a second high voltage lower than said first high voltage to one of said first and second lines, a low voltage to the other of said first and second lines and a high gate voltage to said gate electrode for a selected memory cell to read data out of said selected memory cell in accordance with whetherthevoltage level at said first or second line receiving the high voltage remains at the high voltage of drops when the predetermined gate voltage is applied to the gate in accordance with whetherthe written-in data has increased the threshold voltage of said insulated gate field effect transistor or not.
13. A semiconductor memory device according to claim 12 wherein the bit written into the selected memory cell underthe state in which said first and second lines are set to said first high voltage and to said low voltage, respectively, is read out underthe state in which said first and second lines are set to said low voltage and to said second high voltage, respectively.
14. A semiconductor memory device according to claim 12 wherein the first bit of the selected memory cell is written under the state in which said first and second lines are set to said first high voltage and to said low voltage, respectively; wherein the second bit ofthe selected memory cell is written under the stage in which said first and second lines are set to said low voltage and to said first high voltage, respectively; the first bit of the selected memory cell is read out after said first and second lines are set to said low voltage and to said second high voltage, respectively; and wherein the second bit ofthe selected memory cell is read out after said first and second lines are set to said second high voltage and to said low voltage, respectively.
15. A semiconductor memory device comprising: a memory array having first data lines, second data lines and memory cells, each of said memory cells comprised of an insulated field effect transistor having first and second semiconductor regions formed separately from one another in a substrate, and capable of storing two-bits data; said first and second data lines coupled to said first and secondsemiconductor regions; a common data line to which said first and second data lines areto be coupled; a ground potential line to which said first and seconddata lines are to be coupled; and selecting means coupled to said first and second data lines; said selecting means selecting one of said memory cells upon receiving address signals for said data lines, and coupling one of said first and second data lines ofthe selected memory cell to said common data line and the other of said first and second data lines to said ground potential line.
16. A semiconductor memory device according to claim 15 wherein said selecting means comprises first selecting means for selecting a plurality of said data lines coupled to or adjacentto said memory cells to be selected, among said first and second data lines, and second selecting meansforcoupling one of the two data lines coupled with said memory cell to be selected, among said selected data lines.
17. A semiconductor memory device according to claim 16 wherein said first selecting means selects one ofthetwo data lines coupled to one memory cell, and said second selecting means couples the other of said data lines to said common data line.
18. A semiconductor memory device according to claim 16 wherein said second selecting means receives one bit of said address signal and said first selecting means receives the rest of said address signal.
19. A semiconductor memory device according to claim 18 wherein said one address signal is the most significant digit.
20. A semiconductor memory device according to claim 1 wherein each of said data lines has a first switch for the connection with said common data line and a second switch forthe connection with said ground potential line.
21. A semiconductor memory device according to claim 1 wherein said first selecting means selects one of the two data lines connected to one memory cell and two data lines adjacentto said one data line, and said firstselecting means couples said one data lineto said common data line.
22. A semiconductor memory device according to daim 16 which further comprises an output circu it for reading out data of said memory cells, connected to said common data line.
23. Asemiconductor memory device according to claim 22 wherein one of the two bits stored in one memory cell is read out underthe state in which said firstdata line is coupled to said common data line and said second data line is coupled to said ground potential line when said first address signal is received, and the other of said two bits is read out underthe state in which said first data line is coupled to said ground potential line and said second data line is coupled to said common data line when said second address signal is received.
24. A semiconductor memory device according to claim 17 which further comprises an input circuit for writing data into said memory cell coupled to said common data line, and an output circuit for reading outthe data from said memory cell coupled to said common data line.
25. A semiconductor memory device according to claim 24wherein one of the two bits stored in one memory cell is written underthestate in which said first data line is coupledto said common data line and said second data line is coupled to said ground potential line when said first address signal is received, and the other of said two bits is written underthe state in which said first data line is coupled to said ground potential line and said second data line is coupled to said common data line when said second address signal is received.
26. A semiconductor memory device according to claim 24 wherein said data written under the state in which said first data line is coupled to said common data line and said second data line is coupled to said ground potential line when said first address signal is received, is read out underthe state in which said first data line is coupled to said ground potential line and said second data line is coupled to said common data line when said first address signal is received.
27. A semiconductor memory device according to claim 26 wherein said second selecting means receives one bit of said address signal, and said one-bit address signal atthetime of read-out ofthe data is first converted to a signal which is the same as an inversion signal of said address signal at the time of write-in ofthe data, and is then supplied to said second selecting means.
28. A semiconductor memory device according to claim 25 wherein one of said bits is read out underthe state in which said first data line is coupled to said ground potential line and said second data line is coupled to said common data line when said first address signal is received, and the other of said bits is read out under the state in which said first data line is coupled to said common data line and said second data line is coupledto said ground potential linewhen said second address signal is received.
GB08507524A 1984-03-23 1985-03-22 A semiconductor integrated circuit memory device Withdrawn GB2157489A (en)

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JP5428684A JPS60201594A (en) 1984-03-23 1984-03-23 Semiconductor storage device
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