US20040027871A1 - Programming and erasing methods for a reference cell of an NROM array - Google Patents

Programming and erasing methods for a reference cell of an NROM array Download PDF

Info

Publication number
US20040027871A1
US20040027871A1 US10300924 US30092402A US2004027871A1 US 20040027871 A1 US20040027871 A1 US 20040027871A1 US 10300924 US10300924 US 10300924 US 30092402 A US30092402 A US 30092402A US 2004027871 A1 US2004027871 A1 US 2004027871A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
programming
level
threshold voltage
voltage
step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10300924
Inventor
Ilan Bloom
Eduardo Maayan
Boaz Eitan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion Israel Ltd
Original Assignee
Spansion Israel Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising plural independent storage sites which store independent data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • G11C16/28Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563Multilevel memory reading aspects
    • G11C2211/5634Reference cells

Abstract

A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation application of U.S. Ser. No. 09/827,596, filed Apr. 5, 2001, which is a continuation-in-part application of U.S. Ser. No. 09/730,586, filed Dec. 7, 2000, which is a continuation-in-part application of U.S. Ser. No. 09/563,923, filed May 4, 2000.[0001]
  • FIELD OF THE INVENTION
  • The present invention relates generally to electrically erasable, programmable read only memory (EEPROM) cells and specifically, to methods for programming thereof. [0002]
  • BACKGROUND OF THE INVENTION
  • FIG. 1, to which reference is made, illustrates a typical prior art floating gate cell, comprising two diffusion areas, source [0003] 102 and drain 104, embedded in a substrate 105, between which is a channel 100. A floating gate 101 is located above but insulated from channel 100, and a gate 112 is located above but insulated from floating gate 101.
  • Typically, when programming the floating gate cell, programming voltages V[0004] G and VD are applied to gate 101 and drain 104, respectively, and a low source voltage VS is applied to source 102. For array applications, a row of gates are formed into a word line, and a column of drain and source are formed into bit lines along which voltages VD and VS, respectively, are supplied.
  • The source and drain voltages V[0005] S and VD, respectively, create a lateral field that pulls channel electrons from source 102 to drain 104. This is indicated by arrow 10. Near drain 104, a vertical field created by the gate voltage VG allows hot channel electrons to be injected (arrow 12) into floating gate 101. Once injected into floating gate 101, the electrons are distributed equally across the entire gate, increasing the threshold voltage VTH of gate 101.
  • Another type of non-volatile cell is the nitride, read only memory (NROM) cells are described in Applicant's copending U.S. patent application Ser. No. 08/905,286, entitled “Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” which was filed Aug. 1, 1997. The disclosure of the above-identified application is incorporated herein by reference. [0006]
  • Similar to the floating gate cell of FIG. 1, the NROM cell illustrated in FIGS. 2A and 2B, to which reference is now made, has channel [0007] 100 between two diffusion areas 102 and 104. However, unlike the floating gate cell, the NROM cell has two separated and separately chargeable areas 106 and 108. Each chargeable area defines one bit. For the dual bit cell of FIG. 2, the separately chargeable areas 106 and 108 are found within a nitride layer 110 formed in an oxide-nitride-oxide (ONO) sandwich (layers 109, 110 and 111) underneath gate 112.
  • To program the left bit in area [0008] 106, the left diffusion area 102 receives the high programming voltage VD (i.e. area 102 the drain) and right diffusion area 104 is grounded (i.e. area 104 the source). Hence the electrons flow from area 104 to area 102. This is indicated by arrow 114. The channel hot electrons are then injected into the nitride layer, in area 106. The negative charge in area 106 raise the threshold voltage of the cell, if read in the reverse direction.
  • The opposite is true for programming area [0009] 108; the left diffusion area 102 is the source (i.e. grounded) and right diffusion area 104 is the drain (i.e. receives high programming voltage VD). The cell is therefore programmed in the opposite direction, as indicated by arrow 113, and the electrons then jump up into chargeable area 108.
  • For NROM cells, each bit is read in the direction opposite (a “reverse read”) to that of its programming direction. An explanation of the reverse read process is described in U.S. patent application Ser. No. 08/905,286, mentioned above. Thus, to read the left bit stored in area [0010] 106, right diffusion area 104 is the drain and left diffusion area 102 is the source. This is known as the “read through” direction, indicated by arrow 113. To read the right bit stored in area 108, the cell is read in the opposite direction, indicated by arrow 114. Thus, left diffusion area 102 is the drain and right diffusion area 104 is the source.
  • During the read operation, the presence of the gate and drain voltages V[0011] G and VD, respectively, induce a depletion layer 54 (FIG. 2B) and an inversion layer 52 in the center of channel 100. The drain voltage VD is large enough to induce a depletion region 55 near drain 104 which extends to the depletion layer 54 of channel 100. This is known as “barrier lowering” and it causes “punch-through” of electrons from the inversion layer 52 to the drain 104.
  • Since area [0012] 106 is near left diffusion area 102 which, for this case, acts as the source (i.e. low voltage level), the charge state of area 106 will determine whether or not the inversion layer 52 is extended to the source 102. If enough electrons are trapped in left area 106, then the voltage thereacross will not be sufficient to extend inversion layer 52 to the source 102, the cells current will be low, and a “0” will be read. The opposite is true if area 106 has no charge.
  • Reference is now made to FIGS. 3A, 3B and [0013] 3C, which are timing diagrams of an exemplary prior art programming schedule for NROM cells. Typically, when programming an NROM cell, programming pulses 120A, 120B and 120C, consisting of programming voltages VD, VS, and VG, respectively, are applied to the cell. Programming pulses 120 are then followed by program verify pulses 122A, 122B and 122C, consisting of read voltages VD, VS, and VG, respectively, during which time the cell is read.
  • If there are enough electrons trapped in the bit, a “0” is read, and the cell is verified as programmed. If, however, during the read operation, the inversion layer is not strong enough to prevent the current flow through the channel, than the bit will be read as a “1”, and the cell will fail program verification. [0014]
  • The sequence of pulses [0015] 120 and 122 are repeatedly applied until the effect of the charged trapped in area 106 (or 108) has reached the desired level and the cell is considered “programmed”. The programming process is then terminated.
  • Due to ever demanding manufacturing requirements, the semiconductor industry is continuously searching for ways to improve the programming process. There exist two contradicting programming requirements; 1) to increase the programming speed, thereby reducing the cost of testing the part, and 2) to improve the control of the final programmed threshold, thereby enhancing product reliability. [0016]
  • The first requirement can easily be met just by increasing the drain and gate potentials to their maximum values. However, this strategy will not meet the second requirement due to many process and environmental parameters that affect the programming rate and its variations. [0017]
  • To achieve the second requirement, there are two basic options, controlling the length of the programming sequence, and/or stepping the amplitude of the gate voltage potential. [0018]
  • The article “Nonvolatile Multilevel Memories for Digital Applications”, published in the [0019] IEEE Magazine on Dec. 12, 1998, discusses a number of proposed methods for programming multi-level floating gate circuits, including that of controlling the programming time length. One such method is discussed In the section Programming and Accuracy, 2) Drain Voltage Programming, as follows: 1) a constant gate voltage is set, 2) per bit level of the multi-level cell, a constant drain voltage is determined, and 3) the cell is programmed for a predetermined time period. At the completion of the time period, the programming is terminated. Alternately, the article describes an approach whereby after each programming pulse, the threshold voltage VTH is verified. Upon reaching the target threshold voltage, programming is terminated.
  • U.S. Pat. No. 5,523,972 describes a floating gate method that entails incrementally increasing the programming gate voltage V[0020] G, while keeping other factors constant (e.g. source and drain voltages, VS and VD, respectively). In the described programming algorithm, each cell is checked to determine whether or not it has reached the desired state. If not, a programming gate voltage pulse of a slightly higher voltage is applied to the cell. The charge level is checked again, and if the desired state has not yet been reached, the voltage is raised again and applied. This process is repeated until all the cells reach the desired level.
  • U.S. Pat. No. 5,172,338 describes a programming algorithm similar to that described in the U.S. Pat. No. 5,523,972, however, on a per cell basis. Every cell that reaches the desired level does not receive the drain voltage of the next step. This sequence is continued until the last bit of the byte word/group is programmed. [0021]
  • As explained in both “Nonvolatile Multilevel Memories for Digital Applications” and U.S. Pat. No. 5,523,972, in floating gate cells, the relationship between ΔV[0022] G and ΔVTH is linear. As such, control of programming is relatively precise since, for every change in the gate voltage VG, there is a similar change in the threshold voltage VTH of the cell.
  • Nonetheless, there are many factors influencing the programming speed, and consequently, the programming speed may vary from cell to cell even when the same level of programming voltage is applied thereto. FIG. 4, to which reference is now made, illustrates the typical variation of programming time for a normal population of memory cells. Point [0023] 126 depicts the cell with the fastest programming speed, while point 128 represents the cell with the slowest programming speed. The variance in time between point 126 to point 128 can be as large as 500×.
  • The wide variation of programming speeds creates problems during programming of memory cell arrays. These arrays may contain many millions of memory cells, each with its own distinct programming speed. Some cells may reach their programmed level in a shorter time than needed for other cells to reach their programmed levels. Thus, the programming process needs to be terminated for some cells, while for other, it needs to be continued. [0024]
  • Some of the factors influencing the programming speed in floating gate cells are: variations in process parameters such as channel length, gate coupling ratio, drain coupling ratio, source resistance variations (array effect) and channel doping variations. Another factor influencing the program rate is the temperature of the product during programming; generally, the lower the temperature, the faster the programming rate. [0025]
  • In NROM cells, the parameters that affect the programming speed are: the ONO thickness, the channel length, the channel doping and the temperature. For dual bit NROM cells, the programming state of one bit affects the programming speed of the other bit. [0026]
  • When an improper programming algorithm is used, some cells may receive too high programming voltages or may be programmed for too long. In such instances, an over-abundance of charge is introduced into the gate or retention layer (NROM) and the memory cell is “over-programmed”. In floating gate cells, over-programming deteriorates the quality of the oxide layer (reference number [0027] 109, FIG. 1), creating reliability problems due to the degradation of the quality of the product. Furthermore, continuing to apply high voltage pulses once the unit cells have already reached the programmed level wastes power and creates a power dissipation problem.
  • Moreover, as to be described below, in multi-level floating gate products, over-programming can lead to information read failures. Reference is now made to FIG. 5, a graph illustrating the different threshold voltage levels comprised within a multi-level floating gate cell. As depicted in the FIG. 5, each bit in the multi-level floating gate cell is defined by a predefined region of voltage threshold V[0028] TH. As an example, the first bit lies in region 132, (to the left of line W), while the second bit lies in region 134 (from line W to line X), the third bit in region 136 (from line X to line Y), and so on. When a cell is over-programmed, the resultant threshold voltage may overshoot the desired region, thus leading to a read error or failure.
  • Further problems arise when programming both bits of multi-bit memory cells, such as the two-bit NROM cell. Once the first bit is programmed, the threshold voltage V[0029] TH of the cell is raised, and consequently, the programming of the second bit of the cell is slower.
  • In NROM cells, in addition to the stated problems connected with breakdown of the oxide layer and unnecessary dissipation of power, over-programming creates different problems. As explained below in connection with FIGS. [0030] 6, over-programming results in quality deterioration and reliability degradation, as well as read failures in two-bit cells.
  • FIGS. 6A, 6B, [0031] 6C and 6D, to which reference is now made, are exploded views of the NROM cell depicted in FIGS. 2A and 2B. It is noted that the shape of the trapped charge in chargeable areas 106 and 108 range from a narrow pocket, depicted as 106N and 108N, to an average pocket (i.e. 106A and 108A), to an even wider pocket (i.e. 106W and 108W) with a “tail” 44.
  • Applicants note that tail [0032] 44, which is farther from the bit line than the bulk of the trapped charge, is generally not removable during erasure and thus, reduces the ability of the NROM cell to withstand a large number of program and erase cycles. Typically, erasure depletes only the charge concentration closest to the diffusion area. Thus, if the distribution pocket is too wide, the tail 44 of the trapped charge will not erase, and with each progressive erase, more and more charge will remain in the retention section, even after erasures (FIG. 6D).
  • The trapped charge in tail [0033] 44 acts as partially programmed charge. It is due to the trapped charge in tail 44 that fewer programming pulses are required to achieve the programmed threshold voltage level (since the bit is already, in effect, partially programmed).
  • Furthermore, the accumulation of trapped negative charge far from the junction increases the threshold voltage level, which affects the reverse read, making it difficult to distinguish the first bit from the second bit and creating read failures. In order to compensate, the erase operation accumulates extra positive charge close to the junction, which makes the erase time take longer. [0034]
  • Unfortunately, prior art methods of gradually increasing the programming gate voltage V[0035] G are not effective for NROM cells, and tend to produce the following two problems:
  • 1. In NROM products, increases in the gate voltage V[0036] G do not linearly correlate to increases in the threshold voltage VTH, and the effect of the increases varies from cell to cell. This causes a lack of precise programming control, and an incurred risk of over programming.
  • 2. In order to ensure a reasonable yield rate, meeting the programming rate requirement, the drain voltage V[0037] D potential must be high, creating trapped charge regions distant from the junction.
  • The above two problems result in reduction in the endurance of the product, increase in the charge loss and reduction in yield. [0038]
  • In regard to the first problem, reference is now made to FIG. 7, an electrical schematic of a portion of an NROM array. The depicted circuit includes a bit line power supply V[0039] PPS, a select transistor 152, resistors R1 and R2, and an NROM cell 154. Resistors R1 and R2 denote the native resistance of the wire in the depicted array. Transistor 152 is a select transistor used to select a bit line of the array. Programming current IPR flows throughout the entire circuit. The voltage drops across the channels of transistor 152 and cell 154 are designated as VDS-SEL and VDS, respectively.
  • In NROM cells, small increases in the programming gate voltage V[0040] G greatly influences the programming current IPR. In a chain reaction effect, when the programming gate voltage VG is stepped, programming current IPR increases, which causes an increase in voltage drops VDS-SEL and VDS and an increase in the voltage drops along resistors R1 and R2. Hence, with all the different factors changing, there is no clear linear relationship between the stepped gate voltage VG and the threshold voltage VTH, and therefore, no precise control over the programming process. As a further complication, the reduction in VDS increases the programming time exponentially.
  • Reduction in the incremental increase of the gate voltage V[0041] G can alleviate part of the control problem, but it will dramatically increase the programming time. Further control improvement can be achieved by increasing the dynamic range of the gate voltage VG. Unfortunately, there are resultant difficulties at both ends of the dynamic range.
  • Low gate voltage V[0042] G results in cycling degradation. So therefore, the desired gate voltage VG is set relatively high, i.e. 8-10V. Further increases in gate voltage VG, such as over 10V, require special processes and put severe limitations on the scaling of the ONO thickness due to charging by tunneling. For example, a 180A ONO of the 0.5 μm process will experience tunneling charging for voltages over 12V.
  • The second problem noted above (high drain voltage V[0043] D) creates even more severe limitations on the stepped gate voltage VG approach. When programming according to stepping of the gate voltage VG, the programming drain voltage VD must be fixed and high in order to cover a large dynamic range. Using a high programming drain voltage VD creates a large lateral field and a wide pinch-off regime, yielding a wide trapped charge region. Accordingly, the resultant product is the undesirable tail 44, which drastically reduces the product's endurance.
  • Hence, due to the first problem noted above, using the gate voltage V[0044] G as a dynamic parameter for controlling programming is very limited in range.
  • In conclusion, in NROM cells, stepping the programming gate voltage V[0045] G does not provide tight programming control and is not effective in preventing over-programming and eventual degradation of the product's quality.
  • As can be understood from the above, when prior art programming algorithms are applied to the NROM cell, they do not sufficiently provide the abilities to produce increased programming speed while maintaining tight programming control. Applicants have found a need for an NROM programming algorithm which executes these functions over a wide range of programming parameters, thus avoiding the dangers of over-programming and its resultant reduction in product reliability. [0046]
  • SUMMARY OF THE INVENTION
  • A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming the reference cell with small programming steps until the threshold voltage level is above a final target level. [0047]
  • Specifically, there is provided, in accordance with a preferred embodiment of the present invention, a method for programming a reference cell of a memory array which uses programming pulses. If a threshold voltage of the reference cell is below an interim target level, the method includes the step of raising a drain voltage for a next programming pulse and otherwise, setting the drain voltage for the next programming pulse at a fixed level not higher than a current level. Programming pulses are provided using the fixed drain voltage level until the threshold voltage level is at or above a final target level above the interim target level. [0048]
  • Additionally, in accordance with a preferred embodiment of the present invention, for the step of providing, the programming pulses have a different duration than the programming pulse for the step of raising. [0049]
  • Moreover, in accordance with a preferred embodiment of the present invention, the interim target level is in the range of 100-400 mV below the final target level. [0050]
  • Alternatively, in accordance with a preferred embodiment of the present invention, the interim target level is below the final target level by an amount generally not smaller than an expected threshold voltage change due to the programming pulses of the raising step. [0051]
  • Further, in accordance with a preferred embodiment of the present invention, the method also includes the step of measuring the programmed threshold voltage level after each programming pulse. [0052]
  • Still further, in accordance with a preferred embodiment of the present invention, the method also includes the step of determining after each programming pulse if the programmed threshold voltage is above or below the target level. [0053]
  • There is also provided, in accordance with a further preferred embodiment of the present invention, a method for programming a reference cell of a memory array which includes the steps of fast programming of the reference cell until a threshold voltage level of the reference cell is above an interim target level and slow programming of the reference cell until the threshold voltage level is above a final target level which is above the interim target level. [0054]
  • Additionally, in accordance with a preferred embodiment of the present invention, the fast programming comprises providing programming pulses and changing a drain voltage level between programming pulses. [0055]
  • Moreover, in accordance with a preferred embodiment of the present invention, the slow programming comprises maintaining a generally constant drain voltage level between programming pulses. [0056]
  • Further, in accordance with a preferred embodiment of the present invention, the steps of programming include providing programming pulses and also include the step of measuring the threshold voltage level of the reference cell after each programming pulse. [0057]
  • There is still further provided, in accordance with a preferred embodiment of the present invention, a method for programming a reference cell of a memory array which includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming the reference cell with small programming steps until the threshold voltage level is above a final target level. [0058]
  • Moreover, in accordance with a preferred embodiment of the present invention, the programming with large programming steps includes providing programming pulses and changing a drain voltage level between programming pulses. [0059]
  • Finally, in accordance with a preferred embodiment of the present invention, the programming with small programming steps comprises maintaining a generally constant drain voltage level between programming pulses. [0060]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended drawings in which: [0061]
  • FIG. 1 is a schematic illustration of a floating gate memory cell; [0062]
  • FIGS. 2A and 2B are schematic illustrations of a NROM memory cell; [0063]
  • FIGS. 3A, 3B and [0064] 3C are graphical illustrations of a prior art programming scheme;
  • FIG. 4 is a histogram of the distribution of programming speed in NROM memory cells; [0065]
  • FIG. 5 is a graph of the charge levels in a multi-level floating gate cell; [0066]
  • FIGS. 6A, 6B, [0067] 6C and 6D are schematic illustrations of trapped charge retained in a two-bit NROM memory cell;
  • FIG. 7 is an electrical schematic illustration of a portion of an NROM array; [0068]
  • FIGS. 8A, 8B and [0069] 8C are graphs illustrating the effect of programming drain voltages on the threshold voltage, as a function of cell temperature, channel length, and array and second bit effects, respectively;
  • FIG. 9 is a graph illustrating the effect of the gate voltage and the drain voltage on the threshold voltage; [0070]
  • FIG. 10 is a graph illustrating the increases in the threshold voltages over time, as a function of the drain voltage; [0071]
  • FIGS. 11A, 11B and [0072] 11C are graphical illustrations of a programming algorithm, constructed and operated according to a preferred embodiment of the present invention;
  • FIG. 12 is a flow chart illustration of a method of setting an initial programming voltage level, operative in accordance with a preferred embodiment of the present invention; [0073]
  • FIGS. 13A, 13B, [0074] 13C, 13D and 13E are schematic illustrations of histograms of the number of programming pulses required to program the bits of an array for the method of FIG. 12;
  • FIGS. 14A and 14B together are a flow chart illustration of a method of setting an initial erase voltage level, operative in accordance with a preferred embodiment of the present invention; [0075]
  • FIG. 15 is a schematic illustration showing two programming schedules for two different bits; [0076]
  • FIG. 16 is a schematic illustration of an alternative embodiment of the present invention having multiple verify levels during programming; [0077]
  • FIG. 17 is a flow chart illustration of a method of generally fast erasing using multiple verify levels; [0078]
  • FIG. 18A is a schematic illustration of threshold voltage levels for various reference cells; [0079]
  • FIG. 18B is a schematic illustration of the operation of programming an exemplary reference cell; [0080]
  • FIGS. 19A, 19B, [0081] 19C and 19D are a series of timing diagram illustrations of the programming algorithm for reference cells;
  • FIGS. 20A and 20B are graphical illustrations of the evolution of the threshold voltage of two reference cells; and [0082]
  • FIG. 21 is a flow chart illustration of an exemplary programming method for reference cells. [0083]
  • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • The present invention teaches an NROM cell algorithm which regulates the bit line voltage V[0084] BL provided to the bit line acting as the drain, thereby providing tight programming control. Furthermore, the described invention provides the combination of a fast programming algorithm with reduced over-programming risk, and hence improved product endurance and cycling ability.
  • Although a bit line can act as either a source or a drain, in the present application, references to the bit line voltage V[0085] BL refer to the voltage provided to the bit line currently acting as a drain. For purposes of clarity herein, when the bit line acts as a source, it is herein referred to as a source.
  • The present invention further teaches the use of a low programming bit line voltage V[0086] BL to produce a tight spatial distribution of trapped charge, thereby resulting in better two-bit separation in the NROM cell, faster erase, and increased product life.
  • Furthermore, by controlling the bit line voltage V[0087] BL, the present invention provides a fast and generally accurate programming algorithm for a large distribution of cells with diverse process variations and programming times. Reference is now made to FIGS. 8A-C, a series of graphs that illustrate the effect of the programming bit line voltage VBL on threshold voltage VTH as a function of cell temperature, channel length, and array effects/second bit, respectively. In this graph the reverse read threshold voltage VTR, which is the threshold voltage VTH when the cell is reverse read, is a function of bit line voltage VBL. Every point represents a programming pulse of 2 μsec in exemplary steps of 0.3V. It is noted that the gate voltage VG is constant at 9V.
  • The graph in FIG. 8A illustrates [0088] 3 programming curves for three varying cell temperatures: curve 202 denotes a cell at −40° C., curve 204—a cell at 20° C., and curve 206—a cell at 80° C. As seen in the figure, in order to achieve a specific threshold voltage VTH, each cell receives a different drain voltage VD, depending on the temperature of that specific cell. As an example, to achieve a desired threshold voltage VTH of approximately 4V, the low temperature case (curve 202) receives a bit line voltage VBL of approximately 4.1V, while the high temperature case (curve 206) must receive a bit line voltage VBL potential of 5V to reach the same desired threshold voltage VTH level. Accordingly, in a preferred embodiment, the bit line voltage VBL is incrementally increased from a minimum voltage to a higher voltage, thus covering a wide range of operating temperatures.
  • When a cell has reached the desired threshold voltage V[0089] TH, such as 4V, the programming algorithm for that cell is terminated. Meanwhile, for cells which have not yet reached the desired threshold voltage, the bit line voltage VBL is incrementally increased, until those cells have reached their desired level. Thus, referring to the example above, when operating at a low temperature (curve 202), the cell will complete programming at a bit line voltage VBL of 4.3V, while if operating at high temperatures (curve 206), the cell will complete programming at a bit line voltage VBL of approximately 5V. It is noted that for curves 202 and 206, the bit line voltages VBL of 4.3V and 5V, respectively, are the first bit line voltage levels that result in a threshold voltage VTH higher than the exemplary target of 4V.
  • It is also apparent from FIG. 8A that the chosen step size for the bit line voltage V[0090] BL affects the size of the maximum overshoot (over-programming) of the threshold voltage VTH. In order to achieve a very accurate bit line voltage VBL rise, it is preferable that the step size is relatively small. Thus to receive the programming level, the resultant algorithm requires many programming steps and may result in extended programming times. Conversely, a large voltage step results in quicker programming times however, opens up to the risk of a large overshoot. The practical step size is a compromise between the requirements for quick programming speed and limited overshoot.
  • It is noted that, when observing the section of the graph commencing at a bit line voltage V[0091] BL of 3V, although the absolute rise of the curves may differ, the slopes of the curves are essentially equivalent, and approximately linear. Consequently, for each step in the bit line voltage VBL, there is an equivalent step in the threshold voltage VTH, regardless of the temperature of the cell.
  • Thus, for a known incremental increase in drain voltage V[0092] D, it is possible to guage the incremental increase in threshold voltage VTH. Knowing this information allows for more precise programming abilities and a greater protection against over-programming, with all the detrimental affects associated therewith.
  • FIG. 8B is comparable to the graph of FIG. 8A and depicts the effect of the bit line voltage V[0093] BL on the reverse read threshold voltage VTH as a function of a channel length of 0.6 μm, 0.65 μm and 0.7 μm respectively, for curves 212, 214, and 216, respectfully. FIG. 8C depicts the effect of the of the bit line voltage VBL on the reverse read threshold voltage VTH as a function of the location of a cell along a 32 bit long local diffusion bit-line segment and a comparison between the 1″ and 2nd bit of the same cell. The fastest bit is bit 1 of word-line 16 and the slowest is bit 2 on word-lines 32 and 2. In order to reach a threshold voltage VTH of 3.5V, the fastest bit receives a bit line voltage VBL equal to approximately 5.8V, and the slowest, receives approximately 7V.
  • As was noted in FIG. 8A, and bringing attention to a similar phenomenon in FIGS. 8B and 8C, although the characteristics of the represented cells differ, the programming slope is generally equivalent and generally linear. Hence, the explanation as outline above for FIG. 8A is also applicable to these figures, and the conclusions drawn for FIG. 8A are also applicable to FIGS. 8B and 8C. [0094]
  • Consequently, for an array of cells with a wide divergence of process and/or environmental conditions, by stepping the bit line voltage V[0095] B1, it is possible to achieve a controlled programming algorithm with an accurate prediction of the delta threshold voltage VTH rise.
  • Although it is possible to cover a diverse range of programming variations by stepping the gate voltage V[0096] G, as was done in prior art floating gate algorithms, in NROM cells, drain voltage V stepping is more efficient. Reference is now made to FIG. 9, a graph illustrating the programming time of an exemplary cell (channel length=0.65 μm, temperature=20° C.) as a function of either drain voltage VD or gate voltage VG.
  • When programming with a constant gate voltage V[0097] G and a stepped drain voltage VD between 4.5V to 5.5V, the resultant programming times range from of 100 μsec down to 0.8 μsec, respectively. However, in order to achieve approximately the same programming time range with a constant drain voltage VD, the gate voltage must be stepped from 8V to 11.5V. Thus, in the NROM cell, in order to cover an equivalent range of programming times, a 1V step in drain voltage VD is equivalent to a 3.5V step in gate voltage VG.
  • As further noted and depicted in FIG. 9, when stepping the gate voltage V[0098] G, in order to catch the fast programming cells without risking over-programming, the resultant programming algorithm must commence with a low potential for the gate voltage VG. This, however, is undesirable since it causes programming to be slow. Hence, in order to increase the programming speed, the low gate voltage VG must-be paired with high drain voltages VD.
  • Nonetheless, as noted in the previous sections, high drain voltages V[0099] D promote cell degradation and decreased cycling ability. Unequivocally, high drain voltages VD in combination with a low gate voltages VG are even more detrimental to the cell, producing very large lateral fields and wide pinch-off regions, yielding an extensive trapped charge region.
  • In contrast, in the present invention, in order to capture the fast programmers, the inventive programming algorithm commences with a low drain voltage V[0100] D, and a high gate voltage VG. This is favorable since applying a high programming gate voltage VG and a low drain voltage VD imposes a large vertical field and a narrow pinch-off regime, thus resulting in a narrower trapped electron pocket.
  • In order to explain the present invention in more detail, reference is now made again to FIGS. 2A and 7. As noted above (FIG. 2A), in NROM cells the charge is trapped in a localized region and the read process is a reverse read. As such, the programming current I[0101] PR is generally insensitive to the rise in threshold voltage VTH, and remains constant even during programming.
  • The programming current is fixed during programming since the cell is programmed in the forward direction, which causes the charge to be trapped next to the drain. Hence, during reading, there is full punch-through under the localized charge. Additionally, for each increase in the threshold voltage V[0102] TH, the charge is punched through at a greater distance from the junction.
  • Hence, [0103]
  • ΔV D S=αΔV TH =V BL −V BL-S  (1)
  • where V[0104] BL-S is the bit line voltage for the source and is constant, and a is a constant proportionally between 0.5 and 2, and is affected by parameters such as channel length, gate voltage VG, temperature, and location of the cell in the array. Referring now to FIG. 7, the IR loss equation that defines the circuit depicted therein is:
  • V PS =V DS +V DS-SEL+(R 1 +R 2)*I PR  (2)
  • Since the programming current I[0105] PR is constant, then the IR losses across VDS-SEL, IPR and R1 and R2 are also constant. Consequently, the only remaining non-constant factor is the channel voltage VDS. Thus
  • ΔV PS =αΔV DS  (3)
  • Thus, since V[0106] BL2 is constant, when combining equations (1) and (3)
  • ΔV PS ≅ΔV BL =ΔV TH  (4)
  • or, since V[0107] BL is equivalent to VD
  • ΔV D =αΔV TH  (5)
  • Evidence to such can also be seen when observing the linear sections of FIGS. [0108] 8A-8C, and as explained hereinabove in reference to those graphs. Consequently, when considering this linear relationship, applicants have concluded that closely controlling the drain voltage VD produces a known change in the threshold voltage VTH, and thus the programming algorithm of the present invention provides precise control over the programming procedure, including preventing over-programming.
  • Reference is now made to FIG. 10, a graph illustrating the rise in threshold voltage V[0109] TH, as a function of time, with the bit line voltage VBL as a parameter. Depicted in FIG. 10 the resulting threshold voltage VTH for 4 exemplary drain voltages of 5V, 5.25V, 5.5V and 5.75 V, respectively.
  • As can be observed in all of the curves, the threshold voltage V[0110] TH rises quickly at the start of the curve, and then reaches a point where the increase in threshold voltage VTH i is saturated. The flatter region of the curve, to the right of dashed line 232, illustrates the region wherein the cell programming has saturated and subsequent programming pulses have a limited affect on the cell. Once saturated, most of the rise in threshold voltage VTH is due to an undesirable injection of remote electrons from non-primary mechanisms.
  • Therefore, in order to maintain an efficient increase in the threshold voltage V[0111] TH, and in order to create a pocket of trapped charge close to the drain, it is preferable to remain in the part of the graph (to the left of line 232) where the threshold voltage rise is steep. With stepping of bit line voltage VBL, it is possible to remain in the steep slope area (left of line 232).
  • As an example, when stepping in increments from the designated points [0112] 234 to 236, to 238, and to 240, it is possible to achieve equivalent increases in the threshold voltage VTH. When observing FIG. 10, it is possible to note that in the range of points 234 240, for each 0.25V increase in the bit line voltage VBL, there is a 0.15V increase in the threshold voltage VTH.
  • It is therefore noted that, according to a preferred embodiment of the present invention, a progressively increasing drain voltage V[0113] D causes the threshold voltage VTH to climb along the steep slope of the programming function, and produces a more efficient and quicker programming algorithm.
  • Reference is now made to FIGS. 11A, 11B, and [0114] 11C, a series of timing diagrams of a programming algorithm for NROM cells, constructed and operated in accordance with a preferred embodiment of the present invention. Although FIGS. 11A-11C illustrate only a limited number of pulses, it is apparent that a typical programming algorithm comprises numerous pulses and still complies with the principles of the present invention.
  • FIGS. [0115] 11A-11C depict a programming algorithm utilizing gate voltage VG, drain voltage VD, and source voltage VS, respectively. The algorithm additionally comprises a series of alternating programming and program verify pulses. The first pulse is a programming pulse and is designated as A. The second pulse is a program verify pulse and is designated as B, and so on.
  • The sequence of programming and program verify pulses A, B, C, etc. are repeatedly applied to an array of NROM cells. Once the threshold voltage V[0116] TH of an applicable cell has reached a desired level, the programming algorithm is terminated for that specific cell. The programming algorithm proceeds until each cell has reached the desired level, at which point the algorithm is terminated. Preferably the algorithm is applied on a bit by bit basis for either a byte, or word.
  • With each progressive programming pulse, from A to C to E, the level of the drain voltage V[0117] D increases. Typically, the voltage steps are evenly incremented from progressive drain voltage VD pulse to pulse, i.e. at fixed increments of 0.25V, or any other desired increment.
  • Alternatively, in order to customize the algorithm for diverse programming times, and as a means to improve programming speed, the present method teaches unevenly incremented voltage steps, i.e. with smaller incremented steps at the start of the algorithm and larger steps as the algorithm progresses. In this manner, the [0118]
  • The explanation for such is as follows: When a cell commences programming, its threshold voltage V[0119] TH is relatively low. With the application of each progressive programming pulse, the threshold voltage VTH of the cell increases. Each time the threshold voltage VTH increases, a higher programming pulse is needed to force punch-through of electrons. Hence, at the start of the programming algorithm, when the threshold voltage VTH is low, smaller incremental jumps are sufficient to induce punch-through. However, farther into the algorithm, when the threshold voltage VTH is higher, larger steps are needed to produce the punch-through effect. Consequently, by varying the incremental size of the voltage step increases, i.e. with small steps at the beginning when the threshold barrier is still low, and with larger steps when the barrier is higher, it is possible to provide more precise control over the programming algorithm. See for example FIG. 8A, wherein the slope is shallower for the hot temperature cells than for the cooler temperature cells.
  • According to a preferred embodiment of the present invention, when programming an NROM cell, the gate voltage V[0120] G is high and constant, (e.g. 10V) and the drain voltage VD is as low as possible, resulting in a narrow spatial distribution of trapped charge. Preferably, the initial bit line voltage VD is approximately 4V.
  • When programming with a low initial bit line voltage V[0121] D, the resultant spatial distribution of the trapped charge 24 is closer to the diffusion area, which also facilitates effective erasure and increased life cycles. It is additionally noted that, due to the tighter spatial distribution of trapped charge, the present invention produces better two-bit separation and enables better distinction between the two bits during read. Furthermore, a smaller tail of trapped charge results in less erase time and voltage. This in turn, improves retention since less erase stress creates less trapped holes in the nitride. Less trapped holes, improves the retention since there is less trapped movement at the high temperature back.
  • It is noted that the final step of the drain voltage V[0122] D stops at a level that is just sufficient to reach the desired threshold voltage VTH, thus avoiding any unnecessary extra pulses of the drain voltage VD which might create secondary electron injections far from the junction, imposing the unwanted tail 44.
  • Frequently, due to architecture density, the applied source voltage V[0123] S is not necessarily ground or 0V. However, in order to provide a tight distribution of charge, it is preferable that source voltage VS be as close to OV as possible, and preferably less than 0.5V.
  • The present invention includes adapting the programming and erasure methods of an array to its particular circumstances. For example, the speed of programming and erasure of a bit is a function of how it is manufactured, the current operating temperature, the power supply, the peripheral circuitry and, if there are two bits in the memory cell, the programmed state of the other bit. Having a programming and/or erasure method that is adaptable enables the memory array to be programmed and/or erased quickly in most circumstances, no matter how the operating and environmental conditions vary. [0124]
  • The present invention presents two types of adaptations, one of the initial programming or erasure level and the other of the program or erasure step. [0125]
  • In some instances, it may be known that all of the cells are “slow” to program. Usually, this means that the initial program steps are not effective. In accordance with a preferred embodiment of the present invention, it is possible to dial-in a higher initial drain voltage V[0126] D (pulse A) As an example, and referring again to FIG. 8B, for cells with a longer than average channel length dimension (curve 216), the initial dialed-in drain voltage VD might be 4V, while for the cells with shorter channel lengths (curve 212), the dial in drain voltage VD would be 3.1V. In such a manner, for the cells on curve 216, the first few ineffective pulses between 3.1V and 4V are eliminated, and the programming time is shortened.
  • The dial-in level is determined from the response of the bits of the array, as described hereinbelow, and thus, is adapted to the particular array. [0127]
  • Reference is now made to FIG. 12, which illustrates the method, using the dial-in procedure, to determine the highest possible, initial programming level for the memory array. This method is generally performed once per array, as part of a sort or a test part of the manufacturing process, although it can be performed at other times as well. Reference is also made to FIGS. 13A, 13B and [0128] 13C, which are useful in understanding the method of FIG. 12.
  • A representative portion of the array is first programmed (step [0129] 100), where “programmed” means that the threshold voltage of each cell is above a predetermined “program verify” level.
  • The representative portion should include enough bits to cover the expected variation in programming responses. For example, the portion can include a few bytes. If there are more than one bit per cell, the portion should include a selection of each type of bit. The portion should also include cells in different locations within a block and/or column of cells, since the paths to such, from the power supplies, are different and each path has a different resistance level. The cells of the representative portion may be chosen according to known array effects and to sensitive manufacturing areas in the array. Which cells are chosen is typically determined empirically. [0130]
  • The bit line voltage V[0131] BL at which each bit in the representative portion became programmed is registered and the bit line voltage VBL1 of the fastest bit of the group is stored (step 102). FIG. 13A graphs the bit line voltage VBL (in number of steps) and the number of bits that became programmed at that level. In the example of FIG. 13A, two bits became programmed at level 6, five at level 7, eight at level 8 and 4 at level 9.
  • Level [0132] 6 is the lowest programming level and is thus, the bit line voltage VBL1 of the fastest bits (i.e. the bits programmed in six, rather than seven, eight or nine, steps). Thus, as Applicants have realized, all bits of the representative portion could begin the programming procedure at level 6. In such a case, the fastest bits would be programmed in one step while the others would be programmed in two, three or four steps.
  • Since the portion was only a representative portion and the array could include bits that program even faster, in step [0133] 104, the dial-in level DI is set to X levels lower than the fastest bit line voltage VBL1, where X can be any reasonable margin, such as two or three levels. FIG. 13A shows (with arrow 106) setting the dial-in level DI to two levels lower than the stored bit line voltage VBL1.
  • The rest of the array is now programmed (step [0134] 108), starting at the dial-in level DI. FIGS. 13B, 13C, 13D and 13E show four possible results. Since, in the four figures, the programming procedure begins at the dial-in level (the fourth original programming level), the first programming level in FIGS. 13B-13E is aligned with the fourth programming level of FIG. 13A. For all figures, the new bit line voltage VBL2 of the fastest bit is found in step 110.
  • In FIG. 13B, the fastest bits are as fast as the fastest ones in the representative portion and thus, program at the third programming level (which is equivalent to the old sixth programming level). In FIG. 13C the fastest bits program in two steps, and thus, are faster than those in the representative portion. In both cases, the dial-in level DI is changed (step [0135] 112) to the fastest bit line voltage VBL2. In FIG. 13D, however, the fastest level is above the third programming level (as checked in step 114), meaning that the fastest bits in the remainder of the array are slower than those of the representative portion. In this case, the dial-in level DI is kept at the first fast programming level, VBL1.
  • In FIG. 13E, the fastest programming level is the first one. This situation is inconclusive. It is possible that the fastest bit can program at an even lower programming level. The system now has a choice (steps [0136] 114 and 115); it can set the dial-in level DI to this first programming level, it can repeat the whole process from step 104, setting the preliminary dial-in level DI to lower than this level was previously, or it can decide to fail the part.
  • For the remaining situations (i.e. all but that of FIG. 13E), the dial-in level DI is modified (step [0137] 112) to the either VBL1 or VBL2, whichever is lowest. If desired, DI may be set to a lower level since the conditions during the test are not likely to match the expected conditions of operation. For example, the test may be performed at a fixed temperature while the product may be operated at lower or higher temperatures.
  • FIGS. 13B, 13C and [0138] 13D show that, by beginning the programming levels at a higher level than that of the original of FIG. 13A, the number of programming steps and thus, the programming time, is reduced. It should be noted that the first original steps cannot be omitted since, in some cases, the dial-in level DI may fall on the initial steps.
  • In step [0139] 113 (FIG. 12), the dial-in level DI is set to Y levels lower than the level set in step 112, where Y can be any reasonable margin to accommodate for temperature and cycling. For example, Y can be one or two levels below the value found in step 112.
  • It will be appreciated that other methods of finding an initial dial-in level which ensure that the first programming level is close to the programming level of the fastest bit of the array are possible and are incorporated into the present invention. For example, the entire array can be programmed and the fastest programming level chosen. Alternatively, a two stage method such as described above can be performed but the second stage can be performed on the entire array rather than all but the representative portion. [0140]
  • Furthermore, the operation described hereinabove can be performed at other times during the life of the array, such as when so instructed by a user or by automatic built-in procedures. [0141]
  • Finally, occasionally it might be desired to determine the dial-in level DI quickly or roughly. In this case, only the representative portion is utilized and the dial-in level DI is set to the first fastest programming level V[0142] BL1 or, if desired, even higher. This choice may be adequate if fast programming is required.
  • It will be appreciated that the method of changing the dial-in level generally improves yield since the initial programming pulses that hardly change the state of the bits are eliminated. Each programming pulse above the dial-in level is generally more effective and thus, most of the bits will not fail to program (a cause of reduced yield). [0143]
  • It will be appreciated that the method of changing the dial-in level, described hereinabove for programming, may also be utilized for erasing. Reference is now made to FIGS. 14A and 14B which, together, illustrate an exemplary method for dial-in for erasure. The basic method is similar to that of programming except that, in erasure, both the gate and the drain voltage levels may be set. This is shown in FIG. 14. Alternatively, only the drain voltage level can be set. [0144]
  • Furthermore, only the representative portion is considered. In one embodiment, the dial-in level DI of the gate or the drain is then set to a voltage level slightly below the voltage level of the slowest bit (to force the erase procedure to perform at least two erase pulses). [0145]
  • In step [0146] 120, the drain voltage Vppd is set to its lowest level for erasure. In step 122, the gate voltage level is set to the least negative voltage possible for erasure.
  • In step [0147] 124, one or more representative bytes are programmed and, in step 126, a single erase pulse is provided. An erase verify operation is performed in step 128 and the results checked in step 130.
  • If all of the bits which were programmed are now fully erased (i.e. the erase is fully verified), then either this occurred after the first loop (i.e. the gate is at its least negative level) or it occurred at some other point. This is checked in step [0148] 131. If the erasure occurred after the first loop (through steps 124-130), then the process was too successful and an error flag is set (step 133). Either the array can then be thrown away or the length of the erase pulse can be shortened and the process repeated.
  • If erasure is successful with a somewhat lower gate voltage, the gate voltage level for dial-in is set (step [0149] 132), as is the drain voltage Vppd for dial-in (step 135), and the process finishes in step 154. In one embodiment, the gate voltage level for dial-in can be set to one level less negative than the current level. Other embodiments include setting the gate voltage for dial-in to the level found in this process or for setting it to Z levels less negative than the current level.
  • If the erase verify (of step [0150] 130) was not successful, the gate voltage level is made more negative (step 134). As long as the gate voltage has not reached its most negative level (checked in step 136), the process of steps 124 through 130 is repeated with the new gate voltage level.
  • If the gate voltage has reached its most negative level without successfully erasing all of the programmed bits, then the process continues with steps [0151] 138-148 by changing the drain voltage level. The gate level is set at this point to its most negative voltage level.
  • In step [0152] 138, the gate voltage is set to its most negative level. As in the previous section, in step 140, one or more representative bytes are programmed. However, in this section, the drain voltage is raised (step 142), after which, in step 144, a single erase pulse is provided. An erase verify operation is performed in step 146 and the results checked in step 148.
  • If the all of the bits are now erased, the drain voltage Vppd for dial-in is set (step [0153] 152) and the process finished (step 154). As for the gate level, in one embodiment, the drain voltage Vppd for dial-in can be set to one level lower than the current level. Other embodiments include setting the drain voltage for dial-in to the level found in this process or for setting it to Z1 levels lower than the current level.
  • If the bits are not yet fully erased, the process of steps [0154] 140-148 is repeated until a maximum drain voltage is reached, as checked by step 150. If the maximum drain voltage is reached and the bits have not been erased, then the array cannot be erased in one pulse. An error flag is set (step 156) and the process finished. At this point, the array may either be thrown away, the process of FIG. 14 may be repeated using two or more erase pulses in steps 126 and 144 or the duration of the erase pulse may be made longer.
  • As mentioned hereinabove, the dial-in level may also be determined by changing only the drain voltage Vppd (i.e. steps [0155] 120, 122 and 138-152).
  • Even with the dial-in level described hereinabove with respect to FIGS. 12, 13 and [0156] 14, some of the bits may still take many programming or erase pulses before becoming programmed or erased, respectively, and the number of pulses needed may vary depending on operating conditions.
  • Typically, the bit line programming levels increase in voltage by predetermined amounts. Reference is now made to FIGS. 15 and 16 which illustrate a further embodiment of the present invention which changes the incremental voltage level of the drain Vppd between pulses in order to program most of the bits in as few programming steps as possible. As described hereinbelow, the incremental voltage level is adapted to the current response of the bit to programming pulse. [0157]
  • Bits respond to programming in different ways. When given a programming pulse, the threshold voltage of some may increase significantly (see arrow [0158] 160 of FIG. 15) while the threshold voltage of others may only increase slightly (see arrow 162). The former bit requires only one more programming pulse (arrow 164) until it becomes programmed (i.e. until its threshold voltage is larger than a “program verify” voltage level). The latter type of bit must have multiple programming pulses (labeled 1-8) until it becomes programmed.
  • A bit that takes a significant number of programming pulses takes a long time to program and may limit the overall product performance. Applicants have realized that, if the threshold voltage level after a programming pulse is measured, it is possible to adjust the voltage level increment of the next programming pulse to move the threshold level toward the program verify level more quickly. This is illustrated in FIG. 16 in which multiple verify levels, labeled verify 1, verify 2, verify 3 and verify 4, are shown. It will be appreciated that the present invention includes having multiple verify levels and that the four levels are shown for purposes of clarity only. The number of verify levels is a design choice and any number greater than one is included in the present invention. It will also be appreciated that existing reference levels in the array can be used to provide the multiple verify levels. [0159]
  • During the program verify operation, after a programming pulse, the threshold voltage level of the bit is compared to five voltage levels, that of verify 1, verify 2, verify 3, verify 4 and program verify to determine how close to fully programmed the bit is. [0160]
  • Consider the two bits shown in FIG. 16 (the first one with solid lines and the second one with dashed lines). In the first example, the first programming pulse brings the threshold voltage level of the first bit almost to the verify 3 level (this pulse is labeled [0161] 170A). The output of the comparisons will be that the threshold voltage level is above the verify 1 and verify 2 levels but not above the verify 3, verify 4 and program verify levels. The threshold level of the bit is thus above the verify 2 level.
  • For the second bit, the first programming pulse (here labeled [0162] 170B) brings the threshold voltage level to above the verify 1 level. Only the verify 1 comparison will indicate that the threshold level is above it; all the remaining comparisons will be that the threshold level of the bit is below the comparison level. Thus, the threshold level for the second exemplary bit is above the verify 1 level.
  • It will be appreciated that the comparison operations can be performed together or serially. If performed serially, from the program verify level down to the verify 1 level, then-the comparison operation ends once the threshold level of the bit is above the current comparison level. [0163]
  • Typically, a group of bits, such as a byte, are programmed together. The verify operation described hereinabove is performed for the group of bits and the bit having the highest verify level is then used to determine the size of the next programming pulse. [0164]
  • Each verify level has a different voltage level increment associated therewith, depending on how far away the verify level is from the program verify level. The closer the verify level is to the program verify level, the smaller the increment to the drain voltage Vppd. The size of the increment depends on the average transfer function between the change ΔV[0165] PPD in bit line voltage and the resultant change ΔVτ in threshold level and is typically determined by experimentation. In addition to depending on the change ΔVPPD, it can also depend on the level of the bit line voltage itself.
  • In one example, the verify 4 level is 250 mV less than the program verify level. For this example, the increment in bit line voltage level, ΔV[0166] PPD, for a bit which is above the verify 4 level but below the program verify level is be about 300 mV. Table 1 gives an example of voltage levels for the verify levels and their associated incremental voltage levels for the example of FIG. 16.
    TABLE 1
    How much the reference
    level is less than the
    Verify Name program verify Level (mV) ΔVPPD (mV)
    Program Verify 0 0
    Verify 4 −250 300
    Verify 3 −500 600
    Verify 2 −750 900
    Verify 1 −1000 1200
  • It will be appreciated that the size of the increment is a tradeoff. If the minimum number of programming pulses is required, then the increment should be designed to bring a bit to fully programmed from whatever threshold voltage level it is at. Alternatively, if a minimum amount of overprogramming is desired, then the increment should be designed to bring a bit to just under the program verify level. The latter method requires that a further small increment programming pulse be performed in order to bring the bit above the program verify level. However, the latter method generally will not overprogram the bits. [0167]
  • The process is repeated until one or more bits are fully programmed, at which point they no longer receive programming pulses. The bit with the next highest threshold level defines the increment for the next programming pulse. FIG. 16 shows this process. The first programming pulse [0168] 170 brought the first bit to above the verify 2 level, so the voltage level of the second programming pulse 174 is set to be large enough to bring the first bit to the program verify level. In this case, the second pulse was not quite large enough (arrow 174A does not quite reach the program verify level) and a third pulse 176 was necessary (arrow 176A is above the program verify level).
  • For the second bit, second pulse [0169] 174 brings the threshold level above the verify 3 level (arrow 174B) and the third pulse brings the threshold level above the verify 4 level (arrow 176B). At this point, the second bit is the highest bit and its verify 4 level defines the increment for the fourth programming pulse, labeled 178, after which the second bit is fully programmed.
  • It will be appreciated that the present invention can also be utilized for erasure, as shown in FIG. 17, to which reference is now made. [0170]
  • Reference is now made to FIG. 17, which illustrates an exemplary method for multiple pulse erasure. In step [0171] 180, the block to be erased is read and, in step 182, its erase state is checked. If all of the bits of the block are erased already, the process is finished (step 204).
  • If the block requires further erasure, an erase pulse is provided (step [0172] 184), typically with predefined gate and drain voltages, such as those defined in the dial-in process of FIG. 14. Other predefined gate and drain voltages are also possible.
  • In steps [0173] 186-194, the read level is decreased from the program verify level (i.e. the level of fully programmed bits) towards the erase verify level (i.e. fully erased) to determine how much erasure has occurred and how much more needs to occur.
  • Specifically, in step [0174] 186, the read voltage level is set to the program verify (PV) level and the block is read (step 188). If all of the bits of the block pass the read operation, as checked in step 190, the read voltage level is reduced (step 194) as long as it has not yet reached the erase verify level (as checked in step 192).
  • If the read operation is successful at the erase verify level, then the block has been fully erased and the process finishes in step [0175] 204. However, if the read operation fails at some point, the drain voltage level Vppd is increased (step 196), for example, according to Table 2, another erase pulse is provided (step 200) using the new drain voltage level Vppd and the process is repeated from step 186. Step 198 checks that the number of erase pulses has not exceeded a maximum. If it has, then an error flag is set (step 202) and the process is stopped (step 204).
    TABLE 2
    Reference Level above the
    Verify Name Erase Verify Level (mV) ΔVPPD (mV)
    Program Verify 950 +1000
    Verify 2 700 +750
    Verify 1 400 +500
    Erase Verify 0 0
  • It is noted that Table 2 has only four verify levels while Table 1, for programming, has five verify levels. The number of verify levels are set by a designer according to any appropriate set of design considerations. [0176]
  • The multiple verify levels of FIG. 16 are typically defined by the voltage level on or the current produced by a reference cell. Such reference cells may form sections of the memory array or they may be located outside of the memory array. In either embodiment, the reference cell has a known and predefined set of characteristics which ensure that the voltage or current it produces when it receives a predefined set of gate, drain and source voltages is generally precise and reliable. [0177]
  • A reference cell can either be unprogrammed or programmed. If the latter, the programming level should be well-defined to ensure that the reference cell has the desired characteristics. In contrast to programming an array cell, which should be programmed as fast as possible, programming a reference cell should be done as accurately as possible to ensure that the final threshold voltage Vt is at the desired level. [0178]
  • Reference is now made to FIGS. 18A, 18B, [0179] 19A, 19B, 19C, 19D, 20A, 20B and 21, which illustrate a method of programming reference cells in an NROM array. FIG. 18A indicates the target threshold voltage (Vt) levels for various reference cells, FIG. 18B is similar to FIG. 16 and generally illustrates the operation of programming an exemplary reference cell, FIGS. 19A, 19B, 19C and 19D are a series of timing diagrams (similar to FIGS. 11A-11C) of the programming algorithm for reference cells, FIGS. 20A and 20B illustrate the evolution of the threshold voltage of two reference cells and FIG. 21 provides an exemplary method in flow chart format.
  • FIG. 18A shows some exemplary target threshold voltage Vt levels of reference cells to be programmed on a Vt axis. In this figure, five target Vt levels for five different reference cells are shown (erase verify (EV), verify 1, verify 2, verify 3 and program verify (PV)) as is the initial distribution of threshold voltages of the native cells (i.e. prior to any programming). The threshold voltage of each reference cell must be brought to one of these target levels in order for them to act as reference levels for the array. [0180]
  • In the present invention and as shown in FIG. 18B, the reference cells are programmed in two stages, a fast stage [0181] 206 and a slow stage 208. FIG. 18B illustrates the operation for one reference level, verify 3. Fast stage 206 first moves the threshold voltage Vt of the reference cell from an initial threshold voltage 207 to the vicinity of an interim target level 209 that is below and close to the desired final target level (i.e. verify 3), where close may be, for example, within 300 mV. Then, the slow stage 208 ‘creeps’ toward the final target level to ensure that, if the final target level is passed, it is passed by only a very small margin. This ensures the accuracy in the final level of the reference threshold voltage Vt.
  • FIG. 18B shows also one example of the threshold voltage evolution when the cell is programmed according to one embodiment of the present invention. The threshold voltage Vt begins at initial level [0182] 207. The final target Vt of the cell is the verify 3 level, but the interim target Vt level for the fast stage is below it, (e.g. verify 3-X, where X may be 300 mV). Fast stage 206 has three programming pulses. A first pulse results in a Vt increment 210, a second pulse results in a Vt increment 212 and a third pulse results in a Vt increment 214, after which, the threshold voltage level is slightly above the interim level 209. It is noted that, in the fast stage, each programming pulse applied to the reference cell produces relatively large increments in its threshold voltage.
  • Once the interim level [0183] 209 has been passed, the method changes to the slow stage 208. At this point, the method provides pulses which produce much smaller increments 216, per programming pulse, in the threshold voltage of the reference cell. Thus, even if the threshold voltage after one of the small pulses is only very slightly under the final target level (i.e. verify 3 in the example), the next pulse, which brings the threshold voltage above the final target level, will not surpass it by more than the small threshold voltage increment 216. The reference cells thus have programmed threshold voltage levels whose accuracy is within the size of the small increment 216 in threshold voltage provided by the slow stage pulses.
  • Programming in fast stage [0184] 206 is performed as discussed hereinabove; i.e. the drain voltage level VBL is stepped (as can be seen in FIG. 19A), providing an increased voltage level for each consecutive programming pulse. At the same time, the gate voltage level is relatively high (typically 7 to 10V), and the source is grounded (usually through a few conducting transistors). The target threshold voltage Vt level of the fast programming stage is the interim threshold voltage level. The interim threshold voltage level is predetermined based on the known accuracy level of the fast programming stage and on the expected Vt increment after each programming pulse at this stage. After each programming pulse, the threshold voltage level of the reference cell is measured, as described in a U.S. Patent Application to be filed on the same day herewith (attorney docket No. 2671/01011), entitled “Method For Programming a Reference Cell”, assigned to the common assignees of the present invention and incorporated in its entirety herein. Other methods of measuring the threshold voltage level of the reference cell are possible and are incorporated herein.
  • When the threshold voltage level reaches the interim target level, the method changes to slow stage [0185] 208.
  • In slow stage [0186] 208, the drain voltage level VBL is not changed between pulses. Typically, the gate, drain and source voltage levels are fixed and the same programming conditions remain until the cell achieves its final target level. However, the gate voltage and pulse duration can be altered, if necessary. Typically, the drain voltage level VBL, is set to a level lower than it was for the last step of fast stage 206. FIG. 19A shows as an example that drain voltage level VBL is set to two levels lower than the last pulse of the fast stage. The gate voltage Vg can remain the same as shown in FIG. 19C, or lowered. If desired, and as shown in FIG. 19D, the pulse duration can be changed.
  • It will be appreciated that the programming conditions for slow stage [0187] 208 should be such that the expected incremental threshold voltage level is significantly smaller than that for fast stage 206. For example, if fast stage 206 has an expected incremental threshold voltage level of at least 200-300 mV, slow stage 208 might have an expected incremental threshold voltage level of 10-50 mV.
  • It will also be appreciated that the interim target level should be placed XmV below the final target level, where X is the expected incremental threshold voltage level of fast stage [0188] 206 when approaching the target Vt, and in general, ranges between 100-400 mV.
  • FIG. 20A is a graph of the threshold voltage Vt evolution when programming the cell during fast stage [0189] 206 and FIG. 20B is a graph of the threshold voltage Vt evolution when programming the cell during slow stage 208. FIG. 20A graphs the threshold voltage versus drain voltage VBL while FIG. 20B graphs threshold voltage over time.
  • In both figures, two curves are shown, illustrating the results for two different cells. Both cells have an interim target level of 2.0V for the fast programming stage; however, they exceeded that level with different bit line voltage levels. In the first stage, both curves ([0190] 220A and 222A) initially change very slowly and then, when provided a programming pulse with a drain voltage VBL of about 4V, the threshold voltages start to change significantly (on the order of 100 mV Vt increase per 100 mV VBL increase). At 4.4V and 4.6V, respectively, the cells achieve their interim target level and the programming method switches to slow stage 208 (shown in FIG. 20B).
  • In this example, the bit line voltages are reduced (from 4.4V to 4.2V and from 4.6V to 4.4V, respectively), and then maintained at that level for the slow stage [0191] 208. In this example, the duration of the programming pulses is also fixed. As can be seen in FIG. 20B, both curves 220B and 222B slowly increase in threshold voltage until reaching the final threshold voltage of 2.4V. As can be seen, the consecutive programming pulses at the fixed conditions in this stage provide smaller and smaller increments in the threshold voltages of the cells. When approaching the final target level, each programming pulse provides an increase of no more than about 40 mV in threshold voltage.
  • FIG. 21 illustrates an exemplary embodiment of the method in which two gate voltages, 7.5V and 9V, are used, where the higher gate voltage causes programming to occur faster and should only be used if it is known that the reference cell or group of cells cannot be programmed using the lower voltage level. [0192]
  • A few reference cells can be programmed together or they can be programmed one after the other. The latter operation uses its knowledge of the conditions used to program the previous cells. The initial set of programming voltages are set (step [0193] 221) to the lowest gate voltage (Vg=7.5V) and the lowest drain voltage (VBL=lowest). In step 223, the pulse is applied, where the pulse is in the range of a few μs long, such as 1 μs long.
  • The voltage level of the current reference cell is checked (step [0194] 224) to determine if it is within XmV of the desired final target level, where X is 200 mV for this example. If it has not achieved the interim target level (i.e. if it has not been verified), the drain voltage VBL is raised by one step (step 226) as long as it is not already at the highest drain voltage level (checked in step 228). If the drain voltage VBL cannot be increased, then the gate voltage Vg is raised (step 230) to 9V and the drain voltage VBL is lowered, to either its lowest level or by a significant number of steps, such as 4. The next pulse is applied (step 223) and the process repeated until the threshold voltage Vt is above the interim target level (in step 224).
  • Now that the threshold voltage Vt is close to the desired level, the drain voltage V[0195] BL can be lowered (step 232) by a few steps, such as 2 or 1, and a count is set. The next pulse is applied (step 234) and the threshold voltage level of the current reference cell is checked (step 236) against the desired level. If the threshold voltage level has not achieved the desired level, the count is increased (step 238), a check is made that the count has not yet reached its maximum level (step 240) and the next pulse provided (step 234). If the count reaches its maximum, an error is issued (step 242). This counter improves quality as it will screen out arrays whose reference cells have abnormal characteristics.
  • If the reference cell has reached the desired threshold voltage level, the process continues for the next reference cell (checked in step [0196] 244), or ends (step 246) if no more reference cells must be processed.
  • For the current reference cell, the programming conditions are recorded (step [0197] 250) and the next reference cell selected. The programming conditions of the previous reference cell can be utilized. In step 252, the gate voltage Vg is set to the lower value (Vg=7.5V) and the drain voltage VBL is lowered by 1 or 2 steps. The process then proceeds to step 223 and a pulse is applied. The remaining operations are the same for all reference cells.
  • The methods and apparatus disclosed herein have been described without reference to specific hardware or software. Rather, the methods and apparatus have been described in a manner sufficient to enable persons of ordinary skill in the art to readily adapt commercially available hardware and software as may be needed to reduce any of the embodiments of the present invention to practice without undue experimentation and using conventional techniques. [0198]
  • It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow: [0199]

Claims (16)

  1. 1. A method for programming a reference cell of a memory array, the method using programming pulses, the method comprising the steps of:
    if a threshold voltage of said reference cell is below an interim target level, raising a drain voltage for a next programming pulse, otherwise, setting said drain voltage for the next programming pulse at a fixed level not higher than a current level; and
    providing programming pulses using said fixed drain voltage level until said threshold voltage level is at or above a final target level above said interim target level.
  2. 2. A method according to claim 1 wherein for said step of providing, said programming pulses have a different duration than said programming pulse for said step of raising.
  3. 3. A method according to claim 1 wherein said interim target level is in the range of 100-400 mV below said final target level.
  4. 4. A method according to claim 1 wherein said interim target level is below said final target level by an amount generally not smaller than an expected threshold voltage change due to said programming pulses of said raising step.
  5. 5. A method according to claim 1 and also comprising the step of measuring said programmed threshold voltage level after each programming pulse.
  6. 6. A method according to claim 1 and also comprising the step of determining after each programming pulse if the programmed threshold voltage is above or below the target level.
  7. 7. A method for programming a reference cell of a memory array, the method comprising:
    fast programming of said reference cell until a threshold voltage level of said reference cell is above an interim target level; and
    slow programming of said reference cell until said threshold voltage level is above a final target level which is above said interim target level.
  8. 8. A method according to claim 7 wherein said fast programming comprises providing programming pulses and changing a drain voltage level between programming pulses.
  9. 9. A method according to claim 7 wherein said slow programming comprises maintaining a generally constant drain voltage level between programming pulses.
  10. 10. A method according to claim 7 wherein said interim target level is below said final verify level by an amount generally not smaller than the expected threshold voltage change due to said programming pulses of said fast programming step.
  11. 11. A method according to claim 7 wherein said steps of programming include providing programming pulses and also comprising the step of measuring said threshold voltage level of said reference cell after each programming pulse.
  12. 12. A method for programming a reference cell of a memory array, the method comprising the steps of:
    programming said reference cell with large programming steps until a threshold voltage level of said reference cell is above an interim target level; and
    programming said reference cell with small programming steps until said threshold voltage level is above a final target level.
  13. 13. A method according to claim 12 wherein said programming with large programming steps comprises providing programming pulses and changing a drain voltage level between programming pulses.
  14. 14. A method according to claim 12 wherein said programming with small programming steps comprises maintaining a generally constant drain voltage level between programming pulses.
  15. 15. A method according to claim 12 wherein said interim target level is below said final verify level by an amount generally not smaller than an expected threshold voltage change due to said large programming steps.
  16. 16. A method according to claim 12 wherein said steps of programming include providing programming pulses and also comprising the step of measuring said threshold voltage level of said reference cell after each programming pulse.
US10300924 2000-05-04 2002-11-21 Programming and erasing methods for a reference cell of an NROM array Abandoned US20040027871A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09563923 US6396741B1 (en) 2000-05-04 2000-05-04 Programming of nonvolatile memory cells
US09730586 US6928001B2 (en) 2000-12-07 2000-12-07 Programming and erasing methods for a non-volatile memory cell
US09827596 US6490204B2 (en) 2000-05-04 2001-04-05 Programming and erasing methods for a reference cell of an NROM array
US10300924 US20040027871A1 (en) 2000-05-04 2002-11-21 Programming and erasing methods for a reference cell of an NROM array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10300924 US20040027871A1 (en) 2000-05-04 2002-11-21 Programming and erasing methods for a reference cell of an NROM array

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09827596 Continuation US6490204B2 (en) 2000-05-04 2001-04-05 Programming and erasing methods for a reference cell of an NROM array

Publications (1)

Publication Number Publication Date
US20040027871A1 true true US20040027871A1 (en) 2004-02-12

Family

ID=27112077

Family Applications (2)

Application Number Title Priority Date Filing Date
US09827596 Expired - Fee Related US6490204B2 (en) 2000-05-04 2001-04-05 Programming and erasing methods for a reference cell of an NROM array
US10300924 Abandoned US20040027871A1 (en) 2000-05-04 2002-11-21 Programming and erasing methods for a reference cell of an NROM array

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09827596 Expired - Fee Related US6490204B2 (en) 2000-05-04 2001-04-05 Programming and erasing methods for a reference cell of an NROM array

Country Status (4)

Country Link
US (2) US6490204B2 (en)
EP (1) EP1225596B1 (en)
JP (1) JP2002319289A (en)
DE (1) DE60126582D1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030123290A1 (en) * 2000-12-15 2003-07-03 Halo Lsi, Inc. Fast program to program verify method
US20060291287A1 (en) * 2005-06-03 2006-12-28 Interuniversitair Microelektronica Centrum (Imec) Method for operating a non-volatile charge-trapping memory device and method for determining programming/erase conditions
US20080002464A1 (en) * 2004-12-09 2008-01-03 Eduardo Maayan Non-volatile memory device and method for reading cells
US7933153B2 (en) 2005-06-03 2011-04-26 Imec Method for extracting the distribution of charge stored in a semiconductor device

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7366020B2 (en) * 1999-07-28 2008-04-29 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof
US6914827B2 (en) * 1999-07-28 2005-07-05 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
JP2002208293A (en) * 2001-01-11 2002-07-26 Oki Electric Ind Co Ltd Semiconductor memory
US6584017B2 (en) * 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
JP3987715B2 (en) * 2001-12-06 2007-10-10 富士通株式会社 Program voltage control method of a nonvolatile semiconductor memory and the nonvolatile semiconductor memory
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US7190620B2 (en) 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6693828B1 (en) * 2002-04-23 2004-02-17 Alta Analog, Inc. Method for compensating field-induced retention loss in non-volatile storage with reference cells
JP2003346484A (en) * 2002-05-23 2003-12-05 Mitsubishi Electric Corp Nonvolatile semiconductor storage device
US6804136B2 (en) * 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US7193893B2 (en) * 2002-06-21 2007-03-20 Micron Technology, Inc. Write once read only memory employing floating gates
US7154140B2 (en) 2002-06-21 2006-12-26 Micron Technology, Inc. Write once read only memory with large work function floating gates
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US7847344B2 (en) 2002-07-08 2010-12-07 Micron Technology, Inc. Memory utilizing oxide-nitride nanolaminates
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6891752B1 (en) 2002-07-31 2005-05-10 Advanced Micro Devices System and method for erase voltage control during multiple sector erase of a flash memory device
US6826107B2 (en) 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6873550B2 (en) 2003-08-07 2005-03-29 Micron Technology, Inc. Method for programming and erasing an NROM cell
US6954393B2 (en) * 2003-09-16 2005-10-11 Saifun Semiconductors Ltd. Reading array cell with matched reference cell
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7177199B2 (en) 2003-10-20 2007-02-13 Sandisk Corporation Behavior based programming of non-volatile memory
US6961267B1 (en) * 2003-12-16 2005-11-01 Advanced Micro Devices, Inc. Method and device for programming cells in a memory array in a narrow distribution
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7366025B2 (en) 2004-06-10 2008-04-29 Saifun Semiconductors Ltd. Reduced power programming of non-volatile cells
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7242618B2 (en) 2004-12-09 2007-07-10 Saifun Semiconductors Ltd. Method for reading non-volatile memory cells
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7187589B2 (en) * 2005-05-11 2007-03-06 Infineon Technologies Flash Gmbh & Co. Kg Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) * 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US7656710B1 (en) 2005-07-14 2010-02-02 Sau Ching Wong Adaptive operations for nonvolatile memories
JP2007027760A (en) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd High density nonvolatile memory array and manufacturing method
KR100704033B1 (en) * 2005-08-05 2007-04-04 삼성전자주식회사 Chrge trap type nonvolatile semiconductor memory device having three-level memory cells and operating method therefor
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7342833B2 (en) * 2005-08-23 2008-03-11 Freescale Semiconductor, Inc. Nonvolatile memory cell programming
US8116142B2 (en) * 2005-09-06 2012-02-14 Infineon Technologies Ag Method and circuit for erasing a non-volatile memory cell
US7301817B2 (en) 2005-10-27 2007-11-27 Sandisk Corporation Method for programming of multi-state non-volatile memory using smart verify
US7366022B2 (en) * 2005-10-27 2008-04-29 Sandisk Corporation Apparatus for programming of multi-state non-volatile memory using smart verify
US20070153495A1 (en) * 2005-12-29 2007-07-05 Wang Michael Dongxue Illumination mechanism for mobile digital imaging
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US20080205140A1 (en) * 2007-02-26 2008-08-28 Aplus Flash Technology, Inc. Bit line structure for a multilevel, dual-sided nonvolatile memory cell array
US7830713B2 (en) * 2007-03-14 2010-11-09 Aplus Flash Technology, Inc. Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
US7599224B2 (en) 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7508715B2 (en) 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7853841B2 (en) * 2007-10-29 2010-12-14 Micron Technology, Inc. Memory cell programming
US7924628B2 (en) * 2007-11-14 2011-04-12 Spansion Israel Ltd Operation of a non-volatile memory array
US7945825B2 (en) * 2007-11-25 2011-05-17 Spansion Isreal, Ltd Recovery while programming non-volatile memory (NVM)
KR101437102B1 (en) * 2008-01-08 2014-09-05 삼성전자주식회사 Memory device and method of estimation of characteristic of multi-bit cell
US7808833B2 (en) * 2008-01-28 2010-10-05 Qimonda Flash Gmbh Method of operating an integrated circuit, integrated circuit and method to determine an operating point
WO2010024883A1 (en) * 2008-08-25 2010-03-04 Halo Lsi, Inc Complementary reference method for high reliability trap-type non-volatile memory
JP4720912B2 (en) 2009-01-22 2011-07-13 ソニー株式会社 Resistance-change memory device
US8982636B2 (en) * 2009-07-10 2015-03-17 Macronix International Co., Ltd. Accessing method and a memory using thereof
JP6101369B2 (en) * 2013-03-15 2017-03-22 シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc. Self-timer of the sense amplifier in the memory device
DE102014115885B4 (en) * 2014-10-31 2018-03-08 Infineon Technologies Ag Functioning state of non-volatile memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812457A (en) * 1996-09-09 1998-09-22 Sony Corporation Semiconductor NAND type flash memory with incremental step pulse programming
US5926409A (en) * 1997-09-05 1999-07-20 Information Storage Devices, Inc. Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application
US5949714A (en) * 1994-09-17 1999-09-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US6064591A (en) * 1996-04-19 2000-05-16 Kabushiki Kaisha Toshiba Memory system
US6075724A (en) * 1999-02-22 2000-06-13 Vantis Corporation Method for sorting semiconductor devices having a plurality of non-volatile memory cells
US6118692A (en) * 1991-02-08 2000-09-12 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell

Family Cites Families (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1297899A (en) 1970-10-02 1972-11-29
US3895360A (en) 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4016588A (en) 1974-12-27 1977-04-05 Nippon Electric Company, Ltd. Non-volatile semiconductor memory device
US4017888A (en) 1975-12-31 1977-04-12 International Business Machines Corporation Non-volatile metal nitride oxide semiconductor device
US4151021A (en) 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US4173766A (en) 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory cell
US4173791A (en) 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory array
DE2832388C2 (en) 1978-07-24 1986-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
US4360900A (en) 1978-11-27 1982-11-23 Texas Instruments Incorporated Non-volatile semiconductor memory elements
DE2923995C2 (en) 1979-06-13 1985-11-07 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
WO1981000790A1 (en) 1979-09-13 1981-03-19 Ncr Co Silicon gate non-volatile memory device
DE2947350A1 (en) 1979-11-23 1981-05-27 Siemens Ag Process for the manufacture of MNOS memory transistors with very short kanallaenge in silicon-gate technology
JPS56120166A (en) 1980-02-27 1981-09-21 Hitachi Ltd Semiconductor ic device and manufacture thereof
US4380057A (en) 1980-10-27 1983-04-12 International Business Machines Corporation Electrically alterable double dense memory
US4521796A (en) 1980-12-11 1985-06-04 General Instrument Corporation Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device
US4527257A (en) 1982-08-25 1985-07-02 Westinghouse Electric Corp. Common memory gate non-volatile transistor memory
US4769340A (en) 1983-11-28 1988-09-06 Exel Microelectronics, Inc. Method for making electrically programmable memory device by doping the floating gate by implant
JPS60182174A (en) 1984-02-28 1985-09-17 Nec Corp Non-volatile semiconductor memory
GB2157489A (en) 1984-03-23 1985-10-23 Hitachi Ltd A semiconductor integrated circuit memory device
US4667217A (en) 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US4742491A (en) 1985-09-26 1988-05-03 Advanced Micro Devices, Inc. Memory cell having hot-hole injection erase mode
JPH0828431B2 (en) 1986-04-22 1996-03-21 日本電気株式会社 A semiconductor memory device
US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US4780424A (en) 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US4870470A (en) 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
JPH07120720B2 (en) 1987-12-17 1995-12-20 三菱電機株式会社 Nonvolatile semiconductor memory device
US5159570A (en) 1987-12-22 1992-10-27 Texas Instruments Incorporated Four memory state EEPROM
US5268870A (en) 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US4941028A (en) 1988-08-10 1990-07-10 Actel Corporation Structure for protecting thin dielectrics during processing
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
DE69033438D1 (en) * 1989-04-13 2000-03-02 Sandisk Corp Replacement of faulty memory cells of a EEprommatritze
US5104819A (en) 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5075245A (en) 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
US5289406A (en) 1990-08-28 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Read only memory for storing multi-data
JP2612969B2 (en) 1991-02-08 1997-05-21 シャープ株式会社 A method of manufacturing a semiconductor device
US5424567A (en) 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication
JP3109537B2 (en) 1991-07-12 2000-11-20 日本電気株式会社 A read-only semiconductor memory device
JP2965415B2 (en) 1991-08-27 1999-10-18 松下電器産業株式会社 A semiconductor memory device
DK0740854T3 (en) 1991-08-29 2003-08-18 Hyundai Electronics Ind Self-aligned dual-bit split gate (DSG) flash EEPROM cell
KR960013022B1 (en) 1991-09-11 1996-09-25 토자기 시노부 Semiconductor integrated circuit
US5175120A (en) 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
JPH05110114A (en) 1991-10-17 1993-04-30 Rohm Co Ltd Nonvolatile semiconductor memory device
JP3358663B2 (en) 1991-10-25 2002-12-24 ローム株式会社 The semiconductor memory device and the stored information reading method
US5260593A (en) 1991-12-10 1993-11-09 Micron Technology, Inc. Semiconductor floating gate device having improved channel-floating gate interaction
US5293328A (en) 1992-01-15 1994-03-08 National Semiconductor Corporation Electrically reprogrammable EPROM cell with merged transistor and optiumum area
US5654568A (en) 1992-01-17 1997-08-05 Rohm Co., Ltd. Semiconductor device including nonvolatile memories
US5324675A (en) 1992-03-31 1994-06-28 Kawasaki Steel Corporation Method of producing semiconductor devices of a MONOS type
EP0597124B1 (en) 1992-05-29 1998-12-09 Citizen Watch Co. Ltd. Method of fabricating a semiconductor nonvolatile storage device
GB9217743D0 (en) 1992-08-19 1992-09-30 Philips Electronics Uk Ltd A semiconductor memory device
US5412238A (en) 1992-09-08 1995-05-02 National Semiconductor Corporation Source-coupling, split-gate, virtual ground flash EEPROM array
US5418743A (en) 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5319593A (en) 1992-12-21 1994-06-07 National Semiconductor Corp. Memory array with field oxide islands eliminated and method
US5436481A (en) 1993-01-21 1995-07-25 Nippon Steel Corporation MOS-type semiconductor device and method of making the same
US5393701A (en) 1993-04-08 1995-02-28 United Microelectronics Corporation Layout design to eliminate process antenna effect
US5350710A (en) 1993-06-24 1994-09-27 United Microelectronics Corporation Device for preventing antenna effect on circuit
US5477499A (en) 1993-10-13 1995-12-19 Advanced Micro Devices, Inc. Memory architecture for a three volt flash EEPROM
US5828601A (en) * 1993-12-01 1998-10-27 Advanced Micro Devices, Inc. Programmed reference
JPH07193151A (en) 1993-12-27 1995-07-28 Toshiba Corp Non-volatile semiconductor storage and its storage method
US5418176A (en) 1994-02-17 1995-05-23 United Microelectronics Corporation Process for producing memory devices having narrow buried N+ lines
US5523972A (en) 1994-06-02 1996-06-04 Intel Corporation Method and apparatus for verifying the programming of multi-level flash EEPROM memory
JP3725911B2 (en) 1994-06-02 2005-12-14 株式会社ルネサステクノロジ Semiconductor device
DE69413960T2 (en) 1994-07-18 1999-04-01 St Microelectronics Srl Non-volatile EPROM and Flash EEPROM memory and process for its preparation
JPH08181284A (en) 1994-09-13 1996-07-12 Hewlett Packard Co <Hp> Protective element nd fabrication therefor
DE4434725C1 (en) 1994-09-28 1996-05-30 Siemens Ag Read-only memory cell arrangement, and processes for their preparation
US5619052A (en) 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device
US5523251A (en) 1994-10-05 1996-06-04 United Microelectronics Corp. Method for fabricating a self aligned mask ROM
US5599727A (en) 1994-12-15 1997-02-04 Sharp Kabushiki Kaisha Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed
DE19505293A1 (en) 1995-02-16 1996-08-22 Siemens Ag Polyvalent only memory cell with improved signal to noise ratio
US5801076A (en) 1995-02-21 1998-09-01 Advanced Micro Devices, Inc. Method of making non-volatile memory device having a floating gate with enhanced charge retention
US5518942A (en) 1995-02-22 1996-05-21 Alliance Semiconductor Corporation Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
KR100187656B1 (en) 1995-05-16 1999-06-01 김주용 Method for manufacturing a flash eeprom and the programming method
US5656513A (en) 1995-06-07 1997-08-12 Advanced Micro Devices, Inc. Nonvolatile memory cell formed using self aligned source implant
DE69528971D1 (en) 1995-06-30 2003-01-09 St Microelectronics Srl Manufacturing method of a circuit containing nonvolatile memory cells and peripheral transistors of at least two different types, and corresponding IC
US5903031A (en) 1995-07-04 1999-05-11 Matsushita Electric Industrial Co., Ltd. MIS device, method of manufacturing the same, and method of diagnosing the same
DE69514790T2 (en) * 1995-07-14 2000-08-03 St Microelectronics Srl A method for setting the threshold voltage of a reference memory cell
JP3424427B2 (en) 1995-07-27 2003-07-07 ソニー株式会社 Non-volatile semiconductor memory device
JP2982670B2 (en) 1995-12-12 1999-11-29 日本電気株式会社 Nonvolatile semiconductor memory device and storing method
US5841441A (en) 1996-01-19 1998-11-24 Virtus Corporation High-speed three-dimensional texture mapping systems and methods
WO2004090908A1 (en) * 1996-06-11 2004-10-21 Nobuyoshi Takeuchi Nonvolatile memory having verifying function
US5793079A (en) 1996-07-22 1998-08-11 Catalyst Semiconductor, Inc. Single transistor non-volatile electrically alterable semiconductor memory device
US5768192A (en) 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
JP2000515327A (en) 1996-08-01 2000-11-14 シーメンス アクチエンゲゼルシヤフト Method of operating a memory cell arrangement
US5870335A (en) 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells
US6028324A (en) 1997-03-07 2000-02-22 Taiwan Semiconductor Manufacturing Company Test structures for monitoring gate oxide defect densities and the plasma antenna effect
US6297096B1 (en) 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US5963412A (en) 1997-11-13 1999-10-05 Advanced Micro Devices, Inc. Process induced charging damage control device
US6020241A (en) 1997-12-22 2000-02-01 Taiwan Semiconductor Manufacturing Company Post metal code engineering for a ROM
KR100327421B1 (en) 1997-12-31 2002-02-22 주식회사 하이닉스반도체 Program system of non-volatile memory device and programming method thereof
US6030871A (en) 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6063666A (en) 1998-06-16 2000-05-16 Advanced Micro Devices, Inc. RTCVD oxide and N2 O anneal for top oxide of ONO film
US6034403A (en) 1998-06-25 2000-03-07 Acer Semiconductor Manufacturing, Inc. High density flat cell mask ROM
US5991202A (en) 1998-09-24 1999-11-23 Advanced Micro Devices, Inc. Method for reducing program disturb during self-boosting in a NAND flash memory
US6282145B1 (en) * 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US6205056B1 (en) * 2000-03-14 2001-03-20 Advanced Micro Devices, Inc. Automated reference cell trimming verify

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118692A (en) * 1991-02-08 2000-09-12 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5949714A (en) * 1994-09-17 1999-09-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US6064591A (en) * 1996-04-19 2000-05-16 Kabushiki Kaisha Toshiba Memory system
US5812457A (en) * 1996-09-09 1998-09-22 Sony Corporation Semiconductor NAND type flash memory with incremental step pulse programming
US5926409A (en) * 1997-09-05 1999-07-20 Information Storage Devices, Inc. Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application
US6075724A (en) * 1999-02-22 2000-06-13 Vantis Corporation Method for sorting semiconductor devices having a plurality of non-volatile memory cells

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030123290A1 (en) * 2000-12-15 2003-07-03 Halo Lsi, Inc. Fast program to program verify method
US7046553B2 (en) * 2000-12-15 2006-05-16 Halo Lsi, Inc. Fast program to program verify method
US20080002464A1 (en) * 2004-12-09 2008-01-03 Eduardo Maayan Non-volatile memory device and method for reading cells
US7535765B2 (en) * 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
US20060291287A1 (en) * 2005-06-03 2006-12-28 Interuniversitair Microelektronica Centrum (Imec) Method for operating a non-volatile charge-trapping memory device and method for determining programming/erase conditions
US7508718B2 (en) 2005-06-03 2009-03-24 Interuniversitair Microelektronica Centrum (Imec) Method for operating a non-volatile charge-trapping memory device and method for determining programming/erase conditions
US20090141563A1 (en) * 2005-06-03 2009-06-04 Interuniversitair Microelektronica Centrum (Imec) Vzw Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions
US7933153B2 (en) 2005-06-03 2011-04-26 Imec Method for extracting the distribution of charge stored in a semiconductor device

Also Published As

Publication number Publication date Type
JP2002319289A (en) 2002-10-31 application
EP1225596A3 (en) 2003-07-23 application
EP1225596A2 (en) 2002-07-24 application
DE60126582D1 (en) 2007-03-29 grant
US6490204B2 (en) 2002-12-03 grant
US20010048614A1 (en) 2001-12-06 application
EP1225596B1 (en) 2007-02-14 grant

Similar Documents

Publication Publication Date Title
US7161833B2 (en) Self-boosting system for flash memory cells
US6888758B1 (en) Programming non-volatile memory
US7151692B2 (en) Operation scheme for programming charge trapping non-volatile memory
US5712819A (en) Flash EEPROM system with storage of sector characteristic information within the sector
US7130210B2 (en) Multi-level ONO flash program algorithm for threshold width control
US6011722A (en) Method for erasing and programming memory devices
US6567303B1 (en) Charge injection
US6587903B2 (en) Soft programming for recovery of overerasure
US6438037B1 (en) Threshold voltage compacting for non-volatile semiconductor memory designs
US6522580B2 (en) Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US5774397A (en) Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state
US7206235B1 (en) Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
US7499338B2 (en) Partitioned soft programming in non-volatile memory
US5892714A (en) Method of programming and/or verifying a threshold voltage level of a nonvolatile memory cell
US6690602B1 (en) Algorithm dynamic reference programming
US7286408B1 (en) Boosting methods for NAND flash memory
US6055190A (en) Device and method for suppressing bit line column leakage during erase verification of a memory cell
US6643181B2 (en) Method for erasing a memory cell
US5357476A (en) Apparatus and method for erasing a flash EEPROM
US20070025157A1 (en) Method for programming non-volatile memory with self-adjusting maximum program loop
US6205074B1 (en) Temperature-compensated bias generator
US6292394B1 (en) Method for programming of a semiconductor memory cell
US5790456A (en) Multiple bits-per-cell flash EEPROM memory cells with wide program and erase Vt window
US6456528B1 (en) Selective operation of a multi-state non-volatile memory system in a binary mode
US7535766B2 (en) Systems for partitioned soft programming in non-volatile memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAIFUN SEMICONDUCTORS LTD, ISRAEL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BLOOM, ILAN;MAAYAN, EDUARDO;EITAN, BOAZ;REEL/FRAME:047260/0444

Effective date: 20020201