FI951340A0 - SOI-substrat och förfarande för framställning därav - Google Patents

SOI-substrat och förfarande för framställning därav

Info

Publication number
FI951340A0
FI951340A0 FI951340A FI951340A FI951340A0 FI 951340 A0 FI951340 A0 FI 951340A0 FI 951340 A FI951340 A FI 951340A FI 951340 A FI951340 A FI 951340A FI 951340 A0 FI951340 A0 FI 951340A0
Authority
FI
Finland
Prior art keywords
preparation
soi substrate
soi
substrate
Prior art date
Application number
FI951340A
Other languages
English (en)
Finnish (fi)
Other versions
FI951340A (sv
Inventor
Sadao Nakashima
Katsutoshi Izumi
Norihiko Ohwada
Tatsuhiko Katayama
Original Assignee
Komatsu Denshi Kinzoku Kk
Nippon Telegraph & Telephone
Ntt Electronic Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Denshi Kinzoku Kk, Nippon Telegraph & Telephone, Ntt Electronic Tech filed Critical Komatsu Denshi Kinzoku Kk
Publication of FI951340A0 publication Critical patent/FI951340A0/sv
Publication of FI951340A publication Critical patent/FI951340A/sv

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
FI951340A 1994-03-23 1995-03-22 SOI-substrat och förfarande för framställning därav FI951340A (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6076538A JP3036619B2 (ja) 1994-03-23 1994-03-23 Soi基板の製造方法およびsoi基板

Publications (2)

Publication Number Publication Date
FI951340A0 true FI951340A0 (sv) 1995-03-22
FI951340A FI951340A (sv) 1995-09-24

Family

ID=13608053

Family Applications (1)

Application Number Title Priority Date Filing Date
FI951340A FI951340A (sv) 1994-03-23 1995-03-22 SOI-substrat och förfarande för framställning därav

Country Status (8)

Country Link
US (2) US5658809A (sv)
EP (1) EP0675534B1 (sv)
JP (1) JP3036619B2 (sv)
KR (1) KR0145824B1 (sv)
CZ (1) CZ281798B6 (sv)
DE (1) DE69515189T2 (sv)
FI (1) FI951340A (sv)
TW (1) TW401609B (sv)

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JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
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JPH10284431A (ja) * 1997-04-11 1998-10-23 Sharp Corp Soi基板の製造方法
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KR100258096B1 (ko) * 1997-12-01 2000-06-01 정선종 에스오아이(soi) 기판 제조방법
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JP3911901B2 (ja) 1999-04-09 2007-05-09 信越半導体株式会社 Soiウエーハおよびsoiウエーハの製造方法
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CN100418194C (zh) 2003-02-19 2008-09-10 信越半导体股份有限公司 Soi晶片的制造方法及soi晶片
US7704318B2 (en) * 2003-02-25 2010-04-27 Sumco Corporation Silicon wafer, SOI substrate, method for growing silicon single crystal, method for manufacturing silicon wafer, and method for manufacturing SOI substrate
US7112509B2 (en) * 2003-05-09 2006-09-26 Ibis Technology Corporation Method of producing a high resistivity SIMOX silicon substrate
KR100956711B1 (ko) 2003-12-16 2010-05-06 인터내셔널 비지네스 머신즈 코포레이션 실리콘-온-절연체 웨이퍼의 컨투어화 된 절연체 층 및 이의제조 프로세스
JP2005229062A (ja) * 2004-02-16 2005-08-25 Canon Inc Soi基板及びその製造方法
JP2006032785A (ja) * 2004-07-20 2006-02-02 Sumco Corp Soi基板の製造方法及びsoi基板
US7358586B2 (en) * 2004-09-28 2008-04-15 International Business Machines Corporation Silicon-on-insulator wafer having reentrant shape dielectric trenches
JP4609026B2 (ja) * 2004-10-06 2011-01-12 信越半導体株式会社 Soiウェーハの製造方法
JP2006173568A (ja) * 2004-12-14 2006-06-29 Korea Electronics Telecommun Soi基板の製造方法
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JP4876442B2 (ja) 2005-06-13 2012-02-15 株式会社Sumco Simoxウェーハの製造方法およびsimoxウェーハ
JP2007005563A (ja) 2005-06-23 2007-01-11 Sumco Corp Simoxウェーハの製造方法
KR100752182B1 (ko) * 2005-10-12 2007-08-24 동부일렉트로닉스 주식회사 씨모스 이미지 센서 및 그 제조방법
JP2007208023A (ja) 2006-02-02 2007-08-16 Sumco Corp Simoxウェーハの製造方法
JP2007227424A (ja) 2006-02-21 2007-09-06 Sumco Corp Simoxウェーハの製造方法
JP5157075B2 (ja) * 2006-03-27 2013-03-06 株式会社Sumco Simoxウェーハの製造方法
JP5061489B2 (ja) 2006-04-05 2012-10-31 株式会社Sumco Simoxウェーハの製造方法
JP2008244261A (ja) 2007-03-28 2008-10-09 Shin Etsu Handotai Co Ltd Soi基板の製造方法
US7955950B2 (en) * 2007-10-18 2011-06-07 International Business Machines Corporation Semiconductor-on-insulator substrate with a diffusion barrier
KR100937599B1 (ko) * 2007-12-17 2010-01-20 한국전자통신연구원 반도체 장치 및 그 형성 방법
FR2926925B1 (fr) * 2008-01-29 2010-06-25 Soitec Silicon On Insulator Procede de fabrication d'heterostructures
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US7998815B2 (en) * 2008-08-15 2011-08-16 Qualcomm Incorporated Shallow trench isolation
KR100987794B1 (ko) 2008-12-22 2010-10-13 한국전자통신연구원 반도체 장치의 제조 방법
JP2009147383A (ja) * 2009-03-26 2009-07-02 Hitachi Kokusai Electric Inc 熱処理方法
JP5387451B2 (ja) * 2010-03-04 2014-01-15 信越半導体株式会社 Soiウェーハの設計方法及び製造方法
JP2011176320A (ja) * 2011-03-07 2011-09-08 Hitachi Kokusai Electric Inc 基板処理装置
FR3034565B1 (fr) * 2015-03-30 2017-03-31 Soitec Silicon On Insulator Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme
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Also Published As

Publication number Publication date
TW401609B (en) 2000-08-11
KR0145824B1 (ko) 1998-11-02
DE69515189D1 (de) 2000-04-06
DE69515189T2 (de) 2000-11-23
FI951340A (sv) 1995-09-24
CZ72695A3 (en) 1995-11-15
KR950027901A (ko) 1995-10-18
CZ281798B6 (cs) 1997-02-12
JPH07263538A (ja) 1995-10-13
US5658809A (en) 1997-08-19
EP0675534B1 (en) 2000-03-01
US5918136A (en) 1999-06-29
EP0675534A3 (en) 1996-11-13
JP3036619B2 (ja) 2000-04-24
EP0675534A2 (en) 1995-10-04

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