FR2926925B1 - Procede de fabrication d'heterostructures - Google Patents

Procede de fabrication d'heterostructures

Info

Publication number
FR2926925B1
FR2926925B1 FR0850534A FR0850534A FR2926925B1 FR 2926925 B1 FR2926925 B1 FR 2926925B1 FR 0850534 A FR0850534 A FR 0850534A FR 0850534 A FR0850534 A FR 0850534A FR 2926925 B1 FR2926925 B1 FR 2926925B1
Authority
FR
France
Prior art keywords
heterostructures
producing
producing heterostructures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0850534A
Other languages
English (en)
Other versions
FR2926925A1 (fr
Inventor
Ionut Radu
Oleg Kononchuk
Konstantin Bourdelle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0850534A priority Critical patent/FR2926925B1/fr
Priority to PCT/EP2009/050878 priority patent/WO2009095380A1/fr
Priority to US12/747,099 priority patent/US8263475B2/en
Publication of FR2926925A1 publication Critical patent/FR2926925A1/fr
Application granted granted Critical
Publication of FR2926925B1 publication Critical patent/FR2926925B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
FR0850534A 2008-01-29 2008-01-29 Procede de fabrication d'heterostructures Expired - Fee Related FR2926925B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0850534A FR2926925B1 (fr) 2008-01-29 2008-01-29 Procede de fabrication d'heterostructures
PCT/EP2009/050878 WO2009095380A1 (fr) 2008-01-29 2009-01-27 Procédé de fabrication d'hétérostructures
US12/747,099 US8263475B2 (en) 2008-01-29 2009-01-27 Method for manufacturing heterostructures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0850534A FR2926925B1 (fr) 2008-01-29 2008-01-29 Procede de fabrication d'heterostructures

Publications (2)

Publication Number Publication Date
FR2926925A1 FR2926925A1 (fr) 2009-07-31
FR2926925B1 true FR2926925B1 (fr) 2010-06-25

Family

ID=39705315

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0850534A Expired - Fee Related FR2926925B1 (fr) 2008-01-29 2008-01-29 Procede de fabrication d'heterostructures

Country Status (3)

Country Link
US (1) US8263475B2 (fr)
FR (1) FR2926925B1 (fr)
WO (1) WO2009095380A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR3005895B1 (fr) * 2013-05-27 2015-06-26 Commissariat Energie Atomique Procede d'assemblage de deux substrats de nature differente via une couche intermediaire ductile
FR3079659B1 (fr) * 2018-03-29 2020-03-13 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree
CN111435648A (zh) * 2019-01-11 2020-07-21 中国科学院上海微系统与信息技术研究所 图形化结构的soi衬底的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3036619B2 (ja) * 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JP3250721B2 (ja) 1995-12-12 2002-01-28 キヤノン株式会社 Ｓｏｉ基板の製造方法
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
FR2911430B1 (fr) 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"

Also Published As

Publication number Publication date
FR2926925A1 (fr) 2009-07-31
WO2009095380A1 (fr) 2009-08-06
WO2009095380A8 (fr) 2009-11-05
US8263475B2 (en) 2012-09-11
US20100264458A1 (en) 2010-10-21

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20140930