EP2201687A1 - Générateur de signaux à poursuite de signal - Google Patents

Générateur de signaux à poursuite de signal

Info

Publication number
EP2201687A1
EP2201687A1 EP07814983A EP07814983A EP2201687A1 EP 2201687 A1 EP2201687 A1 EP 2201687A1 EP 07814983 A EP07814983 A EP 07814983A EP 07814983 A EP07814983 A EP 07814983A EP 2201687 A1 EP2201687 A1 EP 2201687A1
Authority
EP
European Patent Office
Prior art keywords
signal
control
output signal
frequency
oscillating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07814983A
Other languages
German (de)
English (en)
Inventor
Chong Lee
Wei Xiong
Amal Ekbal
David Julian
Pavel Monat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/859,335 external-priority patent/US8446976B2/en
Priority claimed from US11/859,354 external-priority patent/US7965805B2/en
Priority claimed from US11/859,723 external-priority patent/US8385474B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP2201687A1 publication Critical patent/EP2201687A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers

Definitions

  • This application relates generally to data communication and more specifically, but not exclusively, to generating a signal such as a clock signal with adjustable phase and/or frequency, and to generating a signal that tracks another signal.
  • a communication system may generate signals where the frequency and the phase of the signals are adjustable to some degree.
  • a typical receiver may use a clock signal to recover data from a received signal.
  • the frequency and phase of the clock signal may be synchronized to the frequency and phase of the received signal to improve the accuracy with which the data is recovered from the received signal.
  • some systems may employ multiphase clocks where the different phases may be used at different times and/or for different circuits.
  • an ultra-wideband communication system may employ very narrow pulses and a high level of duty cycling to reduce the power requirements of associated transceiver components.
  • the effectiveness with which received data is recovered depends, in part, on appropriate tracking of the timing of the received pulses. Due to the use of relatively narrow pulse widths, however, a synchronization and tracking structure that provides a sufficient level of tracking performance may be undesirably complex.
  • a synchronization and tracking circuit may comprise a phase lock loop or some form of a voltage controlled oscillator circuit to generate signals with appropriate frequency and/or phase (e.g., different clock phases in a multiphase system).
  • a synchronization and tracking circuit may comprise a high-frequency oscillator and a high-frequency phase locked loop (“PLL”) or delay locked loop (“DLL").
  • PLL phase locked loop
  • DLL delay locked loop
  • the operating frequency of the PLL/DLL may be selected so that the PLL/DLL provides sufficient resolution for a tracking and acquisition control signal.
  • the disclosure relates in some aspects to signal generation schemes for relatively low-complexity systems.
  • Such systems may include, for example, receivers that may be employed in ultra- wideband applications.
  • the disclosure relates in some aspects to circuits that generate one or more signals where the frequency and/or the phase of each signal may be adjusted.
  • some implementations relate to a relatively lower-complexity tunable multiphase clock generator.
  • the clock generator may employ a low-frequency oscillator that has an operating frequency on the order of the pulse repetition frequency of the pulses processed by an associated device (e.g., a receiver).
  • some implementations relate to a relatively low-complexity synchronization and tracking circuit that employs an oscillator having an operating frequency on the order of the pulse repetition frequency of the pulses processed by the circuit.
  • a device that incorporates such circuits may be less complex, may consume less power, and may have lower implementation cost than devices that employ traditional clocking schemes such as a PLL or a DLL.
  • Such circuits may be particularly advantageous in applications such as ultra-wideband where it may be highly desirable for a device to be relatively small in size, have very low power consumption, and have very low cost.
  • a signal generator generates an adjustable phase output signal where the phase of the output signal is based on comparison of an oscillating signal with an adjustable threshold (e.g., an adjustable reference signal). In this case, adjustment of the threshold results in a corresponding adjustment of the phase of the output signal.
  • the adjustable threshold comprises an adjustable bias signal for a transistor circuit where the oscillating signal is provided as an input to the transistor circuit and the output of the transistor circuit provides the output signal.
  • the above techniques may be employed in one or more signal generator circuits to provide one or more tunable multiphase clocks.
  • a signal generator generates an output signal where the frequency and/or the phase of the output signal is adjusted by temporarily adjusting the frequency of an oscillating signal.
  • the frequency of the oscillating signal is adjusted for a short period of time to effect a slight change (e.g., skew) in the phase of the output signal.
  • the frequency of the oscillating signal is temporarily adjusted in a repeated manner to provide an output signal having an effective frequency that lies between two baseline frequency values.
  • the frequency of the oscillating signal is adjusted by selectively coupling one or more reactive circuits to an oscillator circuit and/or by changing the reactance of one or more reactive circuits.
  • the frequency and phase of one or more output signals is adjusted to track one or more input signals.
  • at least one control signal is adjusted to control a frequency of an oscillating signal from which the output signal is derived.
  • the phase of each output signal is adjusted based on comparison of the oscillating signal with an associated adjustable threshold.
  • FIG. 1 is a simplified block diagram of several sample aspects of a wireless communication system
  • FIG. 2 is a simplified diagram of several sample aspects of a signal generator circuit configured to provide multiphase signals
  • FIG. 3 is a simplified timing diagram illustrating an example of how multiphase signals may be provided
  • FIG. 4 is a simplified diagram of several sample aspects of a signal generator circuit configured to provide a multiphase signal
  • FIG. 5 is a simplified diagram of several sample aspects of a signal generator circuit configured to provide multiphase signals
  • FIG. 6 is a flowchart of several sample aspects of operations that may be performed to provide at least one multiphase signal
  • FIG. 7 is a simplified diagram of several sample aspects of a signal generator circuit configured to provide an adjustable phase and/or frequency signal
  • FIG. 8 is a simplified diagram of several sample aspects of a signal generator circuit configured to provide an adjustable phase and/or frequency signal;
  • FIG. 9 is a flowchart of several sample aspects of operations that may be performed to skew the phase of a signal;
  • FIG. 10 is a simplified timing diagram illustrating a sample skewing of the phase of a signal
  • FIG. 11 is a flowchart of several sample aspects of operations that may be performed to adjust the effective frequency of a signal
  • FIG. 12 is a simplified timing diagram illustrating a sample adjustment of the effective frequency of a signal
  • FIG. 13 is a simplified timing diagram illustrating sample out of phase signals
  • FIG. 14 is a simplified block diagram of several sample aspects of a tracking loop
  • FIG. 15 is a simplified block diagram of several sample aspects of a tracking loop circuit
  • FIG. 16 is a flowchart of several sample aspects of operations that may be performed to track at least one signal
  • FIG. 17 is a simplified block diagram of several sample aspects of a communication system
  • FIG. 18 is a simplified block diagram of several sample aspects of communication components.
  • FIGS. 19 - 21 are simplified block diagrams of several sample aspects of apparatuses configured to provide one or more signals as taught herein.
  • FIG. 1 illustrates several sample aspects of a communication system 100 where a wireless device 102 communicates with a wireless device 104.
  • FIG. 1 illustrates several components 106 and 108 of a transmit path of the device 102 and several components 110 and 112 of a receive path of the device 104.
  • the devices 102 and 104 may generate signals having adjustable frequency and/or phase.
  • the device 102 may employ a clock generator 114 that generates one or more adjustable phase clock signals. Such signals may be used, for example, to synchronize data flow through the transmit path of the device 102.
  • the receive path of the device 104 may employ a similar clock generator 116.
  • the clock generator 116 may generate one or more multiphase clock signals that may be used to synchronize a master receive clock with the received signals. For example, during two-way communication the transmitter master clock and the receiver master clock may not be time aligned.
  • an adjustable frequency/phase clock generator 116 may therefore be employed in a synchronization and tracking circuit 118 to provide a receive clock signal that is synchronized in frequency and phase with received data signals.
  • Multiphase clocks signals provided by the clock generator 116 also may be used during a signal acquisition procedure.
  • an adjustable phase signal may be employed in conjunction with a search algorithm (e.g., during hypothesis testing) to find the correct phase offset for the receive clock signal.
  • the phase of the received signal may not be known.
  • the device 104 may adjust the phase of the receive clock signal in relatively small steps whereby, at each phase value, the device attempts to lock onto the received signal.
  • a clock generator as taught herein may provide an efficient mechanism for providing a series of phase offsets.
  • a wireless device may be transmitting to or receiving from multiple wireless devices where the phase of the master clock of each wireless device may be different.
  • the phase of the master clock of each wireless device may be different.
  • the device 104 may select one local phase when receiving from one wireless device and select another local phase when receiving from another wireless device.
  • a clock generator as taught herein may provide an efficient mechanism for providing multiple clock phases.
  • FIG. 2 illustrates sample aspects of a signal generator circuit 200 (e.g., a clock generator) that may be configured to generate at least one output signal having an adjustable phase.
  • the circuit 200 may provide an output signal on one or more branches as represented by the output signals ⁇ l - ⁇ N.
  • each branch includes an adjustable phase circuit designated 202A - 202N, respectively.
  • a signal generator may be implemented using a relatively simple oscillator circuit.
  • the oscillator circuit may comprise a crystal oscillator 204 that is coupled in parallel to a buffer, a high-quality amplifier, or some other suitable device 206.
  • the device 206 comprises an inverter.
  • the oscillator circuit generates an output signal (e.g., a square wave clock signal) designated ⁇ 0 in FIG. 2.
  • an oscillator circuit as taught herein may have a relatively high quality factor (commonly referred to as the"Q" of the circuit).
  • a high-Q signal may have substantially no harmonic components (e.g., the signal is substantially monotonic). Consequently, relatively accurate changes in phase (as discussed below) may be obtained through the use of a high-Q signal since such a signal may be substantially jitter- free.
  • the quality factor of an oscillator circuit may be on the order of 10 or more.
  • FIG. 3 depicts several waveforms that illustrate, in a simplified manner, sample relationships between the control signals VCl - VCN and the output signals ⁇ 0 - ⁇ N.
  • the top waveform illustrates a sinusoidal-like signal A that is generated by the oscillator 204 and provided to the inputs of the circuits 202A - 202N.
  • the top waveform also depicts several sample decision levels as represented by horizontal lines 302A, 302B, and 302N.
  • the next waveform down illustrates, in a simplified form, the output signal ⁇ O.
  • This waveform also illustrates that the time at which the output signal ⁇ O transitions from low to high or vice versa (e.g., as represented by a vertical line 304A) is based on a decision level of the device 206.
  • this decision level is represented by the horizontal line 302 A.
  • the device 206 generates a transition at the output signal ⁇ 0 whenever the input signal A crosses the decision level 302A.
  • the waveform for the output signal ⁇ l illustrates that this signal may be set to transition when the input signal A crosses a different decision level (e.g., decision level 302B). This decision point is represented by a vertical line 304B.
  • the value of the control signal VCl controls the decision level for the circuit 202 A.
  • a change in the decision level causes the inverter of the circuit 202 A to trigger sooner or later.
  • the waveform for the output signal ⁇ N illustrates that this signal may be set to transition when the input signal A crosses yet another decision level (e.g., decision level 302N).
  • This decision point is represented by a vertical line 304N.
  • the value of the control signal VCN controls the decision level for the circuit 202N.
  • an adjustable phase circuit may be implemented in a variety of ways.
  • an adjustable phase circuit may comprise a comparator that compares the level of an input signal (e.g., input signal A) with an adjustable threshold (e.g., an adjustable reference signal).
  • an adjustable threshold e.g., an adjustable reference signal
  • Such a comparator may take a variety of forms including, for example, a buffer (e.g., an inverter) having an adjustable decision threshold, a transistor circuit having an adjustable bias, an operational amplifier, or some other circuit that makes a switching decision based on the level of an input signal wherein a threshold is used to control the switching decision.
  • an adjustable threshold in the form of a control signal VC controls the phase of an output signal ⁇ N of a transistor circuit 400 (e.g., an inverter).
  • the control signal VC is coupled via a resistor 402 to gates of transistors 404 A and 404B to control a bias level of the transistor circuit 400.
  • the level of the bias of the transistor circuit 400 determines a switching decision level of the transistor circuit 400.
  • an input signal A crosses this decision level the transistor circuit 400 provides a transition at the output signal ⁇ N.
  • the signal from the oscillator circuit (e.g., input signal A) is AC-coupled to the gates of the transistors 404A and 404B via a capacitive element (e.g., a capacitor) 406.
  • a capacitive element e.g., a capacitor
  • the oscillator circuit may be decoupled from the transistor circuit 400, thereby reducing any potential loading of the oscillator circuit by the transistor circuit 400.
  • a signal generator 500 may include a threshold circuit 502 that incorporates or otherwise has access to a look-up table or some other suitable data structure 504 (e.g., stored in a data memory) to define one or more output signal phases for the signal generator 500.
  • a look-up table 504 may include information representative of one or more threshold values (e.g., control voltage entries VCl - VCN) that may be associated with one or more phase entries ⁇ - N ⁇ .
  • selection of a particular control voltage may provide a desired phase shift as represented by the symbol ⁇ .
  • the stored information may take various forms. For example, in some implementations the stored information may comprise the actual values of the thresholds.
  • the stored information may comprise offset values (e.g., relative to an adjacent value in the look-up table 504).
  • an oscillator circuit 506 generates an oscillating signal (e.g., similar to signal A in FIG. 2) that is phase delayed by one or more phase adjusters 508A - 508N (collectively, "phase adjusters 508").
  • the phase of an output signal (e.g., output signals ⁇ l - ⁇ N) generated by each of the phase adjusters 508 may be controlled based on one or more entries of the look-up table 504.
  • the look-up table 504 or other similar structure may be advantageously employed in implementations where a given device may, in effect, concurrently communicate with multiple devices.
  • an ultra- wideband receiver may concurrently receive pulse streams from different transmitters where each pulse stream employs relatively high inter-pulse duty cycling.
  • the receiver may continually switch between the different pulse streams (e.g., on a pulse-by-pulse basis) to recover the pulses transmitted by the different transmitters. Consequently, the receiver may store phase information for each of the pulse streams in the look-up table 504 and access one of the entries whenever the receiver elects to receive a pulse from a given one of the pulse streams.
  • the look-up table 504 may be implemented in a variety of ways.
  • the look-up table 504 may comprise an I/O register whereby selection of a particular register address results in the I/O register outputting a given signal level.
  • the look-up table information may simply be stored in a data memory.
  • each of the phase adjusters 508 may be configured with an appropriate value from the look-up table 504 to set the phase of the phase adjuster.
  • the entries in the look-up table 504 may be provided by a control circuit that determines the values that should be placed in the look-up table 504.
  • the tracking loop when the tracking loop synchronizes to a given signal, the tracking loop may place an entry into the look-up table 504 that is associated with the particular signal with which the tracking loop has synchronized. In this way, in the event the tracking loop needs to resynchronize with that signal, the tracking loop may refer to the corresponding value stored in the look-up table 504.
  • the look-up table 504 may be configured to provide any of the control voltage entries to any of the phase adjusters 508.
  • the phase adjuster 508A may be configured using any the control voltages VCl - VCN.
  • the phase adjuster 508N may be configured using any the control voltages VCl - VCN.
  • the look-up table 504 may be configured to provide a specific one of the control voltage entries to a corresponding one of the phase adjusters 508.
  • the control voltage VCl may be provided to the phase adjuster 508A while the control voltage VCN may be provided to the phase adjuster 508N.
  • Such an implementation may be used to provide, for example, a multiphase clock bus where the output signals ⁇ l - ⁇ N comprise each leg of the multiphase clock bus.
  • a signal generator may be employed in a variety of applications.
  • a signal generator employing a single adjustable phase branch e.g., ⁇ l
  • a signal generator employing several phase branches may provide several signals where each signal has a different phase as defined by a respective one of the control voltages VCl - VCN.
  • phase branches e.g., ⁇ l - ⁇ N, where N is the number of phase branches
  • FIG. 6 Sample operations of a signal generator (e.g., the circuit 200) will now be described in conjunction with the flowchart of FIG. 6.
  • the operations of FIG. 6 may be described as being performed by specific components (e.g., the circuit 200). It should be appreciated, however, that these operations may be performed by other types of components and may be performed using a different number of components. It also should be appreciated that one or more of the operations described herein may not be employed in a given implementation.
  • the signal generator may optionally define one or more threshold values or other suitable information (e.g., control voltages) for defining one or more adjustable thresholds (e.g., reference signals) that are used to skew the phase of one or more output signals.
  • the signal generator provides an oscillating signal. This oscillating signal may comprise, for example, the input signal A of FIG. 2.
  • An output signal generator e.g., a comparator
  • a threshold generator e.g., circuit 502 may select one or more new threshold values to adjust the thresholds.
  • each output signal may then be employed in a corresponding circuit to provide the desired signal processing.
  • the output signal may comprise a clock signal that is used to recover data from received signals.
  • the frequency of a signal generated by an oscillator circuit may be changed by reconfiguring a reactive circuit that is coupled to the oscillator circuit.
  • a control circuit may be configured to dynamically change the capacitance and/or the inductance of the oscillator circuit to thereby change the operating frequency of the oscillator circuit.
  • FIG. 7 illustrates an example where one or more reactive elements may be selectively coupled to or decoupled from an oscillator circuit to cause a change in the capacitance and/or inductance of the oscillator circuit.
  • FIG. 8 illustrates an example where adjustable reactive elements are coupled to an oscillator circuit, whereby the reactance of each of these components may be adjusted to cause a change in the capacitance and/or inductance of the oscillator circuit.
  • a control circuit comprising a control signal generator 702 may control (e.g., as represented by the dashed lines 704) one or more switches 706 of a reactive circuit, where the switches 706 are adapted to selectively couple a variable reactance to an oscillator circuit 708.
  • the reactive circuit may comprise, for example, one or more capacitive elements (e.g., capacitors) 710, one or more inductive elements (e.g., inductors) 712, or a combination of one or more capacitive elements 710 and one or more inductive elements 712.
  • each switch 706 may comprise a transistor or some other suitable device that may be controlled by a control signal 704 to selectively make or break an electrical signal path of the reactive circuit.
  • a control circuit comprising a control signal generator 802 may drive (e.g., as represented by the dashed lines 804) a control input of a variable reactive component that is coupled to an oscillator circuit 806.
  • the variable reactive component may comprise one or more variable capacitive elements 810, one or more variable inductive elements 812, or a combination of one or more variable capacitive elements 810 and one or more variable inductive elements 812.
  • the magnitude or some other characteristic of the control signal may affect an internal circuit of each adjustable capacitive element or adjustable inductive element which, in turn, may cause a corresponding change in the effective capacitance or inductance of the adjustable capacitive element or the adjustable inductive element, respectively.
  • the frequency and/or the phase of an oscillating signal generated by an oscillator circuit may be adjusted by temporarily reconfiguring a reactive circuit that is associated with the oscillator circuit. For example, a control signal that controls the configuration of the reactive circuit may be toggled relatively quickly thereby causing a temporary change in the capacitance and/or the inductance of the oscillator circuit.
  • FIGS. 9 - 12 a signal generator may employ a temporary change in frequency to change the phase or the frequency of an oscillating signal.
  • FIG. 9 describes several sample operations that may be employed to change a phase of a signal by temporarily changing the frequency of the signal as illustrated, for example, in FIG. 10.
  • FIG. 11 describes several sample operations that may be employed to change a frequency of a signal by repeatedly causing temporary changes in the frequency of the signal as illustrated, for example, in FIG. 12.
  • an oscillator circuit may be coupled to one or more reconfigurable reactive elements whereby the frequency of the oscillating signal output by the oscillator circuit may be changed by reconfiguring the reactive elements.
  • the oscillator circuit may be configured as illustrated in FIG. 7 or FIG. 8 whereby the frequency of the oscillating output signal is controlled through the use of one or more control signals.
  • a temporary change in the control signal may be defined to provide a desired change in the phase of the output signal.
  • the control signal may initially be set to an original value, then changed to another value for a relatively short period of time, and then changed back to the original value.
  • this temporary change in the control signal causes a temporary change in the frequency of the oscillator circuit which, in turn, results in a shift of the timing of the output signal.
  • FIG. 10 A simplified timing diagram of such a phase shifting operation is shown in FIG. 10. As illustrated by a comparison of time periods 1002 and 1004, it may be observed that a change in the magnitude of a control signal has caused a corresponding change in the frequency of an oscillating signal. As a result, after the control signal is returned back to its original value, the phase of the oscillating signal has been adjusted (i.e., delayed in this example) relative to the original phase of the oscillating signal. [0070] In the example of FIG. 10, the control signal is adjusted for a period of time that is less than the time period of the oscillating signal. It should be appreciated, however, that in other scenarios the value the control signal may be adjusted for a longer or shorter period of time than illustrated in FIG. 10 (e.g., for several cycles or less).
  • one or more control signals may be temporarily changed in a repeated manner to adjust the effective frequency of an oscillating signal.
  • Such implementations may be employed, for example, to provide an oscillating signal that has an effective frequency that lies between two discrete (e.g., baseline) frequency values that may otherwise be provided by an oscillator circuit.
  • the oscillator circuit may be coupled to one or more reconfigurable reactive elements whereby the frequency of the oscillating signal output by the oscillator circuit may be changed by reconfiguring the reactive elements as discussed above.
  • the reactance may normally change in discrete steps.
  • the operating frequency may change from one discrete frequency value to another discrete frequency value. In some scenarios, however, it may be desirable to provide an operating frequency that lies between these discrete frequency values.
  • a series of temporary changes in the control signal may thus be defined to provide a desired change in the frequency of the output signal.
  • the control signal may be repeatedly switched between two or more values at a relatively fast rate.
  • the frequency of the output signal may be repeatedly switched from one instantaneous frequency to another instantaneous frequency, where the instantaneous frequencies are based on the control signal values.
  • These temporary changes in the frequency of the output signal may thus provide an output signal having an effective frequency that lies somewhere between the above instantaneous frequencies.
  • FIG. 12 A simplified timing diagram of such a frequency shifting operation is depicted in FIG. 12.
  • a waveform 1202 illustrates an instantaneous frequency associated with one value (e.g., a high value) of a control signal 1206.
  • a waveform 1204 illustrates an instantaneous frequency associated with another value (e.g., a low value) of the control signal 1206.
  • a waveform 1208 corresponding to an output signal illustrates that as a result of the duty cycling of the control signal 1206, an effective (e.g., average) frequency of the output signal 1208 may be greater than the frequency of the waveform 1202 and less than the frequency of the waveform 1204.
  • the duty cycle of the control signal 1206 is 50%. It should be appreciated, however, that a different duty cycle may be employed to achieve a different frequency at an output signal.
  • FIG. 12 illustrates that the waveform 1208 may have some amount of jitter (e.g., as represented by the use of multiple lines). Such jitter may not, however, significantly impact the operation of certain types of circuits such as, for example, a tracking loop in some implementations.
  • any desired change in the frequency of the output signal may be achieved by controlling the rate at which the control signal is switched between different values and controlling the corresponding duty cycle associated with each of these values.
  • the value of the control signal is adjusted for periods of time that are each less than the time period of an input signal. It should be appreciated that in other scenarios the value the control signal may be adjusted for a longer or shorter period of time than illustrated in FIG. 12 (e.g., for several cycles or less).
  • phase and/or frequency of an output signal may be adjusted by a desired amount through appropriate selection of the quantity and values of the reactive components.
  • the magnitude of the change in the phase and/or the frequency of the output signal may be dynamically controlled through appropriate control of the control signal.
  • the phase and/or frequency of the output signal depends on the manner in which the reactive elements are reconfigured at a given point in time or over a period of time (e.g., how the switches are opened or closed in FIG. 7 or how the values of the control signals are adjusted in FIG. 8).
  • the reactive components may be switched to other voltage points (e.g., other than ground).
  • the values of the reactive elements may be selected to ensure that the circuit provides suitable incremental levels relating to the increase and decrease in oscillator frequency to compensate for any inaccuracies of the generated signals.
  • a set of information relating to values of control signals may be used to specify a frequency or phase for one or more circuits such as those described in FIGS. 7 and 8.
  • the control circuits 702 and 802 may then access this information to control the reactive elements.
  • Such a set of information may be implemented and used, for example, in a similar manner as the table 504 discussed above.
  • a set of values may define specific frequencies and/or phases for a given oscillator circuit (e.g., one output signal).
  • a set of values may define specific frequencies and/or phases for a set of oscillator circuits (e.g., several output signals).
  • a set of values may define frequency and/or phase offsets (e.g., relative to neighboring entries in a table). In some implementations a set of values may define information relating to a time hopping sequence and/or a frequency hopping sequence.
  • a circuit constructing in accordance with the teachings of FIGS. 7 - 12 may be used to provide a signal having controllable frequency and phase.
  • a first control scheme may be employed to generate control signals that provide the desired frequency and a second control scheme may be employed (e.g., concurrently) to generate control signals that provide a desired phase shift.
  • Such a circuit may thus be used, for example, in a tracking loop that tracks the frequency and phase of an input signal.
  • the disclosure relates in some aspects to signal synchronization and tracking.
  • the circuits and operations described above may be employed to adjust the phase and/or frequency of a given signal so that a given signal is synchronized with and tracks another signal.
  • FIG. 13 illustrates a simplified timing diagram for a pulse-based receiver (e.g., an ultra-wideband receiver, not shown in FIG. 13).
  • the received pulses 1302 A and 1302B are relatively narrow and are repeated at a pulse repetition interval ("PRI") as represented by line 1304.
  • PRI pulse repetition interval
  • the width of each pulse 1302 may be on the order of 1 nanosecond or less (e.g., 100 picoseconds), while the pulse repetition interval 1304 may be on the order of 100 nanoseconds to 10 microseconds. It should be appreciated that these numbers are merely representative and that a given pulse-based system may employ different pulse widths and/or pulse repetition intervals.
  • the receiver may employ oscillators and components with specifications on the order of several gigahertz. In practice, this type of structure may be relatively complex and may consume a relatively significant amount of power. Hence, this type of receiver architecture may not be desirable for low-cost and/or low-power applications.
  • a relatively low-power and low-complexity receiver may be provided for recovering data (e.g., from pulse-based signals such as the pulses 1302).
  • a receiver may utilize a master clock signal 1306 that has a frequency on the order of 1/PRI or a small multiple of 1/PRI for recovering data from the received pulses 1302.
  • a phase shift may exist between the received pulses 1302 and the master clock 1306.
  • the line 1308 illustrates a phase shift between a leading-edge of a received pulse and the rising edge of the master clock 1306.
  • a synchronization and tracking circuit may be employed to generate a clock signal that is synchronized with the received pulses 1302.
  • FIG. 14 illustrates, from a basic operational perspective, a circuit 1400 that generates one or more output clocks that may be synchronized with and track one or more input clocks.
  • an error circuit 1402 compares the frequency and phase of an output clock with the frequency and phase of an input clock. In the event the frequency and/or phase of these clocks differ, the error circuit 1402 generates one or more error signals that control the frequency and phase of a controllable clock generator 1404 that generates the output clock.
  • the circuit 1400 may be configured to generate an output clock that has a defined phase and/or frequency difference from an input clock.
  • the error circuit 1402 may comprise or may otherwise access a table of reference values that specify the desired difference in phase and/or frequency. In this case, the error circuit 1402 will take these reference values into account when generating the error signals.
  • the circuit 1402 may provide one or more output clocks having a desired phase and/or frequency relative to one or more input clocks.
  • the circuit 1402 may change the phase and/or frequency of a given signal whenever necessary by changing the reference values 1406. Consequently, the circuit 1400 may provide a tunable multiphase clock.
  • FIG. 15 an implementation of a tracking loop circuit 1500 that may employ structure described above in conjunction with FIGS. 2 - 12 is shown. Briefly, the circuit 1500 includes a controllable oscillator circuit 1502 that generates an oscillating signal VOSC. In a similar manner as discussed above in conjunction with FIGS.
  • the frequency of the oscillating signal VOSC may be adjusted by operation of a set of control signals 1504 (e.g., one or more signals CSl, CS2, etc.).
  • the circuit 1500 also includes a controllable phase adjust circuit 1506 that generates a set of output signals (e.g., one or more signals 1512A, 1512B, etc.) where the phases of these output signals may be adjusted by operation of a set of threshold signals 1508 (e.g., one or more signals Vl, V2, etc.).
  • the circuit 1506 may be similar to the circuits described above in conjunction with FIGS. 2 - 6.
  • the circuit 1500 also includes a time and frequency tracking circuit 1510 that adjusts the set of control signals 1504 and the set of threshold signals 1508 so that the set of output signals 1512 (e.g., signals 1512A and 1512B) are synchronized to and track a set of input signals 1514.
  • the circuit 1510 may utilize early/late signal tracking contract a given input signal 1514.
  • the circuit 1500 may comprise any number of input signals 1514, output signals 1512, control signals 1504, and threshold signals 1508. Sample operations of the circuit 1500 will be described in more detail in conjunction with the flowchart of FIG. 16.
  • the circuit 1502 provides an oscillating signal VOSC that has a frequency that is based on the current values of the set of control signals 1504. That is, as discussed above in conjunction with FIGS. 7 - 12, the set of control signals 1504 may control the operation of a set of switches (e.g., one or more switches Sl, S2, etc.). The operation of the set of switches, in turn, controls the reactance (e.g., the capacitance) of the oscillator circuit 1502 to control the frequency of the oscillating signal VOSC.
  • the circuit 1506 compares the oscillating signal VOSC with the set of adjustable threshold signals 1508 to provide the set of output signals 1512.
  • a set of devices e.g., inverters
  • the tracking circuit 1510 continually ensures that the set of output signals 1512 track the set of input signals 1514. To this end, the tracking loop compares the set of output signals 1512 with the set of input signals 1514 to determine whether the phase and/or the frequency of the set of output signals 1512 needs to be changed. If so, the tracking circuit 1510 defines new values for the control signals and/or the threshold signals (e.g., defined based on an error signal) so that the set of output signals 1512 track the set of input signals 1514.
  • the tracking circuit 1510 defines new values for the control signals and/or the threshold signals (e.g., defined based on an error signal) so that the set of output signals 1512 track the set of input signals 1514.
  • the tracking circuit 1510 may then adjust the set of control signals 1504, as necessary, to fine tune the resonant frequency of the crystal oscillator. In this way, a slow frequency tracking mechanism is provided for the circuit 1500 by controlling the positions of the switches Sl, S2, etc.
  • duty cycling modulation may be used to correct offsets that may not be directly obtained by a single configuration of the switches.
  • the tracking circuit 1510 also may adjust the set of threshold signals 1508, as necessary, to change the phase of the set of output signals 1512.
  • a fast time tracking mechanism is also provided for the circuit 1500.
  • the circuit 1500 may employ a table of information (e.g., reference values) for defining phase offsets and/or different frequencies (e.g., through the use of a frequency divider circuit, not shown) for one or more of the output signals 1512.
  • the tracking circuit 1510 may define (e.g., repeatedly adapt) the entries in the table that are used to generate the control signals 1504 and the threshold signals 1508.
  • the tracking circuit 1510 may store information (e.g., one or more reference values) associated with the current values of one or more of the control signals 1504 and the threshold signals 1508 that caused the current frequency and/or phase of the given output signal 1512.
  • stored reference values may be used to adjust the frequency and/or phase of a given output signal 1512 to one of several different defined values.
  • the reference values may be used to define a unique frequency and/or phase for each of the output signals 1512.
  • the circuit 1500 may be configured in a variety of ways to provide a desired number of output signals 1512.
  • the circuit 1500 may provide multiphase clocks 1512 based on a single input signal 1514.
  • the circuit 1500 may provide multiphase clocks 1512 where each clock is synchronized with and tracks a corresponding one of several input signals 1514.
  • the circuit 1502 may employ different combinations of reactive elements (e.g., capacitors and/or inductors) and different types of reactive elements (e.g., variable reactive elements) as discussed above.
  • the circuit 1506 may employ different types of comparators 1516 for generating the output signals 1512.
  • a synchronization and tracking circuit as discussed herein may be employed in a variety of applications.
  • a receiver 1702 may comprise a synchronization and tracking circuit as taught herein to recover data from signals received from a transmitter 1704.
  • an output stage 1706 of the transmitter 1704 may transmit data to the receiver 1702 based on a transmit clock 1708.
  • the timing of the signal received by the receiver 1702 is based on the frequency of the transmit clock 1708.
  • the receiver 1702 includes a data recovery component (e.g., circuit) 1710 that recovers data from the received signals based on an appropriately time receive clock generated by a receive clock generator 1712.
  • the receive clock generator 1712 may, in turn, utilize a synchronization and tracking circuit to adjust the frequency and phase of a clock generated by an oscillator circuit 1714 (e.g., a crystal oscillator circuit as discussed herein).
  • the received data signal is provided to an amplification and filtering component 1716 that provides the conditioned received data signal to the data recovery component 1710 and the receive clock generator 1712.
  • the received data signal may comprise the set of input signals 1514 of FIG. 15 that the receive clock generator 1712 compares with its generated receive clock signals (e.g., the set of output signals 1512 of FIG. 15). Consequently, the receive clock generator 1712 will adjust the values of its control and threshold signals, as necessary, so that the receive clock signal is synchronized with and tracks the received data signal.
  • the data recovery component 1710 may be provided with a receive clock signal that may be effectively used to extract the data from the received data signals.
  • FIG. 18 depicts several sample components that may be employed to facilitate communication between devices.
  • a first device 1802 and a second device 1804 are adapted to communicate via a wireless communication link 1806 over a suitable medium.
  • a transmit (“TX”) data processor 1808 receives traffic data (e.g., data packets) from a data buffer 1810 or some other suitable component.
  • the transmit data processor 1808 processes (e.g., encodes, interleaves, and symbol maps) each data packet based on a selected coding and modulation scheme, and provides data symbols.
  • a data symbol is a modulation symbol for data
  • a pilot symbol is a modulation symbol for a pilot (which is known a priori).
  • a modulator 1812 receives the data symbols, pilot symbols, and possibly signaling for the reverse link, and performs modulation (e.g., OFDM or some other suitable modulation) and/or other processing as specified by the system, and provides a stream of output chips.
  • a transmitter (“TMTR") 1814 processes (e.g., converts to analog, filters, amplifies, and frequency upconverts) the output chip stream and generates a modulated signal, which is then transmitted from an antenna 1816.
  • the modulated signals transmitted by the device 1802 (along with signals from other devices in communication with the device 1804) are received by an antenna 1818 of the device 1804.
  • a receiver (“RCVR”) 1820 processes (e.g., conditions and digitizes) the received signal from the antenna 1818 and provides received samples.
  • a demodulator (“DEMOD”) 1822 processes (e.g., demodulates and detects) the received samples and provides detected data symbols, which may be a noisy estimate of the data symbols transmitted to the device 1804 by the other device(s).
  • a receive (“RX”) data processor 1824 processes (e.g., symbol demaps, deinterleaves, and decodes) the detected data symbols and provides decoded data associated with each transmitting device (e.g., device 1802).
  • a forward link Components involved in sending information from the device 1804 to the device 1802 (e.g., a forward link) will be now be treated.
  • traffic data is processed by a transmit (“TX") data processor 1826 to generate data symbols.
  • a modulator 1828 receives the data symbols, pilot symbols, and signaling for the forward link, performs modulation (e.g., OFDM or some other suitable modulation) and/or other pertinent processing, and provides an output chip stream, which is further conditioned by a transmitter (“TMTR") 1830 and transmitted from the antenna 1818.
  • modulation e.g., OFDM or some other suitable modulation
  • TMTR transmitter
  • signaling for the forward link may include power control commands and other information (e.g., relating to a communication channel) generated by a controller 1832 for all devices (e.g.
  • the modulated signal transmitted by the device 1804 is received by the antenna 1816, conditioned and digitized by a receiver ("RCVR") 1834, and processed by a demodulator (“DEMOD”) 1836 to obtain detected data symbols.
  • a receive (“RX”) data processor 1838 processes the detected data symbols and provides decoded data for the device 1802 and the forward link signaling.
  • a controller 1840 receives power control commands and other information to control data transmission and to control transmit power on the reverse link to the device 1804.
  • the controllers 1840 and 1832 direct various operations of the device 1802 and the device 1804, respectively. For example, a controller may determine an appropriate filter, reporting information about the filter, and decode information using a filter.
  • Data memories 1842 and 1844 may store program codes and data used by the controllers 1840 and 1832, respectively.
  • FIG. 18 also illustrates that the communication components may include one or more components that provide signal generation functionality as taught herein.
  • the receiver 1824 may include a clock generator circuit 1846 and the receiver 1820 may include a clock generator circuit 1848.
  • a wireless device may include various components that perform functions based on data that is provided (e.g., transmitted or received) through the use of an output signal (e.g., an oscillating signal) that is generated as taught herein.
  • a wireless headset may include a transducer adapted to provide an audio output based on data that is provided through the use of an output signal.
  • a wireless sensing device may include a sensor adapted to provide data to be transmitted through the use of an output signal.
  • a wireless watch may include a user interface adapted to provide an indication based on data that is provided through the use of an output signal.
  • a user interface may comprise a display screen, lighting elements (e.g., an LED device), a speaker, a temperature-based indicator, or some other suitable device that provides some form of indication (e.g., visual, audible, vibration-related, temperature -related, and so on) to a user.
  • a wireless device may communicate via one or more wireless communication links that are based on or otherwise support any suitable wireless communication technology.
  • a wireless device may associate with a network.
  • the network may comprise a body area network or a personal area network (e.g., an ultra-wideband network).
  • the network may comprise a local area network or a wide area network.
  • a wireless device may support or otherwise use one or more of a variety of wireless communication technologies, protocols, or standards such as, for example, CDMA, TDMA, OFDM, OFDMA, WiMAX, and Wi-Fi. Similarly, a wireless device may support or otherwise use one or more of a variety of corresponding modulation or multiplexing schemes.
  • a wireless device may thus include appropriate components (e.g., air interfaces) to establish and communicate via one or more wireless communication links using the above or other wireless communication technologies.
  • a device may comprise a wireless transceiver with associated transmitter and receiver components (e.g., transmitter 108 and receiver 110) that may include various components (e.g., signal generators and signal processors) that facilitate communication over a wireless medium.
  • a wireless device may communicate via an impulse-based wireless communication link.
  • an impulse-based wireless communication link may utilize ultra-wideband pulses that have a relatively short length (e.g., on the order of a few nanoseconds or less) and a relatively wide bandwidth.
  • the ultra- wideband pulses may have a fractional bandwidth on the order of approximately 20% or more and/or have a bandwidth on the order of approximately 500 MHz or more.
  • the teachings herein may be incorporated into (e.g., implemented within or performed by) a variety of apparatuses (e.g., devices).
  • a phone e.g., a cellular phone
  • PDA personal data assistant
  • an entertainment device e.g., a music or video device
  • a headset e.g., headphones, an earpiece, etc.
  • a microphone e.g., a medical sensing device (e.g., a biometric sensor, a heart rate monitor, a pedometer, an EKG device, etc.), a user I/O device (e.g., a watch, a remote control, a light switch, a keyboard, a mouse, etc.), an environment sensing device (e.g., a tire pressure monitor), a computer, a point-of-sale device, an entertainment device, a hearing aid, a set-top box, or any other suitable device.
  • a medical sensing device e.g., a
  • teachings herein may be adapted for use in low power applications (e.g., through the use of an impulse-based signaling scheme and low duty cycle modes) and may support a variety of data rates including relatively high data rates (e.g., through the use of high-bandwidth pulses).
  • a wireless device may comprise an access device (e.g., a Wi- Fi access point) for a communication system.
  • an access device may provide, for example, connectivity to another network (e.g., a wide area network such as the Internet or a cellular network) via a wired or wireless communication link.
  • the access device may enable another device (e.g., a Wi-Fi station) to access the other network or some other functionality.
  • another device e.g., a Wi-Fi station
  • one or both of the devices may be portable or, in some cases, relatively non-portable.
  • apparatuses 1900, 2000, and 2100 are represented as a series of interrelated functional blocks that may represent functions implemented by, for example, one or more integrated circuits (e.g., an ASIC) or may be implemented in some other manner as taught herein.
  • an integrated circuit may include a processor, software, other components, or some combination thereof.
  • the apparatuses 1900 - 2100 may include one or more modules that may perform one or more of the functions described above with regard to various figures.
  • an ASIC for providing, 1902, 2002, or 2102 may correspond to, for example, an oscillator circuit as discussed herein.
  • An ASIC for comparing, 1904 or 2104 may correspond to, for example, a comparator as discussed herein.
  • An ASIC for generating, 1906 may correspond to, for example, a threshold circuit as discussed herein.
  • An ASIC for storing, 1908 or 2108 may correspond to, for example, a data memory as discussed herein.
  • An ASIC for recovering, 1910, 2008, or 2110 may correspond to, for example, a data recovery circuit as discussed herein.
  • An ASIC for coupling, 2004, may correspond to, for example, a reactive circuit as discussed herein.
  • An ASIC for varying, 2006 may correspond to, for example, a control circuit as discussed herein.
  • An ASIC for causing, 2106 may correspond to, for example, a time and frequency tracking circuit as discussed herein.
  • these components may be implemented via appropriate processor components. These processor components may in some aspects be implemented, at least in part, using structure as taught herein. In some aspects a processor may be adapted to implement a portion or all of the functionality of one or more of these components. In some aspects one or more of the components represented by dashed boxes are optional.
  • the apparatuses 1900 - 2100 may comprise one or more integrated circuits.
  • a single integrated circuit may implement the functionality of one or more of the illustrated components, while in other aspects more than one integrated circuit may implement the functionality of one or more of the illustrated components.
  • FIGS. 19 - 21 may be implemented using any suitable means. Such means also may be implemented, at least in part, using corresponding structure as taught herein.
  • the components described above in conjunction with the "ASIC for" components of FIGS. 19 - 21 also may correspond to similarly designated “means for” functionality.
  • one or more of such means may be implemented using one or more of processor components, integrated circuits, or other suitable structure as taught herein.
  • any reference to an element herein using a designation such as "first,” “second,” and so forth does not generally limit the quantity or order of those elements.
  • first and second elements do not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise a set of elements may comprise one or more elements.
  • information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
  • any of the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two, which may be designed using source coding or some other technique), various forms of program or design code incorporating instructions (which may be referred to herein, for convenience, as "software” or a "software module”), or combinations of both.
  • software or a “software module”
  • the IC may comprise a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, electrical components, optical components, mechanical components, or any combination thereof designed to perform the functions described herein, and may execute codes or instructions that reside within the IC, outside of the IC, or both.
  • a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • any specific order or hierarchy of steps in any disclosed process is an example of a sample approach. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure.
  • the accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
  • a software module e.g., including executable instructions and related data
  • other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art.
  • a sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a "processor") such the processor can read information (e.g., code) from and write information to the storage medium.
  • a sample storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in user equipment.
  • the processor and the storage medium may reside as discrete components in user equipment.
  • any suitable computer-program product may comprise a computer-readable medium comprising codes (e.g., executable by at least one computer) relating to one or more of the aspects of the disclosure.
  • a computer program product may comprise packaging materials.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Circuits Of Receivers In General (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

Selon l'invention, on règle la fréquence et la phase d'un signal de sortie afin de suivre un signal d'entrée. On règle un signal de commande afin de réguler la fréquence d'un signal oscillant à partir duquel on dérive le signal de sortie. Dans certains aspects, on règle la fréquence du signal oscillant en reconfigurant les circuits réactifs couplés à un circuit oscillateur. On peut régler la phase du signal de sortie sur la base d'une comparaison entre le signal oscillant et un seuil réglable. Par exemple, le seuil réglable peut comprendre un signal de polarisation réglable de circuit de transistor, le signal oscillant étant fourni sous la forme d'une entrée du circuit de transistor et la sortie du circuit de transistor constituant le signal de sortie.
EP07814983A 2007-09-21 2007-09-24 Générateur de signaux à poursuite de signal Withdrawn EP2201687A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/859,335 US8446976B2 (en) 2007-09-21 2007-09-21 Signal generator with adjustable phase
US11/859,354 US7965805B2 (en) 2007-09-21 2007-09-21 Signal generator with signal tracking
US11/859,723 US8385474B2 (en) 2007-09-21 2007-09-21 Signal generator with adjustable frequency
PCT/US2007/079341 WO2009038589A1 (fr) 2007-09-21 2007-09-24 Générateur de signaux à poursuite de signal

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EP2201687A1 true EP2201687A1 (fr) 2010-06-30

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EP07814981A Withdrawn EP2191572A1 (fr) 2007-09-21 2007-09-24 Générateur de signaux à phase réglable
EP07814983A Withdrawn EP2201687A1 (fr) 2007-09-21 2007-09-24 Générateur de signaux à poursuite de signal

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EP07814981A Withdrawn EP2191572A1 (fr) 2007-09-21 2007-09-24 Générateur de signaux à phase réglable

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WO (3) WO2009038587A1 (fr)

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EP2191571A1 (fr) 2010-06-02
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JP2014014081A (ja) 2014-01-23
JP5815608B2 (ja) 2015-11-17
KR20100057692A (ko) 2010-05-31
WO2009038588A1 (fr) 2009-03-26
KR101537012B1 (ko) 2015-07-16
JP2010541322A (ja) 2010-12-24
JP5826492B2 (ja) 2015-12-02
CN101803195B (zh) 2013-03-27
CN101803195A (zh) 2010-08-11
CN101803193A (zh) 2010-08-11
WO2009038588A8 (fr) 2010-04-15
EP2191571B1 (fr) 2013-11-20
WO2009038587A1 (fr) 2009-03-26
EP2191572A1 (fr) 2010-06-02
TW200915725A (en) 2009-04-01
JP2016001884A (ja) 2016-01-07
JP2010541320A (ja) 2010-12-24
CN101803194B (zh) 2013-03-27
KR101172961B1 (ko) 2012-08-09
KR20100057693A (ko) 2010-05-31
TW200915728A (en) 2009-04-01
KR20120135533A (ko) 2012-12-14
JP2015015725A (ja) 2015-01-22
TW200914842A (en) 2009-04-01
KR20100054165A (ko) 2010-05-24
CN101803194A (zh) 2010-08-11
KR101148348B1 (ko) 2012-05-21
CN101803193B (zh) 2016-04-13
JP5490699B2 (ja) 2014-05-14

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