EP1307920A2 - Cellules de memoire, dispositif a cellules de memoire et procede de fabrication y relatif - Google Patents

Cellules de memoire, dispositif a cellules de memoire et procede de fabrication y relatif

Info

Publication number
EP1307920A2
EP1307920A2 EP01962611A EP01962611A EP1307920A2 EP 1307920 A2 EP1307920 A2 EP 1307920A2 EP 01962611 A EP01962611 A EP 01962611A EP 01962611 A EP01962611 A EP 01962611A EP 1307920 A2 EP1307920 A2 EP 1307920A2
Authority
EP
European Patent Office
Prior art keywords
memory cell
layer
trenches
oxide
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01962611A
Other languages
German (de)
English (en)
Inventor
Herbert Palm
Josef Willer
Achim Gratz
Jakob Kriz
Mayk Röhrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10039441A external-priority patent/DE10039441A1/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1307920A2 publication Critical patent/EP1307920A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the invention relates to the field of electrically writable and erasable non-volatile flash memories. It describes a non-volatile memory cell constructed according to the SONOS (Semiconductor Oxide Nitride Oxide Semiconductor) scheme, which can be used in a virtual ground NOR architecture.
  • SONOS semiconductor Oxide Nitride Oxide Semiconductor
  • the smallest non-volatile memory cells are required for the highest integration density in multimedia applications.
  • semiconductor technology enables increasingly larger storage capacities, which will soon open up the gigabit range.
  • other parameters such as. B. the thickness of the tunnel oxide can no longer be scaled accordingly.
  • the decrease in channel length associated with the reduction in structure in the case of planar transistors requires an increase in the channel doping in order to avoid the occurrence of a voltage breakdown between the source and drain referred to as punch-through. This leads to an increase in the threshold voltage, which is usually compensated for by a reduction in the thickness of the gate oxide.
  • planar SONOS memory cells (see US Pat. No. 5,768,192, US Pat. No. 6,011,725, WO 99/60631) that can be erased by channel hot electrons and can be erased require a control dielectric with a thickness equivalent to a gate oxide.
  • this thickness cannot be reduced arbitrarily without the number of executable programming cycles ("endurance" of the memory cell) decreasing in an intolerable manner.
  • a sufficiently large channel length is therefore required so that the dopant concentration in the channel is not must be chosen too high, because otherwise the threshold voltage increases too much.
  • DE 195 45 903 A1 describes a read-only memory cell arrangement in which planar MOS transistors are arranged in parallel cells. Adjacent cells run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The bit lines run transversely and the word lines run parallel to the longitudinal trenches.
  • DE 196 00 422 C1 describes an electrically programmable memory cell arrangement in which there are a large number of individual memory cells, each of which comprises a MOS transistor with a gate dielectric with adhesion points and which are arranged in rows running in parallel. Adjacent lines run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches and are isolated from one another.
  • DE 196 03 810 C1 describes a memory cell arrangement which comprises first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors.
  • the planar MOS transistors are arranged on the bottom of and on the crown of parallel, strip-shaped trenches.
  • the vertical MOS transistors are arranged on the side walls of the trenches.
  • the object of the present invention is to provide a memory cell for a memory cell arrangement with an extremely small footprint and an associated production method.
  • the memory cell according to the invention has a memory transistor which is provided on a top side of a semiconductor body or a semiconductor layer with a gate electrode which is arranged between a source region and a drain region which are formed in the semiconductor material.
  • the gate electrode is separated from the semiconductor material by dielectric material.
  • At least between a layer sequence is present between the source region and the gate electrode and between the drain region and the gate electrode, which comprises a storage layer provided between the delimitation layers for trapping charge carriers at the source and drain.
  • the material of the boundary layers has a higher energy band gap than the material of the storage layer, so that the charge carriers that are trapped in the storage layer between the boundary layers remain localized there.
  • a nitride is preferably used as the material for the storage layer; an oxide is primarily suitable as the surrounding material.
  • the storage layer in this example is silicon nitride with an energy band gap of approximately 5 eV, the surrounding boundary layers silicon oxide with an energy band gap of approximately 9 eV.
  • the storage layer can be a different material with a smaller energy band gap than that of the boundary layers, the difference between the energy band gaps being as large as possible for good electrical confinement of the charge carriers (confinement).
  • Adhesion points or adhesion centers are preferably provided in the memory layer, which form energy levels to be occupied by charge carriers within the energy band gap of the storage layer.
  • the lower boundary layer which faces the semiconductor material, is to be made so thick that direct tunneling of charge carriers is avoided.
  • the lower boundary layer is therefore preferably at least about 6 nm to 7 nm thick.
  • the upper boundary layer facing the gate electrode is preferably typically about twice as thick as the lower boundary layer in order to avoid direct tunneling and Fowler-Nordheim tunneling out of the gate during the deletion process.
  • the layer sequence of the storage layer and the boundary layers is preferably formed with a small oxide-equivalent thickness, which means the thickness of a pure oxide layer as a dielectric to form the same capacitance.
  • the electrically effective thickness of the gate dielectric is namely reduced, and a thinner lower boundary layer allows higher programming rates and / or lower programming voltages.
  • the barrier height between the semiconductor material and the storage layer must remain sufficiently high.
  • This barrier height generally decreases with increasing relative dielectric constant of the material of the lower boundary layer.
  • the barrier height is about 3.1 eV; this is the distance of the Fermini level of the electrons in the silicon from the lower edge of the conduction band in the Si0 2 layer.
  • This barrier height should not be less than 2 eV.
  • a low barrier height is advantageous since the programming speed increases drastically in this case and opens up the possibility of reducing the source / drain voltage and thus reducing the risk of punch-through in the channel. If this can be achieved in accordance with the requirements, the material of the lower boundary layer can advantageously also have a relative dielectric constant of at least 20.
  • Silicon nitride has a relative dielectric constant of approximately 7.9.
  • silicon nitride can also be used advantageously as a lower boundary layer.
  • silicon oxynitride can also be used here; the content of oxygen and nitrogen can be changed continuously or in stages from the semiconductor material to the storage layer.
  • tantalum oxide, hafnium silicate, titanium oxide, zirconium oxide and aluminum oxide, but also tantalum oxide (with a stoichiometric composition Ta 2 0 5 ), titanate and tantalate are also suitable as materials for the boundary layers.
  • the use of silicates in the boundary layers is particularly noteworthy.
  • hafnium silicate, here preferably without adhesion points, can be used with advantage. It is also a constantly changing one
  • Composition of the lower boundary layer can be reached, in which Si0 2 is present at the bottom to achieve a good interface with the silicon of the substrate or semiconductor body, which is increasingly mixed with hafnium upwards, ie toward the storage layer, so that a stoichiometric composition may be present of a hafnium silicate is achieved.
  • the silicon Towards the storage layer, the silicon Remove the material until there is only Hf0 2 adjacent to the storage layer. In this way, a barrier height between the semiconductor material and the storage layer is reduced from 3.1 eV to approximately 2 eV compared to the exclusive use of SiO 2 .
  • a corresponding continuous variation of the composition of a lower boundary layer based on SiO 2 is possible instead of with hafnium with other chemical elements, preferably with metals, as additives, for example with titanium, zirconium or lanthanum.
  • hafnium with other chemical elements, preferably with metals, as additives, for example with titanium, zirconium or lanthanum.
  • metals for example with titanium, zirconium or lanthanum.
  • Al 2 0 3 and Ta 2 0 5 are of particular interest for the upper boundary layer, a combination with titanate, titanium dioxide, tantalate or tantalum pentoxide in the storage layer being preferred.
  • the layer sequence of a boundary layer, a memory layer and a further boundary layer can be applied over the entire surface of an upper side of the semiconductor body, so that portions of the memory layer are also present on the horizontal regions of this surface with respect to this upper side and on the bottoms of the trenches filled with the gate electrodes are.
  • the storage layer can be delimited in that the layer sequence comprising the storage layer is respectively present on the walls of a trench in the semiconductor material, in which respective gate electrodes are arranged, and is interrupted therebetween.
  • the memory cells according to the invention can be connected as a memory cell arrangement in a virtual ground NOR architecture, with a freely selectable one within wide limits
  • Channel length can be realized. This is achieved by forming trenches in a semiconductor body.
  • the trenches can e.g. B. can be etched into previously generated n + region , so that the channel regions at the bottom of these trenches have a curvature directed towards the semiconductor body or are deeper than the regions of the source and drain.
  • the advantages of this arrangement are in particular ⁇ rt IQ IQ CQ H h- 1 3 ⁇ CQ 'Tj ⁇ CQ ⁇ O ö ⁇ PJ td CQ CQ> ⁇
  • ⁇ PJ H- H- ⁇ 3 tr tr 3 g: 3 rt 1 rt 3 3 rt _> t 3 M ⁇ ⁇ - H- 1 Hj ⁇ tr ⁇ 3 i h- 1 ⁇ tr rt ⁇ Hi 3 ⁇ 3 CQ> n 3 3 ⁇ PJ ⁇ ! J Hj Hj 3 er ⁇ ⁇ -
  • the trenches are filled with electrically conductive material, preferably with conductively doped polysilicon applied over the entire surface, in order to produce the gate electrodes 2 and a layer for the conductor tracks 8 forming the word lines WL.
  • a layer 9 which reduces the lead resistance is also produced, for example from tungsten silicide or a metal layer from tungsten.
  • a strip-like structured mask layer 15, e.g. B. a hard mask made of nitride, with which the gate electrodes and word lines are structured by the polysilicon not covered by the mask, for. B. is removed by means of RIE (reactive ion etching).
  • FIG. 4 shows an alternative embodiment in which the ONO layer sequence has been anisotropically etched down to the lower boundary layer before the polysilicon layer is applied. Remains of the ONO layer sequence only remain in the areas on the walls of the trenches intended for the storage of trapped charge carriers. Otherwise, this exemplary embodiment is the same as the exemplary embodiment in FIG. 3.
  • FIG. 5 shows a cross section through the memory cell arrangement that runs transversely to the word lines.
  • the embodiment corresponds to the embodiment according to FIG. 3 with an ONO layer sequence present over the entire surface.
  • the ONO layer sequence between the word lines at least partially, for. B. can be removed down to the lower boundary layer 5, or even completely down to the semiconductor material, spacer elements 16 (spacers) are produced, which are part of the manufacturing process of the CMOS ⁇ 1 ⁇ ⁇
  • FIG. 11 shows the cross section marked in FIG. 10, in which the pad oxide 22 and the pad nitride 23 can be seen as layers between the filled trenches.
  • the upper side is provided with a further strip-shaped mask which is oriented transversely, preferably perpendicularly, to the orientation of the strip-shaped mask previously used. Openings in the dielectric 21 are produced using this further mask.
  • Figure 12 shows the arrangement thus achieved.
  • the strip-shaped portions 24 of the further mask which are shown here piece by piece with dashed borders, run perpendicular to the etched and filled trenches.
  • the dielectric 21 of the filled trenches is removed in those regions of the upper side which are left free by the further mask, so that openings 25 are formed here.
  • the dielectric 21 is removed in these openings down to the bottom of the trenches.
  • the gate electrodes and the word lines arranged for this purpose in a self-aligned manner can be introduced in a next method step, as described above, using the strip-like structured layer 19 made of dielectric material.
  • a layer of the material provided for the word lines (for example W, WSi, polysilicon) is deposited over the entire surface, that is to say also onto the gate electrodes introduced into the openings. If the same material is provided for the gate electrodes and the word lines, the openings 25 can also be filled together with the full-surface deposition of this material on the upper side.
  • the word lines are deposited from the entire surface Structured layer.
  • the third mask can advantageously also be used to structure the gate electrodes of transistors which are arranged in an area of a control circuit adjoining the memory field or in other logic areas of a circuit integrated on the same chip. This makes it possible in a simple manner to contact the word lines in the pitch of the array, that is to say in the spacing of adjacent lines from one another, with the circuit components of the drive circuit for the purpose of driving the memory transistors with the required voltages.
  • the third stripe-shaped mask is not necessarily manufactured to be exactly complementary to the previously used mask with which the openings 25 were formed, it can happen that the word lines are somewhat displaced transversely to their longitudinal direction with respect to the gate electrodes, ie not are completely aligned to the gate electrodes.
  • FIG. 13 shows the upper side of the arrangement corresponding to FIG. 12 after the openings 25 have been filled with the gate electrodes 26 and the word lines 27 have been structured.
  • the word lines are drawn exaggeratedly clearly so that they are laterally shifted relative to the gate electrodes 26.
  • the word lines 27 therefore only partially cover the gate electrodes 26, which are approximately square here in the plan view, specifically in the area represented by the hidden contours drawn with dashed lines.
  • the usual and known process steps for completing the control components are carried out. These include in particular the implants for the source and drain regions of the drive transistors, including the LDD and Pocke implants, which are carried out independently of the memory cell structure. Wiring is carried out via a suitable number of structured metallization levels, which are arranged in intermetal dielectrics. From the description of the manufacture of the memory cell arrangement according to the invention, its structure and in particular the structure of the individual memory cell, as is also claimed separately, result.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Chaque cellule de mémoire est un transistor de mémoire qui est muni, sur une face supérieure d'un corps semi-conducteur, d'une électrode de grille (2) qui est disposée dans une tranchée entre une région source (3) et une région drain (4), lesquelles sont formées dans le matériau semi-conducteur. L'électrode de grille est séparée du matériau semi-conducteur par un matériau diélectrique. On dispose, au moins entre la région source et l'électrode de grille, et entre la région drain et l'électrode de grille, une succession de couches oxyde-nitrure-oxyde qui est prévue pour la capture de porteurs de charge sur la source et le drain.
EP01962611A 2000-08-11 2001-08-06 Cellules de memoire, dispositif a cellules de memoire et procede de fabrication y relatif Withdrawn EP1307920A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US900654 1986-08-26
DE10039441 2000-08-11
DE10039441A DE10039441A1 (de) 2000-08-11 2000-08-11 Speicherzelle, Speicherzellenanordnung und Herstellungsverfahren
US09/900,654 US20020024092A1 (en) 2000-08-11 2001-07-06 Memory cell, memory cell arrangement and fabrication method
PCT/DE2001/002997 WO2002015276A2 (fr) 2000-08-11 2001-08-06 Cellules de memoire, dispositif a cellules de memoire et procede de fabrication y relatif

Publications (1)

Publication Number Publication Date
EP1307920A2 true EP1307920A2 (fr) 2003-05-07

Family

ID=26006676

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01962611A Withdrawn EP1307920A2 (fr) 2000-08-11 2001-08-06 Cellules de memoire, dispositif a cellules de memoire et procede de fabrication y relatif

Country Status (9)

Country Link
US (1) US6844584B2 (fr)
EP (1) EP1307920A2 (fr)
JP (1) JP2004517464A (fr)
CN (1) CN100446258C (fr)
BR (1) BR0113164A (fr)
MX (1) MXPA03001223A (fr)
RU (1) RU2247441C2 (fr)
TW (1) TWI244199B (fr)
WO (1) WO2002015276A2 (fr)

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Also Published As

Publication number Publication date
WO2002015276A2 (fr) 2002-02-21
JP2004517464A (ja) 2004-06-10
RU2247441C2 (ru) 2005-02-27
US20030015752A1 (en) 2003-01-23
CN1446378A (zh) 2003-10-01
WO2002015276A3 (fr) 2002-06-06
TWI244199B (en) 2005-11-21
BR0113164A (pt) 2003-06-24
MXPA03001223A (es) 2003-09-22
US6844584B2 (en) 2005-01-18
CN100446258C (zh) 2008-12-24

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