EP1212794A2 - Procede de production d'un circuit integre comportant au moins un plan de metallisation - Google Patents

Procede de production d'un circuit integre comportant au moins un plan de metallisation

Info

Publication number
EP1212794A2
EP1212794A2 EP00965776A EP00965776A EP1212794A2 EP 1212794 A2 EP1212794 A2 EP 1212794A2 EP 00965776 A EP00965776 A EP 00965776A EP 00965776 A EP00965776 A EP 00965776A EP 1212794 A2 EP1212794 A2 EP 1212794A2
Authority
EP
European Patent Office
Prior art keywords
dielectric layer
thickness
etching
layer
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00965776A
Other languages
German (de)
English (en)
Inventor
Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1212794A2 publication Critical patent/EP1212794A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Selon l'invention, pour réaliser un plan de métallisation comportant des lignes et des contacts, on applique des couches diélectriques sur un substrat (4). On procède d'abord à la réalisation de trous de contact par attaque à travers les deux couches diélectriques supérieures, jusqu'à pénétration dans la couche diélectrique située sous ces deux couches, l'épaisseur restante de cette couche étant sensiblement égale à l'épaisseur de la couche supérieure. Ensuite on procède à la réalisation de tranchées de ligne par attaque sélective par rapport à la première couche diélectrique et à la troisième couche diélectrique dont les surfaces sont enlevées sensiblement simultanément. Après structuration de la première couche diélectrique et de la troisième couche diélectrique, on réalise les contacts et les lignes dans les trous de contact et dans les tranchées de ligne.
EP00965776A 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation Withdrawn EP1212794A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19940358 1999-08-25
DE19940358 1999-08-25
PCT/DE2000/002811 WO2001015219A2 (fr) 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation

Publications (1)

Publication Number Publication Date
EP1212794A2 true EP1212794A2 (fr) 2002-06-12

Family

ID=7919589

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00965776A Withdrawn EP1212794A2 (fr) 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation

Country Status (7)

Country Link
US (2) US20020098679A1 (fr)
EP (1) EP1212794A2 (fr)
JP (1) JP2003508896A (fr)
KR (1) KR20020025237A (fr)
CN (1) CN1192427C (fr)
TW (1) TW461037B (fr)
WO (1) WO2001015219A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US20060261036A1 (en) * 2005-04-11 2006-11-23 Stmicroelectronics S.R.L. Method for patterning on a wafer having at least one substrate for the realization of an integrated circuit
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US7592253B2 (en) * 2005-12-29 2009-09-22 Dongbu Electronics Co., Ltd. Method for forming a damascene pattern of a copper metallization layer
WO2007100125A1 (fr) * 2006-02-28 2007-09-07 Advanced Interconnect Materials, Llc Dispositif semiconducteur, son procede de fabrication et materiau cible de pulverisation a utiliser dans ledit procede
US20080303154A1 (en) * 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
DE102007054384A1 (de) 2007-11-14 2009-05-20 Institut Für Solarenergieforschung Gmbh Verfahren zum Herstellen einer Solarzelle mit einer oberflächenpassivierenden Dielektrikumdoppelschicht und entsprechende Solarzelle
TWI490939B (zh) * 2008-10-01 2015-07-01 Vanguard Int Semiconduct Corp 孔洞的形成方法
CN102543837A (zh) * 2010-12-22 2012-07-04 中芯国际集成电路制造(上海)有限公司 顶层金属互连层结构和制作方法
US10327333B2 (en) * 2012-03-01 2019-06-18 Koninklijke Philips N.V. Electronic circuit arrangement and method of manufacturing the same
KR102477608B1 (ko) * 2017-12-12 2022-12-14 삼성디스플레이 주식회사 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
CN112018077A (zh) * 2020-07-29 2020-12-01 复旦大学 一种铜互连结构及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
KR0184158B1 (ko) * 1996-07-13 1999-04-15 문정환 반도체장치의 자기 정합정 금속 배선 형성 방법
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
US6291334B1 (en) * 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
FR2791472B1 (fr) * 1999-03-26 2002-07-05 Commissariat Energie Atomique Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique
US6326301B1 (en) * 1999-07-13 2001-12-04 Motorola, Inc. Method for forming a dual inlaid copper interconnect structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0115219A2 *

Also Published As

Publication number Publication date
KR20020025237A (ko) 2002-04-03
WO2001015219A2 (fr) 2001-03-01
TW461037B (en) 2001-10-21
US20020098679A1 (en) 2002-07-25
WO2001015219A3 (fr) 2001-07-19
US20040092093A1 (en) 2004-05-13
US6930052B2 (en) 2005-08-16
CN1192427C (zh) 2005-03-09
JP2003508896A (ja) 2003-03-04
CN1377511A (zh) 2002-10-30

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