US20020098679A1 - Method for producing an integrated circuit having at least one metalicized surface - Google Patents

Method for producing an integrated circuit having at least one metalicized surface Download PDF

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Publication number
US20020098679A1
US20020098679A1 US10/005,293 US529301A US2002098679A1 US 20020098679 A1 US20020098679 A1 US 20020098679A1 US 529301 A US529301 A US 529301A US 2002098679 A1 US2002098679 A1 US 2002098679A1
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Prior art keywords
dielectric layer
etching
thickness
layer
uncovered
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Abandoned
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US10/005,293
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English (en)
Inventor
Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ENGELHARDT, MANFRED, KREUPL, FRANZ
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SCHWARZL, SIEGFRIED
Publication of US20020098679A1 publication Critical patent/US20020098679A1/en
Priority to US10/654,054 priority Critical patent/US6930052B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • Metallization planes are used in integrated circuits to connect active components.
  • a metallization plane comprises lines and contacts via which the lines are connected to conductive structures.
  • Said contacts are often referred to as vias by experts.
  • Said conductive structures may be diffusion regions, terminal electrodes, metal contacts or lines of metallization planes arranged below the respective metallization plane. If a plurality of metallization planes arranged one above the other are provided in an integrated circuit, then this is referred to as multilayer metallization.
  • Metallization planes are increasingly being fabricated according to the so-called damascene technique.
  • a dielectric is deposited which surrounds the lines and contacts that are to be fabricated later. Holes and trenches are formed in the intermetal dielectric and are subsequently filled with metal. This produces contacts, also called vias, in the holes and the lines in the trenches.
  • the process of filling with metal is effected by PVD, CVD or electroplating and subsequent chemical mechanical polishing. This method is employed in particular if the metallization plane is formed from a metal which is difficult to etch.
  • dual damascene expresses the fact that firstly the contact holes and trenches are patterned and these are filled jointly by the deposition of metal and chemical mechanical polishing.
  • the trenches are etched and afterwards, selectively with respect to silicon nitride, the contact holes, down to the lower first silicon nitride layer.
  • the patterned upper silicon nitride layer acts as an additional mask.
  • the invention is based on the problem of specifying a method for fabricating an integrated circuit having at least one metallization plane which is suitable for fabricating metallization planes with metals that are difficult to etch and in which contaminants are avoided. This problem is solved by means of a method in accordance with claim 1. Further refinements of the invention emerge from the rest of the claims.
  • a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are applied on a surface of a substrate.
  • the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer in each case have the same etching properties.
  • the thickness of the second dielectric layer differs from the thickness of the fourth dielectric layer.
  • the thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer then, using a first etching mask, which defines the arrangement of contact holes, etching is effected through the fourth dielectric layer and the third dielectric layer into the second dielectric layer. In this case, etching is effected into the second dielectric layer to a depth such that the remaining thickness of the second dielectric layer is essentially equal to the thickness of the fourth dielectric layer.
  • etching mask which defines the arrangement of line trenches
  • firstly the fourth dielectric layer and, at the same time, the second dielectric layer are etched incompletely using a nonselective process, i.e. the etching is ended before the surface of the underlying layer is uncovered.
  • uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched until the underlying surface is uncovered in each case.
  • the surface of the third dielectric layer is uncovered, in the case of the fourth dielectric layer, and the surface of the first dielectric layer is uncovered in the case of the second dielectric layer.
  • a non-selective etching method which is optimized with regard to a high etching rate is used to etch into uncovered parts of the fourth dielectric layer and of the second dielectric layer.
  • the etching is ended before the underlying surfaces are uncovered.
  • the layer thickness that has to be etched using a selective etching process which usually has very low etching rates, is reduced. The duration of the fabrication process is thus shortened.
  • the third dielectric layer and the first dielectric layer are etched until the underlying surface is uncovered in each case.
  • the surface of the second dielectric layer is uncovered under the third dielectric layer and the surface of the substrate is uncovered under the first dielectric layer.
  • the contact holes and the line trenches are completed.
  • the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer, then, using the first etching mask, which defines the arrangement of contact holes, etching is effected into the fourth dielectric layer. In this case, etching is effected into the fourth dielectric layer to a depth such that the remaining thickness of the fourth dielectric layer is essentially equal to the thickness of the second dielectric layer.
  • a non-selective etching process is then carried out using the second etching mask, which defines the arrangement of line trenches.
  • the fourth dielectric layer has depressions at the locations of the contact holes.
  • uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched selectively with respect to the third dielectric layer and with respect to the first dielectric layer until the underlying surface of the third dielectric layer and of the first dielectric layer, respectively, is uncovered.
  • the third dielectric layer and the first dielectric layer are etched until the underlying surface of the second dielectric layer and of the substrate, respectively, is uncovered. After this etching, the contact holes and the line trenches are completed.
  • the metallization plane is completed by the formation of contacts and lines in the contact holes and the line trenches.
  • the first dielectric layer and the third dielectric layer can be formed from silicon nitride and the second dielectric layer and the fourth dielectric layer can be formed from SiO 2 , without the selectivity of the etching of SiO 2 with regard to Si 3 N 4 being adversely affected in the manner known from the literature. Therefore, the widths and heights of the line trenches and of the contact holes can be reliably controlled. Since the third dielectric layer is not uncovered prematurely, widening and beveling of the contact holes are avoided. The bottoms of the line trenches are smooth.
  • a further advantage is that in the case of the etching using the first etching mask, it is possible to employ a non-selective etching method which can be optimized with regard to the speed of etching removal.
  • a fast inexpensive etching method with a high etching rate can be employed in the case of the etching using the first etching mask, since etching selectivity is not necessary in this case.
  • the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer in each case to be provided with essentially the same material composition.
  • the first dielectric layer and the third dielectric layer are formed from an Si 3 N 4 -containing material and the second dielectric layer and the fourth dielectric layer are formed from an SiO 2 -containing material.
  • the following materials are also suitable: SiON, amorphous silicon, polysilicon, SiC, Al 2 O 3 .
  • the following materials are furthermore suitable: SiO 2 , BPSG, SOG, flare, BCB, silk, HSQ, FSG, nanoglass, parylene, PTFE, xerogels, aerogels.
  • the first dielectric layer and the third dielectric layer have essentially the same thickness.
  • the surface of the substrate is prevented from being uncovered prematurely. This prevents contamination of the side walls of the contact holes and/or line trenches by material which is present in the surface of the substrate and is removed due to premature uncovering in the sense of overetching.
  • the method is therefore particularly suitable for fabricating a metallization plane which extends to copper-containing contacts or lines.
  • any substrate which is appropriate as a support for a metallization plane is suitable as the substrate.
  • a semiconductor wafer containing an integrated circuit is suitable as the substrate.
  • the contacts to be fabricated may extend both to a metallization plane already situated above the integrated circuit and to the surface of active components of the integrated circuit.
  • the contacts may extend both to lines, contacts, diffusion regions such as, for example, source/drain regions, base regions, emitter regions, collector regions, and to doped regions of a solar cell or of a diode or terminals such as, for example, gate electrodes, source/drain terminals, or the like.
  • An integrated circuit realized using thin-film technology or an insulating support is also suitable as the substrate. In this case, the integrated circuit may be produced either before or else after the fabrication of the metallization plane.
  • FIG. 1 shows a section through a substrate on which a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are arranged.
  • FIG. 2 shows the section through the substrate after the formation of a first etching mask and etching down into the second dielectric layer.
  • FIG. 3 shows a section through the substrate after the formation of a second etching mask after partial etching.
  • FIG. 4 shows a section through the substrate after selective etching of the fourth dielectric layer and second dielectric layer.
  • FIG. 5 shows a section through the substrate after the etching of the third dielectric layer and of the first dielectric layer and the formation of contacts and lines.
  • a first dielectric layer 3 , a second dielectric layer 4 , a third dielectric layer 5 and a fourth dielectric layer 6 are applied to a substrate 1 having a conductive structure 2 (see FIG. 1).
  • the substrate 1 is a monocrystalline silicon wafer in which an integrated circuit (not specifically shown) is realized.
  • the surface of the substrate 1 is formed by a dielectric passivation layer in which the conductive structure 2 is arranged.
  • the conductive structure 2 is a copper line.
  • the first dielectric layer 3 is formed from Si 3 N 4 to a layer thickness of 50 nm by deposition in a plasma CVD process.
  • the second dielectric layer 4 is formed from SiO 2 to a layer thickness of 850 nm by deposition in a plasma CVD method.
  • the third dielectric layer 5 is formed from Si 3 N 4 to a layer thickness of 50 nm by deposition in a plasma CVD method.
  • the fourth dielectric layer 6 is formed from SiO 2 to a layer thickness of 600 nm by deposition in a plasma CVD method.
  • a first etching mask 7 made of photoresist is formed on the surface of the fourth dielectric layer 6 (see FIG. 2).
  • the first etching mask 7 defines the arrangement of contact holes.
  • a non-selective—that is to say with not very different etching rates for the dielectric films; in the best case SiO 2 /SiN selectivity 1:1—RIE process with a high etching rate using CHF 3 and CF 4 as process gas, etching is effected through the fourth dielectric layer 6 and the third dielectric layer 5 into the second dielectric layer 4 .
  • the etching process used has essentially the same etching rates for SiO 2 and Si 3 N 4 .
  • the etching is controlled over time. The etching is ended as soon as the remaining thickness of the third dielectric layer is essentially equal to the thickness of the fourth dielectric layer 6 , that is to say 600 nm.
  • the first etching mask 7 is subsequently removed by incineration and/or wet-chemically using EKC 525 (that is wet-chemical polymer removal).
  • a second etching mask 8 is subsequently produced, which defines the arrangement of line trenches (see FIG. 3).
  • etching is subsequently effected into the uncovered parts of the fourth dielectric layer 6 and of the second dielectric layer 4 .
  • the etching is controlled by way of the etching time. It is ended before the surface of the third dielectric layer 5 and of the first dielectric layer 3 , respectively, is uncovered.
  • the etching is likewise effected using CHF 3 and CF 4 .
  • the residual thickness of the second dielectric layer 4 and of the fourth dielectric layer is from 50 to 100 nm.
  • a conformal diffusion barrier layer is subsequently applied by sputtering, said layer being composed of a TaN layer having a thickness of 10 nm and a Ta layer having a thickness of 40 nm.
  • a copper seed layer is subsequently sputtered on.
  • the contact holes and line trenches are filled by electroplating with copper.
  • Parts of the copper and of the diffusion barrier layer which project beyond the line trenches are removed by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the method is ended by cleaning the substrate on both sides using a brush cleaner.
  • the structure illustrated in FIG. 5 is produced, with a metallization plane comprising the contacts 9 and the lines 10 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
US10/005,293 1999-08-25 2001-12-05 Method for producing an integrated circuit having at least one metalicized surface Abandoned US20020098679A1 (en)

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Application Number Priority Date Filing Date Title
US10/654,054 US6930052B2 (en) 1999-08-25 2003-09-03 Method for producing an integrated circuit having at least one metalicized surface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19940358.9 1999-08-25
DE19940358 1999-08-25

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US (2) US20020098679A1 (fr)
EP (1) EP1212794A2 (fr)
JP (1) JP2003508896A (fr)
KR (1) KR20020025237A (fr)
CN (1) CN1192427C (fr)
TW (1) TW461037B (fr)
WO (1) WO2001015219A2 (fr)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
US20190181360A1 (en) * 2017-12-12 2019-06-13 Samsung Display Co., Ltd. Display substrate, method of manufacturing the same, and display device including the same

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US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US20060261036A1 (en) * 2005-04-11 2006-11-23 Stmicroelectronics S.R.L. Method for patterning on a wafer having at least one substrate for the realization of an integrated circuit
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US7592253B2 (en) * 2005-12-29 2009-09-22 Dongbu Electronics Co., Ltd. Method for forming a damascene pattern of a copper metallization layer
US8188599B2 (en) * 2006-02-28 2012-05-29 Advanced Interconnect Materials, Llc Semiconductor device, its manufacturing method, and sputtering target material for use in the method
US20080303154A1 (en) * 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
DE102007054384A1 (de) 2007-11-14 2009-05-20 Institut Für Solarenergieforschung Gmbh Verfahren zum Herstellen einer Solarzelle mit einer oberflächenpassivierenden Dielektrikumdoppelschicht und entsprechende Solarzelle
TWI490939B (zh) * 2008-10-01 2015-07-01 Vanguard Int Semiconduct Corp 孔洞的形成方法
CN102543837A (zh) * 2010-12-22 2012-07-04 中芯国际集成电路制造(上海)有限公司 顶层金属互连层结构和制作方法
EP2820672A2 (fr) * 2012-03-01 2015-01-07 Koninklijke Philips N.V. Montage de circuit électronique et son procédé de fabrication
CN112018077A (zh) * 2020-07-29 2020-12-01 复旦大学 一种铜互连结构及其制造方法

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US5143820A (en) 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
KR0184158B1 (ko) * 1996-07-13 1999-04-15 문정환 반도체장치의 자기 정합정 금속 배선 형성 방법
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
US6291334B1 (en) * 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
FR2791472B1 (fr) * 1999-03-26 2002-07-05 Commissariat Energie Atomique Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique
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Publication number Priority date Publication date Assignee Title
US20190181360A1 (en) * 2017-12-12 2019-06-13 Samsung Display Co., Ltd. Display substrate, method of manufacturing the same, and display device including the same
US11183650B2 (en) * 2017-12-12 2021-11-23 Samsung Display Co., Ltd. Display substrate, method of manufacturing the same, and display device including the same

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Publication number Publication date
US6930052B2 (en) 2005-08-16
CN1377511A (zh) 2002-10-30
CN1192427C (zh) 2005-03-09
US20040092093A1 (en) 2004-05-13
TW461037B (en) 2001-10-21
WO2001015219A2 (fr) 2001-03-01
KR20020025237A (ko) 2002-04-03
EP1212794A2 (fr) 2002-06-12
JP2003508896A (ja) 2003-03-04
WO2001015219A3 (fr) 2001-07-19

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