US20020098679A1 - Method for producing an integrated circuit having at least one metalicized surface - Google Patents

Method for producing an integrated circuit having at least one metalicized surface Download PDF

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US20020098679A1
US20020098679A1 US10/005,293 US529301A US2002098679A1 US 20020098679 A1 US20020098679 A1 US 20020098679A1 US 529301 A US529301 A US 529301A US 2002098679 A1 US2002098679 A1 US 2002098679A1
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dielectric layer
etching
thickness
layer
uncovered
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Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SCHWARZL, SIEGFRIED
Publication of US20020098679A1 publication Critical patent/US20020098679A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • Metallization planes are used in integrated circuits to connect active components.
  • a metallization plane comprises lines and contacts via which the lines are connected to conductive structures.
  • Said contacts are often referred to as vias by experts.
  • Said conductive structures may be diffusion regions, terminal electrodes, metal contacts or lines of metallization planes arranged below the respective metallization plane. If a plurality of metallization planes arranged one above the other are provided in an integrated circuit, then this is referred to as multilayer metallization.
  • Metallization planes are increasingly being fabricated according to the so-called damascene technique.
  • a dielectric is deposited which surrounds the lines and contacts that are to be fabricated later. Holes and trenches are formed in the intermetal dielectric and are subsequently filled with metal. This produces contacts, also called vias, in the holes and the lines in the trenches.
  • the process of filling with metal is effected by PVD, CVD or electroplating and subsequent chemical mechanical polishing. This method is employed in particular if the metallization plane is formed from a metal which is difficult to etch.
  • dual damascene expresses the fact that firstly the contact holes and trenches are patterned and these are filled jointly by the deposition of metal and chemical mechanical polishing.
  • the trenches are etched and afterwards, selectively with respect to silicon nitride, the contact holes, down to the lower first silicon nitride layer.
  • the patterned upper silicon nitride layer acts as an additional mask.
  • the invention is based on the problem of specifying a method for fabricating an integrated circuit having at least one metallization plane which is suitable for fabricating metallization planes with metals that are difficult to etch and in which contaminants are avoided. This problem is solved by means of a method in accordance with claim 1. Further refinements of the invention emerge from the rest of the claims.
  • a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are applied on a surface of a substrate.
  • the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer in each case have the same etching properties.
  • the thickness of the second dielectric layer differs from the thickness of the fourth dielectric layer.
  • the thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer then, using a first etching mask, which defines the arrangement of contact holes, etching is effected through the fourth dielectric layer and the third dielectric layer into the second dielectric layer. In this case, etching is effected into the second dielectric layer to a depth such that the remaining thickness of the second dielectric layer is essentially equal to the thickness of the fourth dielectric layer.
  • etching mask which defines the arrangement of line trenches
  • firstly the fourth dielectric layer and, at the same time, the second dielectric layer are etched incompletely using a nonselective process, i.e. the etching is ended before the surface of the underlying layer is uncovered.
  • uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched until the underlying surface is uncovered in each case.
  • the surface of the third dielectric layer is uncovered, in the case of the fourth dielectric layer, and the surface of the first dielectric layer is uncovered in the case of the second dielectric layer.
  • a non-selective etching method which is optimized with regard to a high etching rate is used to etch into uncovered parts of the fourth dielectric layer and of the second dielectric layer.
  • the etching is ended before the underlying surfaces are uncovered.
  • the layer thickness that has to be etched using a selective etching process which usually has very low etching rates, is reduced. The duration of the fabrication process is thus shortened.
  • the third dielectric layer and the first dielectric layer are etched until the underlying surface is uncovered in each case.
  • the surface of the second dielectric layer is uncovered under the third dielectric layer and the surface of the substrate is uncovered under the first dielectric layer.
  • the contact holes and the line trenches are completed.
  • the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer, then, using the first etching mask, which defines the arrangement of contact holes, etching is effected into the fourth dielectric layer. In this case, etching is effected into the fourth dielectric layer to a depth such that the remaining thickness of the fourth dielectric layer is essentially equal to the thickness of the second dielectric layer.
  • a non-selective etching process is then carried out using the second etching mask, which defines the arrangement of line trenches.
  • the fourth dielectric layer has depressions at the locations of the contact holes.
  • uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched selectively with respect to the third dielectric layer and with respect to the first dielectric layer until the underlying surface of the third dielectric layer and of the first dielectric layer, respectively, is uncovered.
  • the third dielectric layer and the first dielectric layer are etched until the underlying surface of the second dielectric layer and of the substrate, respectively, is uncovered. After this etching, the contact holes and the line trenches are completed.
  • the metallization plane is completed by the formation of contacts and lines in the contact holes and the line trenches.
  • the first dielectric layer and the third dielectric layer can be formed from silicon nitride and the second dielectric layer and the fourth dielectric layer can be formed from SiO 2 , without the selectivity of the etching of SiO 2 with regard to Si 3 N 4 being adversely affected in the manner known from the literature. Therefore, the widths and heights of the line trenches and of the contact holes can be reliably controlled. Since the third dielectric layer is not uncovered prematurely, widening and beveling of the contact holes are avoided. The bottoms of the line trenches are smooth.
  • a further advantage is that in the case of the etching using the first etching mask, it is possible to employ a non-selective etching method which can be optimized with regard to the speed of etching removal.
  • a fast inexpensive etching method with a high etching rate can be employed in the case of the etching using the first etching mask, since etching selectivity is not necessary in this case.
  • the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer in each case to be provided with essentially the same material composition.
  • the first dielectric layer and the third dielectric layer are formed from an Si 3 N 4 -containing material and the second dielectric layer and the fourth dielectric layer are formed from an SiO 2 -containing material.
  • the following materials are also suitable: SiON, amorphous silicon, polysilicon, SiC, Al 2 O 3 .
  • the following materials are furthermore suitable: SiO 2 , BPSG, SOG, flare, BCB, silk, HSQ, FSG, nanoglass, parylene, PTFE, xerogels, aerogels.
  • the first dielectric layer and the third dielectric layer have essentially the same thickness.
  • the surface of the substrate is prevented from being uncovered prematurely. This prevents contamination of the side walls of the contact holes and/or line trenches by material which is present in the surface of the substrate and is removed due to premature uncovering in the sense of overetching.
  • the method is therefore particularly suitable for fabricating a metallization plane which extends to copper-containing contacts or lines.
  • any substrate which is appropriate as a support for a metallization plane is suitable as the substrate.
  • a semiconductor wafer containing an integrated circuit is suitable as the substrate.
  • the contacts to be fabricated may extend both to a metallization plane already situated above the integrated circuit and to the surface of active components of the integrated circuit.
  • the contacts may extend both to lines, contacts, diffusion regions such as, for example, source/drain regions, base regions, emitter regions, collector regions, and to doped regions of a solar cell or of a diode or terminals such as, for example, gate electrodes, source/drain terminals, or the like.
  • An integrated circuit realized using thin-film technology or an insulating support is also suitable as the substrate. In this case, the integrated circuit may be produced either before or else after the fabrication of the metallization plane.
  • FIG. 1 shows a section through a substrate on which a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are arranged.
  • FIG. 2 shows the section through the substrate after the formation of a first etching mask and etching down into the second dielectric layer.
  • FIG. 3 shows a section through the substrate after the formation of a second etching mask after partial etching.
  • FIG. 4 shows a section through the substrate after selective etching of the fourth dielectric layer and second dielectric layer.
  • FIG. 5 shows a section through the substrate after the etching of the third dielectric layer and of the first dielectric layer and the formation of contacts and lines.
  • a first dielectric layer 3 , a second dielectric layer 4 , a third dielectric layer 5 and a fourth dielectric layer 6 are applied to a substrate 1 having a conductive structure 2 (see FIG. 1).
  • the substrate 1 is a monocrystalline silicon wafer in which an integrated circuit (not specifically shown) is realized.
  • the surface of the substrate 1 is formed by a dielectric passivation layer in which the conductive structure 2 is arranged.
  • the conductive structure 2 is a copper line.
  • the first dielectric layer 3 is formed from Si 3 N 4 to a layer thickness of 50 nm by deposition in a plasma CVD process.
  • the second dielectric layer 4 is formed from SiO 2 to a layer thickness of 850 nm by deposition in a plasma CVD method.
  • the third dielectric layer 5 is formed from Si 3 N 4 to a layer thickness of 50 nm by deposition in a plasma CVD method.
  • the fourth dielectric layer 6 is formed from SiO 2 to a layer thickness of 600 nm by deposition in a plasma CVD method.
  • a first etching mask 7 made of photoresist is formed on the surface of the fourth dielectric layer 6 (see FIG. 2).
  • the first etching mask 7 defines the arrangement of contact holes.
  • a non-selective—that is to say with not very different etching rates for the dielectric films; in the best case SiO 2 /SiN selectivity 1:1—RIE process with a high etching rate using CHF 3 and CF 4 as process gas, etching is effected through the fourth dielectric layer 6 and the third dielectric layer 5 into the second dielectric layer 4 .
  • the etching process used has essentially the same etching rates for SiO 2 and Si 3 N 4 .
  • the etching is controlled over time. The etching is ended as soon as the remaining thickness of the third dielectric layer is essentially equal to the thickness of the fourth dielectric layer 6 , that is to say 600 nm.
  • the first etching mask 7 is subsequently removed by incineration and/or wet-chemically using EKC 525 (that is wet-chemical polymer removal).
  • a second etching mask 8 is subsequently produced, which defines the arrangement of line trenches (see FIG. 3).
  • etching is subsequently effected into the uncovered parts of the fourth dielectric layer 6 and of the second dielectric layer 4 .
  • the etching is controlled by way of the etching time. It is ended before the surface of the third dielectric layer 5 and of the first dielectric layer 3 , respectively, is uncovered.
  • the etching is likewise effected using CHF 3 and CF 4 .
  • the residual thickness of the second dielectric layer 4 and of the fourth dielectric layer is from 50 to 100 nm.
  • a conformal diffusion barrier layer is subsequently applied by sputtering, said layer being composed of a TaN layer having a thickness of 10 nm and a Ta layer having a thickness of 40 nm.
  • a copper seed layer is subsequently sputtered on.
  • the contact holes and line trenches are filled by electroplating with copper.
  • Parts of the copper and of the diffusion barrier layer which project beyond the line trenches are removed by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the method is ended by cleaning the substrate on both sides using a brush cleaner.
  • the structure illustrated in FIG. 5 is produced, with a metallization plane comprising the contacts 9 and the lines 10 .

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Abstract

In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

Description

  • Metallization planes are used in integrated circuits to connect active components. In this case, a metallization plane comprises lines and contacts via which the lines are connected to conductive structures. Said contacts are often referred to as vias by experts. Said conductive structures may be diffusion regions, terminal electrodes, metal contacts or lines of metallization planes arranged below the respective metallization plane. If a plurality of metallization planes arranged one above the other are provided in an integrated circuit, then this is referred to as multilayer metallization. [0001]
  • Metallization planes are increasingly being fabricated according to the so-called damascene technique. [0002]
  • In the damascene technique, firstly a dielectric is deposited which surrounds the lines and contacts that are to be fabricated later. Holes and trenches are formed in the intermetal dielectric and are subsequently filled with metal. This produces contacts, also called vias, in the holes and the lines in the trenches. The process of filling with metal is effected by PVD, CVD or electroplating and subsequent chemical mechanical polishing. This method is employed in particular if the metallization plane is formed from a metal which is difficult to etch. [0003]
  • The term dual damascene expresses the fact that firstly the contact holes and trenches are patterned and these are filled jointly by the deposition of metal and chemical mechanical polishing. [0004]
  • P. Singer, Semiconductor International, August 1997, page 79, K. Derbyshire, Solid State Technology, February 1998, page 26, R. L. Jackson et al., Solid State Technology, March 1998, page 49 and Y. Morand et al., 1997 Symp. On VLSI Techn. Digest of Technical Papers, 31 disclose various process variants for a dual damascene process. [0005]
  • It has been proposed (see P. Singer, Semiconductor International, August 1997, page 79) firstly to etch the trenches for the lines and then to produce the deeper contact holes. In this case, a photoresist mask that is used during the contact hole etching has to be patterned photolithographically on the uneven foundation resulting from the trench etching. In this case, problems arise, in particular in the case of deep contact holes, as a result of resist that has not been fully exposed, unresolved hole structures or hole widening in the event of overexposure. [0006]
  • As an alternative, it has been proposed (see P. Singer, Semiconductor International, August 1997, page 79) firstly to carry out the contact hole etching and then to carry out the trench etching for the lines. During the contact hole etching, there is the risk of the surface of the conductive structure, which may be, in particular, a copper interconnect, being uncovered and contaminants being applied to the walls of the contact hole. In order to avoid this, use is usually made of an etching layer made of silicon nitride, on the surface of which a silicon oxide layer is arranged in which the contact hole and the trenches are etched. However, in many etching processes the etching selectivity is limited for example by the oxygen liberated during the SiO[0007] 2 etching, so that the underlying surface is nonetheless uncovered.
  • In order to eliminate this problem, it has been proposed to protect the contact hole during the trench etching by means of a photoresist plug. However, it has been found that cavity-free filling of the contact hole with photoresist is not possible in a reproducible manner and that, moreover, the residue-free removal of photoresist from the contact holes leads to further problems. [0008]
  • As an alternative it has been proposed (see P. Singer, Semiconductor International, August 1997, page 79 and Y. Morand et al., 1997 Symp. On VLSI Techn. Digest of Technical Papers, 31), to produce as the intermetal dielectric a layer sequence comprising a first silicon nitride layer, an SiO[0009] 2 layer and a second silicon nitride layer. Firstly, the upper second silicon nitride layer is patterned, using a contact hole mask. After the contact hole mask has been removed, a second SiO2 layer is applied. Then, using a line mask, firstly the trenches are etched and afterwards, selectively with respect to silicon nitride, the contact holes, down to the lower first silicon nitride layer. During this etching process, the patterned upper silicon nitride layer acts as an additional mask. The problem of reduced selectivity on account of the oxygen liberated during the SiO2 etching occurs in this case, too.
  • The invention is based on the problem of specifying a method for fabricating an integrated circuit having at least one metallization plane which is suitable for fabricating metallization planes with metals that are difficult to etch and in which contaminants are avoided. This problem is solved by means of a method in accordance with [0010] claim 1. Further refinements of the invention emerge from the rest of the claims.
  • In the method, a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are applied on a surface of a substrate. In this case, the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer, in each case have the same etching properties. The thickness of the second dielectric layer differs from the thickness of the fourth dielectric layer. [0011]
  • If the thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer then, using a first etching mask, which defines the arrangement of contact holes, etching is effected through the fourth dielectric layer and the third dielectric layer into the second dielectric layer. In this case, etching is effected into the second dielectric layer to a depth such that the remaining thickness of the second dielectric layer is essentially equal to the thickness of the fourth dielectric layer. [0012]
  • Using a second etching mask, which defines the arrangement of line trenches, firstly the fourth dielectric layer and, at the same time, the second dielectric layer are etched incompletely using a nonselective process, i.e. the etching is ended before the surface of the underlying layer is uncovered. Then, selectively, with respect to the third dielectric layer and with respect to the first dielectric layer, uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched until the underlying surface is uncovered in each case. The surface of the third dielectric layer is uncovered, in the case of the fourth dielectric layer, and the surface of the first dielectric layer is uncovered in the case of the second dielectric layer. [0013]
  • Preferably, after the formation of the second etching mask, firstly a non-selective etching method which is optimized with regard to a high etching rate is used to etch into uncovered parts of the fourth dielectric layer and of the second dielectric layer. The etching is ended before the underlying surfaces are uncovered. In this way, the layer thickness that has to be etched using a selective etching process, which usually has very low etching rates, is reduced. The duration of the fabrication process is thus shortened. [0014]
  • Afterwards, the third dielectric layer and the first dielectric layer are etched until the underlying surface is uncovered in each case. The surface of the second dielectric layer is uncovered under the third dielectric layer and the surface of the substrate is uncovered under the first dielectric layer. After this etching, the contact holes and the line trenches are completed. [0015]
  • If the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer, then, using the first etching mask, which defines the arrangement of contact holes, etching is effected into the fourth dielectric layer. In this case, etching is effected into the fourth dielectric layer to a depth such that the remaining thickness of the fourth dielectric layer is essentially equal to the thickness of the second dielectric layer. [0016]
  • A non-selective etching process is then carried out using the second etching mask, which defines the arrangement of line trenches. As a result of the preceding etching using the first etching mask, the fourth dielectric layer has depressions at the locations of the contact holes. By employing the nonselective etching process, which etches the fourth dielectric layer, the third dielectric layer and the second dielectric layer at essentially the same etching rate, at the locations of the contact holes, etching is effected through the fourth dielectric layer and the third dielectric layer into the second dielectric layer. At the same time, etching is effected into the fourth layer at the locations of the line trenches outside the contact holes. Afterwards, uncovered parts of the fourth dielectric layer and of the second dielectric layer are etched selectively with respect to the third dielectric layer and with respect to the first dielectric layer until the underlying surface of the third dielectric layer and of the first dielectric layer, respectively, is uncovered. [0017]
  • Afterwards, the third dielectric layer and the first dielectric layer are etched until the underlying surface of the second dielectric layer and of the substrate, respectively, is uncovered. After this etching, the contact holes and the line trenches are completed. [0018]
  • The metallization plane is completed by the formation of contacts and lines in the contact holes and the line trenches. [0019]
  • Since, in the method, the surface of the first dielectric layer and third dielectric layer are uncovered essentially simultaneously during the etching using the second etching mask, the first dielectric layer and the third dielectric layer can be formed from silicon nitride and the second dielectric layer and the fourth dielectric layer can be formed from SiO[0020] 2, without the selectivity of the etching of SiO2 with regard to Si3N4 being adversely affected in the manner known from the literature. Therefore, the widths and heights of the line trenches and of the contact holes can be reliably controlled. Since the third dielectric layer is not uncovered prematurely, widening and beveling of the contact holes are avoided. The bottoms of the line trenches are smooth. A further advantage is that in the case of the etching using the first etching mask, it is possible to employ a non-selective etching method which can be optimized with regard to the speed of etching removal. In other words, a fast inexpensive etching method with a high etching rate can be employed in the case of the etching using the first etching mask, since etching selectivity is not necessary in this case.
  • In the method, firstly line trenches and contact holes are produced, in which contacts and lines of the metallization plane are subsequently formed. It is thus suitable for the fabrication of metallization planes from metals that are difficult to etch according to a damascene technique or dual damascene technique. [0021]
  • It lies within the scope of the invention for the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer, in each case to be provided with essentially the same material composition. In particular, the first dielectric layer and the third dielectric layer are formed from an Si[0022] 3N4-containing material and the second dielectric layer and the fourth dielectric layer are formed from an SiO2-containing material. Furthermore, for the first dielectric layer and the third dielectric layer, which act as an etching stop, the following materials are also suitable: SiON, amorphous silicon, polysilicon, SiC, Al2O3. For the second dielectric layer and the fourth dielectric layer, in which the greatest part of the contact holes and of the line trenches are arranged, the following materials are furthermore suitable: SiO2, BPSG, SOG, flare, BCB, silk, HSQ, FSG, nanoglass, parylene, PTFE, xerogels, aerogels.
  • Preferably, the first dielectric layer and the third dielectric layer have essentially the same thickness. In this case, during the etching of the first dielectric layer and of the third dielectric layer the surface of the substrate is prevented from being uncovered prematurely. This prevents contamination of the side walls of the contact holes and/or line trenches by material which is present in the surface of the substrate and is removed due to premature uncovering in the sense of overetching. The method is therefore particularly suitable for fabricating a metallization plane which extends to copper-containing contacts or lines. [0023]
  • Any substrate which is appropriate as a support for a metallization plane is suitable as the substrate. In particular, a semiconductor wafer containing an integrated circuit is suitable as the substrate. In this case, the contacts to be fabricated may extend both to a metallization plane already situated above the integrated circuit and to the surface of active components of the integrated circuit. The contacts may extend both to lines, contacts, diffusion regions such as, for example, source/drain regions, base regions, emitter regions, collector regions, and to doped regions of a solar cell or of a diode or terminals such as, for example, gate electrodes, source/drain terminals, or the like. An integrated circuit realized using thin-film technology or an insulating support is also suitable as the substrate. In this case, the integrated circuit may be produced either before or else after the fabrication of the metallization plane.[0024]
  • An exemplary embodiment of the invention is explained in more detail below with reference to figures. [0025]
  • FIG. 1 shows a section through a substrate on which a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are arranged. [0026]
  • FIG. 2 shows the section through the substrate after the formation of a first etching mask and etching down into the second dielectric layer. [0027]
  • FIG. 3 shows a section through the substrate after the formation of a second etching mask after partial etching. [0028]
  • FIG. 4 shows a section through the substrate after selective etching of the fourth dielectric layer and second dielectric layer. [0029]
  • FIG. 5 shows a section through the substrate after the etching of the third dielectric layer and of the first dielectric layer and the formation of contacts and lines.[0030]
  • A [0031] first dielectric layer 3, a second dielectric layer 4, a third dielectric layer 5 and a fourth dielectric layer 6 are applied to a substrate 1 having a conductive structure 2 (see FIG. 1). The substrate 1 is a monocrystalline silicon wafer in which an integrated circuit (not specifically shown) is realized. The surface of the substrate 1 is formed by a dielectric passivation layer in which the conductive structure 2 is arranged. The conductive structure 2 is a copper line.
  • The first [0032] dielectric layer 3 is formed from Si3N4 to a layer thickness of 50 nm by deposition in a plasma CVD process. The second dielectric layer 4 is formed from SiO2 to a layer thickness of 850 nm by deposition in a plasma CVD method. The third dielectric layer 5 is formed from Si3N4 to a layer thickness of 50 nm by deposition in a plasma CVD method. The fourth dielectric layer 6 is formed from SiO2 to a layer thickness of 600 nm by deposition in a plasma CVD method.
  • A first etching mask [0033] 7 made of photoresist is formed on the surface of the fourth dielectric layer 6 (see FIG. 2). The first etching mask 7 defines the arrangement of contact holes. In a non-selective—that is to say with not very different etching rates for the dielectric films; in the best case SiO2/SiN selectivity=1:1—RIE process with a high etching rate using CHF3 and CF4 as process gas, etching is effected through the fourth dielectric layer 6 and the third dielectric layer 5 into the second dielectric layer 4. The etching process used has essentially the same etching rates for SiO2 and Si3N4. The etching is controlled over time. The etching is ended as soon as the remaining thickness of the third dielectric layer is essentially equal to the thickness of the fourth dielectric layer 6, that is to say 600 nm.
  • The first etching mask [0034] 7 is subsequently removed by incineration and/or wet-chemically using EKC 525 (that is wet-chemical polymer removal).
  • A [0035] second etching mask 8 is subsequently produced, which defines the arrangement of line trenches (see FIG. 3). In an RIE process with a high etching rate, etching is subsequently effected into the uncovered parts of the fourth dielectric layer 6 and of the second dielectric layer 4. The etching is controlled by way of the etching time. It is ended before the surface of the third dielectric layer 5 and of the first dielectric layer 3, respectively, is uncovered. The etching is likewise effected using CHF3 and CF4. The residual thickness of the second dielectric layer 4 and of the fourth dielectric layer is from 50 to 100 nm.
  • Selective etching is then effected in an RIE process using C[0036] 4F8 and CO, with or without O2 (both are possible) as process gas. A high selectivity in the etching of SiO2 with respect to Si3N4 is obtained in this case. The etching is continued until the surface of the first dielectric layer 3 and of the third dielectric layer 5 is uncovered. Over etching is not necessary since the surface of the first dielectric layer 3 and of the third dielectric layer 5 are uncovered essentially simultaneously (see FIG. 4). After the removal of the second etching mask by incineration and wet-chemical polymer removal using EKC 525, the uncovered parts of the first dielectric layer 3 and of the third dielectric layer 5 are removed. The etching is effected in an RIE process using CF4 and Ar with a low RF power of 250 W and a diameter of the substrate wafer of 6′. After this etching, the contact holes and the line trenches are completed.
  • In order to complete [0037] contacts 9 and lines 10, a conformal diffusion barrier layer is subsequently applied by sputtering, said layer being composed of a TaN layer having a thickness of 10 nm and a Ta layer having a thickness of 40 nm. A copper seed layer is subsequently sputtered on. The contact holes and line trenches are filled by electroplating with copper. Parts of the copper and of the diffusion barrier layer which project beyond the line trenches are removed by chemical mechanical polishing (CMP). The method is ended by cleaning the substrate on both sides using a brush cleaner. The structure illustrated in FIG. 5 is produced, with a metallization plane comprising the contacts 9 and the lines 10.

Claims (7)

1. A method for fabricating an integrated circuit having at least one metallization plane,
in which a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are applied to a surface of a substrate, in each case the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer, having the same etching properties and the thickness of the second dielectric layer differing from the thickness of the fourth dielectric layer,
in which, using a first etching mask, which defines the arrangement of contact holes if the thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer, etching is effected through the fourth dielectric layer and the third dielectric layer into the second dielectric layer to a depth such that the remaining thickness of the second dielectric layer is essentially equal to the thickness of the fourth dielectric layer, and, if the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer, etching is effected into the fourth dielectric layer to a depth such that the remaining thickness of the fourth dielectric layer is essentially equal to the thickness of the second dielectric layer,
in which, using a second etching mask, which defines the arrangement of line trenches, firstly a non-selective etching process is carried out, by means of which etching is effected into the fourth dielectric layer and the second dielectric layer without the surface of the underlying third dielectric layer and first dielectric layer being uncovered, and then the fourth dielectric layer and the second dielectric layer are etched selectively with respect to the third dielectric layer and selectively with respect to the first dielectric layer until the underlying surfaces of the first and of the third dielectric layer are uncovered in each case,
in which the third dielectric layer and the first dielectric layer are etched until the underlying surface is uncovered in each case,
in which metal-containing contacts and lines of the metallization plane are produced in the contact holes and in the line trenches.
2. The method as claimed in claim 1,
in which the etching of the fourth dielectric layer, of the third dielectric layer and of the second dielectric layer using the first etching mask is carried out with the aid of a non-selective etching process.
3. The method as claimed in claim 1 or 2,
in which in each case the first dielectric layer and the third dielectric layer, and the second dielectric layer and the fourth dielectric layer, have essentially the same material composition.
4. The method as claimed in claim 3,
in which the first dielectric layer and the third dielectric layer contain Si3N4 and the second dielectric layer and the fourth dielectric layer contain SiO2.
5. The method as claimed in one of claims 1 to 4,
in which the first dielectric layer and the third dielectric layer have essentially the same thickness.
6. The method as claimed in one of claims 1 to 5,
in which the contacts and interconnects are formed by the deposition and planarization of metal.
7. The method as claimed in one of claims 1 to 6,
in which the contacts and/or the interconnects contain copper.
US10/005,293 1999-08-25 2001-12-05 Method for producing an integrated circuit having at least one metalicized surface Abandoned US20020098679A1 (en)

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TW461037B (en) 2001-10-21
CN1192427C (en) 2005-03-09
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US20040092093A1 (en) 2004-05-13
KR20020025237A (en) 2002-04-03

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