DE69923769D1 - Asynchrones halbleiterspeicher-fliessband - Google Patents

Asynchrones halbleiterspeicher-fliessband

Info

Publication number
DE69923769D1
DE69923769D1 DE69923769T DE69923769T DE69923769D1 DE 69923769 D1 DE69923769 D1 DE 69923769D1 DE 69923769 T DE69923769 T DE 69923769T DE 69923769 T DE69923769 T DE 69923769T DE 69923769 D1 DE69923769 D1 DE 69923769D1
Authority
DE
Germany
Prior art keywords
asynchrones
semiconductor member
member tape
tape
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69923769T
Other languages
English (en)
Other versions
DE69923769T2 (de
Inventor
Ian Mes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA2233789A external-priority patent/CA2233789C/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of DE69923769D1 publication Critical patent/DE69923769D1/de
Application granted granted Critical
Publication of DE69923769T2 publication Critical patent/DE69923769T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69923769T 1998-04-01 1999-04-01 Asynchrones halbleiterspeicher-fliessband Expired - Lifetime DE69923769T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
CA2233789 1998-04-01
CA2233789A CA2233789C (en) 1998-04-01 1998-04-01 Semiconductor memory asynchronous pipeline
US09/129,878 US6539454B2 (en) 1998-04-01 1998-08-06 Semiconductor memory asynchronous pipeline
US129878 1998-08-06
PCT/CA1999/000282 WO1999050852A1 (en) 1998-04-01 1999-04-01 Semiconductor memory asynchronous pipeline

Publications (2)

Publication Number Publication Date
DE69923769D1 true DE69923769D1 (de) 2005-03-24
DE69923769T2 DE69923769T2 (de) 2006-02-02

Family

ID=25680118

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69923769T Expired - Lifetime DE69923769T2 (de) 1998-04-01 1999-04-01 Asynchrones halbleiterspeicher-fliessband

Country Status (7)

Country Link
US (8) US6772312B2 (de)
EP (1) EP1068619B1 (de)
JP (1) JP2002510118A (de)
CN (1) CN1154111C (de)
AU (1) AU3021799A (de)
DE (1) DE69923769T2 (de)
WO (1) WO1999050852A1 (de)

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US7800974B2 (en) * 2008-02-21 2010-09-21 Freescale Semiconductor, Inc. Adjustable pipeline in a memory circuit
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US8711639B2 (en) 2010-11-02 2014-04-29 Micron Technology, Inc. Data paths using a first signal to capture data and a second signal to output data and methods for providing data
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KR102200489B1 (ko) * 2014-05-30 2021-01-11 삼성전자주식회사 비휘발성 메모리 장치 및 그것을 포함하는 저장 장치
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US10074417B2 (en) * 2014-11-20 2018-09-11 Rambus Inc. Memory systems and methods for improved power management
US9747252B2 (en) * 2015-02-05 2017-08-29 Weng Tianxiang Systematic method of coding wave-pipelined circuits in HDL
US10019170B2 (en) * 2016-03-30 2018-07-10 Micron Technology, Inc. Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal
KR20180072316A (ko) 2016-12-21 2018-06-29 에스케이하이닉스 주식회사 반도체장치
US10170166B1 (en) 2017-09-08 2019-01-01 Winbond Electronics Corp. Data transmission apparatus for memory and data transmission method thereof
KR102585218B1 (ko) 2017-09-28 2023-10-05 삼성전자주식회사 비휘발성 메모리 장치 및 그것을 포함하는 저장 장치
US10360956B2 (en) 2017-12-07 2019-07-23 Micron Technology, Inc. Wave pipeline
US10410698B2 (en) * 2017-12-07 2019-09-10 Micron Technology, Inc. Skew reduction of a wave pipeline in a memory device
KR102517462B1 (ko) * 2018-04-23 2023-04-05 에스케이하이닉스 주식회사 반도체장치
KR102708728B1 (ko) 2019-01-15 2024-09-23 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US11061836B2 (en) * 2019-06-21 2021-07-13 Micron Technology, Inc. Wave pipeline including synchronous stage
US11526441B2 (en) 2019-08-19 2022-12-13 Truememory Technology, LLC Hybrid memory systems with cache management
US11055220B2 (en) 2019-08-19 2021-07-06 Truememorytechnology, LLC Hybrid memory systems with cache management
US20230008476A1 (en) * 2021-07-06 2023-01-12 UPBEAT TECHNOLOGY Co., Ltd Error detection and correction method and circuit

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Also Published As

Publication number Publication date
US20110202713A1 (en) 2011-08-18
WO1999050852A1 (en) 1999-10-07
US7865685B2 (en) 2011-01-04
EP1068619B1 (de) 2005-02-16
EP1068619A1 (de) 2001-01-17
US7178001B2 (en) 2007-02-13
US8122218B2 (en) 2012-02-21
AU3021799A (en) 1999-10-18
US9548088B2 (en) 2017-01-17
JP2002510118A (ja) 2002-04-02
US7509469B2 (en) 2009-03-24
US20090175103A1 (en) 2009-07-09
US20120144131A1 (en) 2012-06-07
US8078821B2 (en) 2011-12-13
US20070186034A1 (en) 2007-08-09
US20140089575A1 (en) 2014-03-27
US20050033899A1 (en) 2005-02-10
CN1296624A (zh) 2001-05-23
US8601231B2 (en) 2013-12-03
CN1154111C (zh) 2004-06-16
US20100217928A1 (en) 2010-08-26
US6772312B2 (en) 2004-08-03
US20030065900A1 (en) 2003-04-03
DE69923769T2 (de) 2006-02-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA

8328 Change in the person/name/address of the agent

Representative=s name: MARKS & CLERK (LUXEMBOURG) LLP, LUXEMBOURG, LU