DE69739354D1 - Halbleiteranordnung und deren Herstellungsverfahren - Google Patents

Halbleiteranordnung und deren Herstellungsverfahren

Info

Publication number
DE69739354D1
DE69739354D1 DE69739354T DE69739354T DE69739354D1 DE 69739354 D1 DE69739354 D1 DE 69739354D1 DE 69739354 T DE69739354 T DE 69739354T DE 69739354 T DE69739354 T DE 69739354T DE 69739354 D1 DE69739354 D1 DE 69739354D1
Authority
DE
Germany
Prior art keywords
production method
semiconductor arrangement
semiconductor
arrangement
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69739354T
Other languages
English (en)
Inventor
Toshiki Yabu
Mizuki Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17044263&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69739354(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of DE69739354D1 publication Critical patent/DE69739354D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
DE69739354T 1996-09-10 1997-09-09 Halbleiteranordnung und deren Herstellungsverfahren Expired - Lifetime DE69739354D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23940396A JP3305211B2 (ja) 1996-09-10 1996-09-10 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE69739354D1 true DE69739354D1 (de) 2009-05-28

Family

ID=17044263

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739354T Expired - Lifetime DE69739354D1 (de) 1996-09-10 1997-09-09 Halbleiteranordnung und deren Herstellungsverfahren

Country Status (5)

Country Link
US (4) US5989992A (de)
EP (1) EP0831529B1 (de)
JP (1) JP3305211B2 (de)
KR (1) KR100411782B1 (de)
DE (1) DE69739354D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US6143638A (en) * 1997-12-31 2000-11-07 Intel Corporation Passivation structure and its method of fabrication
US6875681B1 (en) * 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
JPH11261010A (ja) * 1998-03-13 1999-09-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0949672A3 (de) * 1998-04-08 2002-09-11 Texas Instruments Incorporated PO Fliess für Kupfermetallisierung
KR100285701B1 (ko) * 1998-06-29 2001-04-02 윤종용 트렌치격리의제조방법및그구조
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6358831B1 (en) * 1999-03-03 2002-03-19 Taiwan Semiconductor Manufacturing Company Method for forming a top interconnection level and bonding pads on an integrated circuit chip
JP4460669B2 (ja) 1999-03-19 2010-05-12 株式会社東芝 半導体装置
JP3530073B2 (ja) * 1999-05-25 2004-05-24 株式会社東芝 半導体装置及びその製造方法
US6423625B1 (en) * 1999-08-30 2002-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Method of improving the bondability between Au wires and Cu bonding pads
JP2002016065A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体装置
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
JP2002353307A (ja) * 2001-05-25 2002-12-06 Toshiba Corp 半導体装置
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
KR100471401B1 (ko) * 2002-12-27 2005-03-10 주식회사 하이닉스반도체 반도체소자의 콘택 패드 형성 방법
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US5989992A (en) 1999-11-23
JPH1092817A (ja) 1998-04-10
USRE41980E1 (en) 2010-12-07
EP0831529A2 (de) 1998-03-25
KR19980024496A (ko) 1998-07-06
EP0831529B1 (de) 2009-04-15
EP0831529A3 (de) 2000-02-02
US6232656B1 (en) 2001-05-15
USRE39932E1 (en) 2007-12-04
KR100411782B1 (ko) 2004-04-29

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