DE69633423D1 - Verfahren zur Herstellung eines mit einer dünnen ferroelektrischen Schicht überdeckten Substrats - Google Patents

Verfahren zur Herstellung eines mit einer dünnen ferroelektrischen Schicht überdeckten Substrats

Info

Publication number
DE69633423D1
DE69633423D1 DE69633423T DE69633423T DE69633423D1 DE 69633423 D1 DE69633423 D1 DE 69633423D1 DE 69633423 T DE69633423 T DE 69633423T DE 69633423 T DE69633423 T DE 69633423T DE 69633423 D1 DE69633423 D1 DE 69633423D1
Authority
DE
Germany
Prior art keywords
producing
ferroelectric layer
substrate covered
thin ferroelectric
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69633423T
Other languages
English (en)
Other versions
DE69633423T2 (de
Inventor
Sakiko Satoh
Takeshi Kijima
Hironori Matsunaga
Masayoshi Koba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69633423D1 publication Critical patent/DE69633423D1/de
Application granted granted Critical
Publication of DE69633423T2 publication Critical patent/DE69633423T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69633423T 1995-06-09 1996-05-02 Verfahren zur Herstellung eines mit einer dünnen ferroelektrischen Schicht überdeckten Substrats Expired - Lifetime DE69633423T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16811995 1995-06-09
JP07168119A JP3133922B2 (ja) 1995-06-09 1995-06-09 強誘電体薄膜被覆基板、その製造方法、及びキャパシタ構造素子

Publications (2)

Publication Number Publication Date
DE69633423D1 true DE69633423D1 (de) 2004-10-28
DE69633423T2 DE69633423T2 (de) 2005-09-29

Family

ID=15862209

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69633423T Expired - Lifetime DE69633423T2 (de) 1995-06-09 1996-05-02 Verfahren zur Herstellung eines mit einer dünnen ferroelektrischen Schicht überdeckten Substrats

Country Status (4)

Country Link
US (2) US5757061A (de)
EP (1) EP0747937B1 (de)
JP (1) JP3133922B2 (de)
DE (1) DE69633423T2 (de)

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KR100275121B1 (ko) 1997-12-30 2001-01-15 김영환 강유전체 캐패시터 제조방법
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KR100324589B1 (ko) * 1998-12-24 2002-04-17 박종섭 반도체 소자의 강유전체 캐패시터 제조방법
US6316797B1 (en) * 1999-02-19 2001-11-13 Advanced Technology Materials, Inc. Scalable lead zirconium titanate(PZT) thin film material and deposition method, and ferroelectric memory device structures comprising such thin film material
US6369452B1 (en) * 1999-07-27 2002-04-09 International Business Machines Corporation Cap attach surface modification for improved adhesion
TW456027B (en) * 1999-08-18 2001-09-21 Matsushita Electronics Corp Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory
JP3596416B2 (ja) * 2000-03-29 2004-12-02 セイコーエプソン株式会社 セラミックスの製造方法およびその製造装置
JP2002170938A (ja) 2000-04-28 2002-06-14 Sharp Corp 半導体装置およびその製造方法
US6617206B1 (en) * 2000-06-07 2003-09-09 Micron Technology, Inc. Method of forming a capacitor structure
JP4257485B2 (ja) * 2000-06-21 2009-04-22 セイコーエプソン株式会社 セラミックス膜およびその製造方法ならびに半導体装置および圧電素子
US6705708B2 (en) * 2001-02-09 2004-03-16 Seiko Espon Corporation Piezoelectric thin-film element, ink-jet head using the same, and method for manufacture thereof
US6562633B2 (en) * 2001-02-26 2003-05-13 International Business Machines Corporation Assembling arrays of small particles using an atomic force microscope to define ferroelectric domains
JP4182329B2 (ja) 2001-09-28 2008-11-19 セイコーエプソン株式会社 圧電体薄膜素子およびその製造方法、ならびにこれを用いた液体吐出ヘッド及び液体吐出装置
KR20030039893A (ko) 2001-11-16 2003-05-22 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 제조방법
US6534326B1 (en) * 2002-03-13 2003-03-18 Sharp Laboratories Of America, Inc. Method of minimizing leakage current and improving breakdown voltage of polycrystalline memory thin films
KR20040070564A (ko) * 2003-02-04 2004-08-11 삼성전자주식회사 강유전체 커패시터 및 그 제조방법
WO2004079311A1 (ja) 2003-03-07 2004-09-16 Fujitsu Limited 電磁放射線センサ及びその製造方法
WO2004109804A1 (ja) * 2003-06-06 2004-12-16 Fujitsu Limited 半導体装置の製造方法
KR100548247B1 (ko) * 2003-07-01 2006-02-02 엘지전자 주식회사 지터 대응 플라즈마 디스플레이 패널 소자
KR100649580B1 (ko) * 2003-12-15 2006-11-28 삼성전기주식회사 스핀코팅에 의한 적층세라믹 커패시터의 제조방법 및적층세라믹 커패시터
US20100221894A1 (en) * 2006-12-28 2010-09-02 Industry-Academic Cooperation Foundation, Yonsei University Method for manufacturing nanowires by using a stress-induced growth
US7916513B2 (en) * 2008-11-05 2011-03-29 Seagate Technology Llc Non-destructive read back for ferroelectric data storage device
US20130153813A1 (en) * 2010-07-27 2013-06-20 Youtec Co. Ltd. Poling treatment method, plasma poling device, piezoelectric substance, and manfacturing method therefor
JP6011760B2 (ja) * 2011-12-08 2016-10-19 セイコーエプソン株式会社 圧電素子の製造方法及び液体噴射ヘッドの製造方法並びに液体噴射装置の製造方法
WO2014024695A1 (ja) * 2012-08-08 2014-02-13 コニカミノルタ株式会社 圧電素子、圧電デバイス、インクジェットヘッドおよびインクジェットプリンタ
KR102613029B1 (ko) 2018-10-17 2023-12-12 삼성전자주식회사 커패시터 구조물 및 이를 구비하는 반도체 소자
KR102180620B1 (ko) * 2019-01-24 2020-11-18 구창영 비납계 페로브스카이트 압전 박막 및 그 제조 방법

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JPH03108770A (ja) * 1989-09-22 1991-05-08 Olympus Optical Co Ltd 強誘電体メモリ
JPH03108192A (ja) * 1989-09-22 1991-05-08 Olympus Optical Co Ltd 強誘電体メモリ
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WO1994010704A1 (en) * 1992-10-23 1994-05-11 Symetrix Corporation Integrated circuit with layered superlattice material and method of fabricating same
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JPH06334140A (ja) * 1992-12-16 1994-12-02 Ricoh Co Ltd 強誘電体材料および該材料を用いた半導体メモリ、光記録媒体ならびに微小変位制御素子
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JP3113141B2 (ja) * 1993-12-28 2000-11-27 シャープ株式会社 強誘電体結晶薄膜被覆基板、その製造方法及び強誘電体結晶薄膜被覆基板を用いた強誘電体薄膜デバイス
US5426075A (en) * 1994-06-15 1995-06-20 Ramtron International Corporation Method of manufacturing ferroelectric bismuth layered oxides
JP3476932B2 (ja) * 1994-12-06 2003-12-10 シャープ株式会社 強誘電体薄膜及び強誘電体薄膜被覆基板並びに強誘電体薄膜の製造方法

Also Published As

Publication number Publication date
JPH08340085A (ja) 1996-12-24
JP3133922B2 (ja) 2001-02-13
EP0747937B1 (de) 2004-09-22
US6232167B1 (en) 2001-05-15
EP0747937A3 (de) 1997-10-15
US5757061A (en) 1998-05-26
EP0747937A2 (de) 1996-12-11
DE69633423T2 (de) 2005-09-29

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