DE69610252D1 - Verfahren zum Zurückätzen einer Schicht auf einem Substrat - Google Patents

Verfahren zum Zurückätzen einer Schicht auf einem Substrat

Info

Publication number
DE69610252D1
DE69610252D1 DE69610252T DE69610252T DE69610252D1 DE 69610252 D1 DE69610252 D1 DE 69610252D1 DE 69610252 T DE69610252 T DE 69610252T DE 69610252 T DE69610252 T DE 69610252T DE 69610252 D1 DE69610252 D1 DE 69610252D1
Authority
DE
Germany
Prior art keywords
substrate
layer
etching back
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69610252T
Other languages
English (en)
Other versions
DE69610252T2 (de
Inventor
Hiroshi Takahashi
Kazuhiko Tokunaga
Shunichi Yoshigoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69610252D1 publication Critical patent/DE69610252D1/de
Publication of DE69610252T2 publication Critical patent/DE69610252T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)
DE69610252T 1995-05-15 1996-05-07 Verfahren zum Zurückätzen einer Schicht auf einem Substrat Expired - Fee Related DE69610252T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11606995 1995-05-15
JP30440895A JP3438446B2 (ja) 1995-05-15 1995-11-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69610252D1 true DE69610252D1 (de) 2000-10-19
DE69610252T2 DE69610252T2 (de) 2001-04-05

Family

ID=26454448

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69610252T Expired - Fee Related DE69610252T2 (de) 1995-05-15 1996-05-07 Verfahren zum Zurückätzen einer Schicht auf einem Substrat

Country Status (5)

Country Link
US (1) US5736462A (de)
EP (1) EP0743674B1 (de)
JP (1) JP3438446B2 (de)
KR (1) KR960042997A (de)
DE (1) DE69610252T2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
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US6225230B1 (en) * 1996-05-28 2001-05-01 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
TW388096B (en) * 1996-06-10 2000-04-21 Texas Instruments Inc Integrated circuit insulator and method
JP3688816B2 (ja) * 1996-07-16 2005-08-31 株式会社東芝 半導体装置の製造方法
JP3571887B2 (ja) * 1996-10-18 2004-09-29 キヤノン株式会社 アクティブマトリクス基板及び液晶装置
JPH10217149A (ja) * 1997-02-05 1998-08-18 Ebara Corp ターンテーブル用クロスの剥離治具
US6117777A (en) * 1997-07-30 2000-09-12 Chartered Semiconductor Manufacturing Co. Chemical mechanical polish (CMP) endpoint detection by colorimetry
DE19733391C2 (de) * 1997-08-01 2001-08-16 Siemens Ag Strukturierungsverfahren
US5943590A (en) * 1997-09-15 1999-08-24 Winbond Electronics Corp. Method for improving the planarity of shallow trench isolation
US6143625A (en) * 1997-11-19 2000-11-07 Texas Instruments Incorporated Protective liner for isolation trench side walls and method
JP3519589B2 (ja) * 1997-12-24 2004-04-19 株式会社ルネサステクノロジ 半導体集積回路の製造方法
US6228769B1 (en) * 1998-05-06 2001-05-08 International Business Machines Corporation Endpoint detection by chemical reaction and photoionization
US6066564A (en) * 1998-05-06 2000-05-23 International Business Machines Corporation Indirect endpoint detection by chemical reaction
US6268224B1 (en) 1998-06-30 2001-07-31 Lsi Logic Corporation Method and apparatus for detecting an ion-implanted polishing endpoint layer within a semiconductor wafer
US6077783A (en) * 1998-06-30 2000-06-20 Lsi Logic Corporation Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer
US6241847B1 (en) 1998-06-30 2001-06-05 Lsi Logic Corporation Method and apparatus for detecting a polishing endpoint based upon infrared signals
US6071818A (en) 1998-06-30 2000-06-06 Lsi Logic Corporation Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material
TW418459B (en) * 1998-06-30 2001-01-11 Fujitsu Ltd Semiconductor device manufacturing method
US6285035B1 (en) 1998-07-08 2001-09-04 Lsi Logic Corporation Apparatus for detecting an endpoint polishing layer of a semiconductor wafer having a wafer carrier with independent concentric sub-carriers and associated method
US6074517A (en) * 1998-07-08 2000-06-13 Lsi Logic Corporation Method and apparatus for detecting an endpoint polishing layer by transmitting infrared light signals through a semiconductor wafer
US6080670A (en) * 1998-08-10 2000-06-27 Lsi Logic Corporation Method of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specie
US5972787A (en) * 1998-08-18 1999-10-26 International Business Machines Corp. CMP process using indicator areas to determine endpoint
US6201253B1 (en) 1998-10-22 2001-03-13 Lsi Logic Corporation Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system
US6121147A (en) * 1998-12-11 2000-09-19 Lsi Logic Corporation Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance
US6117779A (en) 1998-12-15 2000-09-12 Lsi Logic Corporation Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint
US6316276B1 (en) 1998-12-17 2001-11-13 Lsi Lgoic Corporation Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance
DE19946493C2 (de) * 1999-09-28 2002-05-16 Infineon Technologies Ag Verfahren zum Abtragen von Schichten
US7751609B1 (en) 2000-04-20 2010-07-06 Lsi Logic Corporation Determination of film thickness during chemical mechanical polishing
US6645825B1 (en) 2000-07-12 2003-11-11 Taiwan Semiconductor Manufacturing Company Planarization of shallow trench isolation (STI)
TWI228538B (en) * 2000-10-23 2005-03-01 Kao Corp Polishing composition
US6593238B1 (en) * 2000-11-27 2003-07-15 Motorola, Inc. Method for determining an endpoint and semiconductor wafer
US6664190B2 (en) 2001-09-14 2003-12-16 Chartered Semiconductor Manufacturing Ltd. Pre STI-CMP planarization scheme
US6741913B2 (en) * 2001-12-11 2004-05-25 International Business Machines Corporation Technique for noise reduction in a torque-based chemical-mechanical polishing endpoint detection system
JP2003318140A (ja) * 2002-04-26 2003-11-07 Applied Materials Inc 研磨方法及び装置
US7102206B2 (en) 2003-01-20 2006-09-05 Matsushita Electric Industrial Co., Ltd. Semiconductor substrate, method for fabricating the same, and method for fabricating semiconductor device
US20050197048A1 (en) * 2004-03-04 2005-09-08 Leping Li Method for manufacturing a workpiece and torque transducer module
JP2006245036A (ja) * 2005-02-28 2006-09-14 Seiko Epson Corp 素子分離層の形成方法及び電子デバイスの製造方法、ｃｍｐ装置
US8497210B2 (en) 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
US9825128B2 (en) * 2015-10-20 2017-11-21 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911562A (en) * 1974-01-14 1975-10-14 Signetics Corp Method of chemical polishing of planar silicon structures having filled grooves therein
JPS6039835A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 基板表面の平坦化方法
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JPH0311091A (ja) * 1989-06-06 1991-01-18 Toray Ind Inc 新規白金（２）錯体および悪性腫瘍治療剤
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
JP3208575B2 (ja) * 1991-08-16 2001-09-17 ソニー株式会社 半導体装置の製法
US5376222A (en) * 1991-09-04 1994-12-27 Fujitsu Limited Polishing method for polycrystalline silicon
US5246884A (en) * 1991-10-30 1993-09-21 International Business Machines Corporation Cvd diamond or diamond-like carbon for chemical-mechanical polish etch stop
JP2946920B2 (ja) * 1992-03-09 1999-09-13 日本電気株式会社 半導体装置の製造方法
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
GB2275129B (en) * 1992-05-26 1997-01-08 Toshiba Kk Method for planarizing a layer on a semiconductor wafer
JP3190742B2 (ja) * 1992-10-12 2001-07-23 株式会社東芝 研磨方法
JPH07111962B2 (ja) * 1992-11-27 1995-11-29 日本電気株式会社 選択平坦化ポリッシング方法
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
JPH07235537A (ja) * 1994-02-23 1995-09-05 Mitsubishi Electric Corp 表面が平坦化された半導体装置およびその製造方法
JPH07249626A (ja) * 1994-03-10 1995-09-26 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0936073A (ja) 1997-02-07
EP0743674A3 (de) 1998-02-25
EP0743674B1 (de) 2000-09-13
KR960042997A (de) 1996-12-21
EP0743674A2 (de) 1996-11-20
DE69610252T2 (de) 2001-04-05
JP3438446B2 (ja) 2003-08-18
US5736462A (en) 1998-04-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee