DE69507987T2 - Halbleiteranordnung mit einer MOS-Gate-Struktur und einem Oberflächenschutzfilm und Verfahren zur Herstellung - Google Patents

Halbleiteranordnung mit einer MOS-Gate-Struktur und einem Oberflächenschutzfilm und Verfahren zur Herstellung

Info

Publication number
DE69507987T2
DE69507987T2 DE69507987T DE69507987T DE69507987T2 DE 69507987 T2 DE69507987 T2 DE 69507987T2 DE 69507987 T DE69507987 T DE 69507987T DE 69507987 T DE69507987 T DE 69507987T DE 69507987 T2 DE69507987 T2 DE 69507987T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
gate structure
protection film
surface protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69507987T
Other languages
English (en)
Other versions
DE69507987D1 (de
Inventor
Mitsuhiro Yano
Kouichi Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69507987D1 publication Critical patent/DE69507987D1/de
Application granted granted Critical
Publication of DE69507987T2 publication Critical patent/DE69507987T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
DE69507987T 1994-05-31 1995-05-12 Halbleiteranordnung mit einer MOS-Gate-Struktur und einem Oberflächenschutzfilm und Verfahren zur Herstellung Expired - Lifetime DE69507987T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11838694A JP3275536B2 (ja) 1994-05-31 1994-05-31 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69507987D1 DE69507987D1 (de) 1999-04-08
DE69507987T2 true DE69507987T2 (de) 1999-07-29

Family

ID=14735408

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69507987T Expired - Lifetime DE69507987T2 (de) 1994-05-31 1995-05-12 Halbleiteranordnung mit einer MOS-Gate-Struktur und einem Oberflächenschutzfilm und Verfahren zur Herstellung

Country Status (5)

Country Link
US (2) US5945692A (de)
EP (1) EP0685890B1 (de)
JP (1) JP3275536B2 (de)
KR (1) KR100211185B1 (de)
DE (1) DE69507987T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012018611B3 (de) * 2012-09-20 2013-10-24 Infineon Technologies Ag Chiprandversiegelung

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4765104B2 (ja) * 1998-11-11 2011-09-07 富士電機株式会社 超接合半導体素子の製造方法
JP3612226B2 (ja) * 1998-12-21 2005-01-19 株式会社東芝 半導体装置及び半導体モジュール
EP1156528B1 (de) * 2000-05-08 2006-08-30 STMicroelectronics S.r.l. Elektrische Verbindungsstruktur für elektronische Leistungsbauelemente und Verbindungsmethode
JP3701227B2 (ja) * 2001-10-30 2005-09-28 三菱電機株式会社 半導体装置及びその製造方法
JP2003347547A (ja) * 2002-05-27 2003-12-05 Mitsubishi Electric Corp 電力用半導体装置及びその製造方法
US6972582B2 (en) * 2003-02-10 2005-12-06 Solid State Measurements, Inc. Apparatus and method for measuring semiconductor wafer electrical properties
JP4721653B2 (ja) * 2004-05-12 2011-07-13 トヨタ自動車株式会社 絶縁ゲート型半導体装置
JP2008543031A (ja) * 2005-05-24 2008-11-27 アーベーベー・シュバイツ・アーゲー カソードセル設計
JP5477681B2 (ja) 2008-07-29 2014-04-23 三菱電機株式会社 半導体装置
JP5195186B2 (ja) * 2008-09-05 2013-05-08 三菱電機株式会社 半導体装置の製造方法
JP5609876B2 (ja) * 2009-08-28 2014-10-22 サンケン電気株式会社 半導体装置
JP5671867B2 (ja) * 2010-08-04 2015-02-18 富士電機株式会社 半導体装置およびその製造方法
JP6324914B2 (ja) * 2010-11-25 2018-05-16 三菱電機株式会社 炭化珪素半導体装置
JP5708124B2 (ja) * 2011-03-25 2015-04-30 三菱電機株式会社 半導体装置
JP2013074181A (ja) * 2011-09-28 2013-04-22 Toyota Motor Corp 半導体装置とその製造方法
JP6248392B2 (ja) * 2013-01-17 2017-12-20 富士電機株式会社 半導体装置
CN104347403B (zh) * 2013-07-31 2017-11-14 无锡华润上华科技有限公司 一种绝缘栅双极性晶体管的制造方法
JP6107767B2 (ja) * 2013-12-27 2017-04-05 トヨタ自動車株式会社 半導体装置とその製造方法
WO2016170978A1 (ja) * 2015-04-20 2016-10-27 富士電機株式会社 半導体装置
JP6380666B2 (ja) 2015-04-20 2018-08-29 富士電機株式会社 半導体装置
JP7345354B2 (ja) * 2019-10-25 2023-09-15 三菱電機株式会社 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161744A (en) * 1977-05-23 1979-07-17 Varo Semiconductor, Inc. Passivated semiconductor device and method of making same
US4364073A (en) * 1980-03-25 1982-12-14 Rca Corporation Power MOSFET with an anode region
JPS58171861A (ja) * 1982-04-01 1983-10-08 Toshiba Corp 半導体装置
JPS6273766A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 半導体装置
US4798810A (en) 1986-03-10 1989-01-17 Siliconix Incorporated Method for manufacturing a power MOS transistor
US4814283A (en) * 1988-04-08 1989-03-21 General Electric Company Simple automated discretionary bonding of multiple parallel elements
JPH01265524A (ja) * 1988-04-15 1989-10-23 Sony Corp 半導体装置
JPH02153570A (ja) * 1988-12-06 1990-06-13 Toshiba Corp 半導体素子
JP2908818B2 (ja) * 1989-09-18 1999-06-21 株式会社日立製作所 半導体装置の製造方法
JPH0457330A (ja) * 1990-06-27 1992-02-25 Olympus Optical Co Ltd 半導体装置
JPH04130631A (ja) * 1990-09-20 1992-05-01 Fuji Electric Co Ltd 半導体装置の製造方法
JP2870553B2 (ja) * 1990-11-08 1999-03-17 富士電機株式会社 高耐圧半導体装置
US5404040A (en) * 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
JP3207559B2 (ja) 1992-10-27 2001-09-10 株式会社東芝 Ｍｏｓ駆動型半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012018611B3 (de) * 2012-09-20 2013-10-24 Infineon Technologies Ag Chiprandversiegelung
DE102013015724A1 (de) 2012-09-20 2014-03-20 Infineon Technologies Ag Chiprandversiegelung
US9054150B2 (en) 2012-09-20 2015-06-09 Infineon Technologies Ag Chip edge sealing

Also Published As

Publication number Publication date
DE69507987D1 (de) 1999-04-08
EP0685890B1 (de) 1999-03-03
KR100211185B1 (ko) 2001-05-02
EP0685890A1 (de) 1995-12-06
JP3275536B2 (ja) 2002-04-15
KR950034599A (ko) 1995-12-28
JPH07326744A (ja) 1995-12-12
USRE41866E1 (en) 2010-10-26
US5945692A (en) 1999-08-31

Similar Documents

Publication Publication Date Title
DE69507987T2 (de) Halbleiteranordnung mit einer MOS-Gate-Struktur und einem Oberflächenschutzfilm und Verfahren zur Herstellung
DE69403593D1 (de) Gerät und Verfahren zur Herstellung einer Halbleitervorrichtung
DE69425632T2 (de) Verfahren zur Herstellung einer kristallisierten Halbleiterschicht und diese verwendender Halbleitervorrichtungen
DE69514201D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69530232D1 (de) Halbleiteranordnung mit isoliertem Gate und Verfahren zur Herstellung derselben
DE69526895D1 (de) Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe
DE69418302T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung mit ebener Oberfläche
DE69432615D1 (de) Halbleiteranordnung mit einer gerichteten nichtmonocristallinen Siliziumdünnschicht und Verfahren zur Herstellung
DE69421592D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69503532T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69431023D1 (de) Halbleiteraufbau und Verfahren zur Herstellung
DE69527827D1 (de) Halbleiteranordnung mit einer dünnen Polysilicium-Schicht und Verfahren zur Herstellung
DE69320572T2 (de) Dünnfilm-Halbleiteranordnung und Verfahren zur ihrer Herstellung
DE69415500D1 (de) Verfahren zur Herstellung eines Halbleiterbauteils mit vergrabenem Übergang
DE69523576D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit selbstjustiertem Polycid
DE69229314T2 (de) Halbleiteranordnung und Verfahren zur Herstellung
DE69227290D1 (de) Halbleiteranordnung und Verfahren zur Herstellung
DE69528683D1 (de) Halbleiterbauteil und Verfahren zur Herstellung desselben
DE69416619D1 (de) Halbleiterspeicheranordnung und Verfahren zur Herstellung
DE69637697D1 (de) Verfahren zur Herstellung einer MOSFET-Halbleiteranordnung mit vermindertem Gateoxidfeld im Aus-Zustand
DE69321049D1 (de) Halbleiteranordnung mit Seitenwand-Gate und Verfahren zur Herstellung
DE69520121T2 (de) Halbleiteranordnung mit einem Isolationsgraben und Verfahren zur Herstellung
DE69413276D1 (de) Halbleiteranordnung mit isoliertem Gate und Verfahren zur Herstellung derselben
DE68916412T2 (de) Halbleiteranordnung mit einem eingefügten Gate und Verfahren zur Herstellung.
DE69511992D1 (de) Halbleiteranordnung und Verfahren zur Herstellung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)