DE69520121T2 - Halbleiteranordnung mit einem Isolationsgraben und Verfahren zur Herstellung - Google Patents

Halbleiteranordnung mit einem Isolationsgraben und Verfahren zur Herstellung

Info

Publication number
DE69520121T2
DE69520121T2 DE1995620121 DE69520121T DE69520121T2 DE 69520121 T2 DE69520121 T2 DE 69520121T2 DE 1995620121 DE1995620121 DE 1995620121 DE 69520121 T DE69520121 T DE 69520121T DE 69520121 T2 DE69520121 T2 DE 69520121T2
Authority
DE
Germany
Prior art keywords
manufacture
semiconductor device
isolation trench
trench
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1995620121
Other languages
English (en)
Other versions
DE69520121D1 (de
Inventor
Dylan Wyn Evans
David Ralph Guite
Martin Andrew Henry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Publication of DE69520121D1 publication Critical patent/DE69520121D1/de
Application granted granted Critical
Publication of DE69520121T2 publication Critical patent/DE69520121T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
DE1995620121 1994-05-31 1995-05-31 Halbleiteranordnung mit einem Isolationsgraben und Verfahren zur Herstellung Expired - Fee Related DE69520121T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9410874A GB9410874D0 (en) 1994-05-31 1994-05-31 Semiconductor device incorporating an isolating trench and manufacture thereof

Publications (2)

Publication Number Publication Date
DE69520121D1 DE69520121D1 (de) 2001-03-29
DE69520121T2 true DE69520121T2 (de) 2001-09-13

Family

ID=10755956

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1995620121 Expired - Fee Related DE69520121T2 (de) 1994-05-31 1995-05-31 Halbleiteranordnung mit einem Isolationsgraben und Verfahren zur Herstellung

Country Status (3)

Country Link
EP (1) EP0685882B1 (de)
DE (1) DE69520121T2 (de)
GB (1) GB9410874D0 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994202A (en) * 1997-01-23 1999-11-30 International Business Machines Corporation Threshold voltage tailoring of the corner of a MOSFET device
US5783476A (en) * 1997-06-26 1998-07-21 Siemens Aktiengesellschaft Integrated circuit devices including shallow trench isolation
JP4328405B2 (ja) 1999-03-16 2009-09-09 株式会社デルタツーリング ３次元ネットを有するクッション部材
DE102011010248B3 (de) * 2011-02-03 2012-07-12 Infineon Technologies Ag Ein Verfahren zum Herstellen eines Halbleiterbausteins
CN103633008B (zh) * 2012-08-20 2018-03-30 中国科学院微电子研究所 浅沟槽隔离制造方法
TWI612661B (zh) * 2017-01-05 2018-01-21 立錡科技股份有限公司 改善臨界電壓下滑的金屬氧化物半導體元件及金屬氧化物半導體元件的臨界電壓下滑改善方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111436A (ja) * 1983-11-22 1985-06-17 Toshiba Corp 半導体装置の製造方法
US4653177A (en) * 1985-07-25 1987-03-31 At&T Bell Laboratories Method of making and selectively doping isolation trenches utilized in CMOS devices
IT1225636B (it) * 1988-12-15 1990-11-22 Sgs Thomson Microelectronics Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio

Also Published As

Publication number Publication date
DE69520121D1 (de) 2001-03-29
GB9410874D0 (en) 1994-07-20
EP0685882B1 (de) 2001-02-21
EP0685882A1 (de) 1995-12-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee