DE69506646T2 - Verfahren zum Herstellen einer Halbleitereinrichtung - Google Patents

Verfahren zum Herstellen einer Halbleitereinrichtung

Info

Publication number
DE69506646T2
DE69506646T2 DE69506646T DE69506646T DE69506646T2 DE 69506646 T2 DE69506646 T2 DE 69506646T2 DE 69506646 T DE69506646 T DE 69506646T DE 69506646 T DE69506646 T DE 69506646T DE 69506646 T2 DE69506646 T2 DE 69506646T2
Authority
DE
Germany
Prior art keywords
layer
gate
forming
electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69506646T
Other languages
German (de)
English (en)
Other versions
DE69506646D1 (de
Inventor
Kazuhiro C/O Murata Manufac. Co. Ltd. Nagaokakyo-Shi Kyoto-Fu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of DE69506646D1 publication Critical patent/DE69506646D1/de
Application granted granted Critical
Publication of DE69506646T2 publication Critical patent/DE69506646T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
    • H10D64/0125—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors characterised by the sectional shape, e.g. T or inverted T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes

Landscapes

  • Junction Field-Effect Transistors (AREA)
DE69506646T 1994-09-12 1995-08-08 Verfahren zum Herstellen einer Halbleitereinrichtung Expired - Fee Related DE69506646T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06217513A JP3077524B2 (ja) 1994-09-12 1994-09-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69506646D1 DE69506646D1 (de) 1999-01-28
DE69506646T2 true DE69506646T2 (de) 1999-06-17

Family

ID=16705414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69506646T Expired - Fee Related DE69506646T2 (de) 1994-09-12 1995-08-08 Verfahren zum Herstellen einer Halbleitereinrichtung

Country Status (6)

Country Link
US (1) US5712175A (enExample)
EP (1) EP0701272B1 (enExample)
JP (1) JP3077524B2 (enExample)
KR (1) KR100195293B1 (enExample)
DE (1) DE69506646T2 (enExample)
FI (1) FI110642B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283621A (ja) * 1996-04-10 1997-10-31 Murata Mfg Co Ltd 半導体装置のｔ型ゲート電極形成方法およびその構造
JP2780704B2 (ja) * 1996-06-14 1998-07-30 日本電気株式会社 半導体装置の製造方法
JP4093395B2 (ja) * 2001-08-03 2008-06-04 富士通株式会社 半導体装置とその製造方法
TW569077B (en) * 2003-05-13 2004-01-01 Univ Nat Chiao Tung Method for fabricating nanometer gate in semiconductor device using thermally reflowed resist technology
US8878245B2 (en) 2006-11-30 2014-11-04 Cree, Inc. Transistors and method for making ohmic contact to transistors
US8368100B2 (en) * 2007-11-14 2013-02-05 Cree, Inc. Semiconductor light emitting diodes having reflective structures and methods of fabricating same
US9634191B2 (en) * 2007-11-14 2017-04-25 Cree, Inc. Wire bond free wafer level LED
US8384115B2 (en) * 2008-08-01 2013-02-26 Cree, Inc. Bond pad design for enhancing light extraction from LED chips
US8741715B2 (en) * 2009-04-29 2014-06-03 Cree, Inc. Gate electrodes for millimeter-wave operation and methods of fabrication
JP5521447B2 (ja) 2009-09-07 2014-06-11 富士通株式会社 半導体装置の製造方法
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
USD826871S1 (en) 2014-12-11 2018-08-28 Cree, Inc. Light emitting diode device
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块
WO2020214227A2 (en) 2019-04-04 2020-10-22 Hrl Laboratories, Llc Miniature field plate t-gate and method of fabricating the same
CN113097307B (zh) * 2021-03-31 2022-07-19 浙江集迈科微电子有限公司 GaN器件结构及其制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135773A (ja) * 1983-01-24 1984-08-04 Nec Corp 半導体装置の製造方法
US4959326A (en) * 1988-12-22 1990-09-25 Siemens Aktiengesellschaft Fabricating T-gate MESFETS employing double exposure, double develop techniques
JPH0414212A (ja) * 1990-05-02 1992-01-20 Dainippon Printing Co Ltd レジストパターン形成方法
FR2663155B1 (fr) * 1990-06-12 1997-01-24 Thomson Composants Microondes Procede de realisation d'une grille de transistor.
US5147812A (en) * 1992-04-01 1992-09-15 Motorola, Inc. Fabrication method for a sub-micron geometry semiconductor device
DE4228836A1 (de) * 1992-08-29 1994-03-03 Daimler Benz Ag Selbstjustierendes Verfahren zur Herstellung von Feldeffekttransistoren
JP3082469B2 (ja) * 1992-09-22 2000-08-28 株式会社村田製作所 ゲート電極の形成方法

Also Published As

Publication number Publication date
EP0701272A2 (en) 1996-03-13
FI954241A0 (fi) 1995-09-11
FI110642B (fi) 2003-02-28
EP0701272B1 (en) 1998-12-16
US5712175A (en) 1998-01-27
JP3077524B2 (ja) 2000-08-14
KR100195293B1 (ko) 1999-06-15
JPH0883809A (ja) 1996-03-26
KR960012550A (ko) 1996-04-20
DE69506646D1 (de) 1999-01-28
FI954241L (fi) 1996-03-13
EP0701272A3 (enExample) 1996-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee