DE69125078T2 - Halbleiter-Speichersystem - Google Patents

Halbleiter-Speichersystem

Info

Publication number
DE69125078T2
DE69125078T2 DE69125078T DE69125078T DE69125078T2 DE 69125078 T2 DE69125078 T2 DE 69125078T2 DE 69125078 T DE69125078 T DE 69125078T DE 69125078 T DE69125078 T DE 69125078T DE 69125078 T2 DE69125078 T2 DE 69125078T2
Authority
DE
Germany
Prior art keywords
storage system
semiconductor storage
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125078T
Other languages
English (en)
Other versions
DE69125078D1 (de
Inventor
Masahiro Mizuno
Takashi Fujita
Hiroshi Baba
Keizo Hama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69125078D1 publication Critical patent/DE69125078D1/de
Publication of DE69125078T2 publication Critical patent/DE69125078T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/822—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for read only memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE69125078T 1990-08-09 1991-07-03 Halbleiter-Speichersystem Expired - Fee Related DE69125078T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2211362A JPH0498342A (ja) 1990-08-09 1990-08-09 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69125078D1 DE69125078D1 (de) 1997-04-17
DE69125078T2 true DE69125078T2 (de) 1997-11-13

Family

ID=16604715

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125078T Expired - Fee Related DE69125078T2 (de) 1990-08-09 1991-07-03 Halbleiter-Speichersystem

Country Status (6)

Country Link
US (1) US5357473A (de)
EP (1) EP0476247B1 (de)
JP (1) JPH0498342A (de)
KR (1) KR950000550B1 (de)
CA (1) CA2044441C (de)
DE (1) DE69125078T2 (de)

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US5828599A (en) * 1996-08-06 1998-10-27 Simtek Corporation Memory with electrically erasable and programmable redundancy
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US6560733B1 (en) * 1999-07-09 2003-05-06 Micron Technology, Inc. Soft error detection for digital signal processors
WO2001071725A1 (de) * 2000-03-23 2001-09-27 Infineon Technologies Ag Verfahren und vorrichtung zum verarbeiten von fehleradressen
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US6865702B2 (en) * 2001-04-09 2005-03-08 Micron Technology, Inc. Synchronous flash memory with test code input
US7162668B2 (en) * 2001-04-19 2007-01-09 Micron Technology, Inc. Memory with element redundancy
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WO2003044732A1 (fr) * 2001-11-23 2003-05-30 Netac Technology Co., Ltd. Procede de fabrication de dispositif a memoire a semiconducteurs et dispositif portant des interfaces multiples
AU2003255254A1 (en) * 2002-08-08 2004-02-25 Glenn J. Leedy Vertical system integration
JP4518951B2 (ja) * 2002-10-28 2010-08-04 サンディスク コーポレイション 不揮発性記憶システムにおける自動損耗均等化
US20040088614A1 (en) * 2002-11-01 2004-05-06 Ting-Chin Wu Management system for defective memory
US7174486B2 (en) * 2002-11-22 2007-02-06 International Business Machines Corporation Automation of fuse compression for an ASIC design system
US7203874B2 (en) * 2003-05-08 2007-04-10 Micron Technology, Inc. Error detection, documentation, and correction in a flash memory device
US20050039089A1 (en) * 2003-08-11 2005-02-17 Elias Gedamu System and method for analysis of cache array test data
JP2007533060A (ja) * 2004-04-14 2007-11-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ データメモリ内の誤りを訂正するデータ処理デバイス
US7275190B2 (en) 2004-11-08 2007-09-25 Micron Technology, Inc. Memory block quality identification in a memory device
JP2006196758A (ja) * 2005-01-14 2006-07-27 Renesas Technology Corp 半導体装置
US8072834B2 (en) 2005-08-25 2011-12-06 Cypress Semiconductor Corporation Line driver circuit and method with standby mode of operation
TWI309044B (en) * 2006-11-20 2009-04-21 Nanya Technology Corp Method for repairing defects in memory and related memory system
EP2095234B1 (de) * 2006-11-21 2014-04-09 Freescale Semiconductor, Inc. Speichersystem mit ecc-einheit und weitere verarbeitungsanordnung
US8001444B2 (en) * 2007-08-08 2011-08-16 Intel Corporation ECC functional block placement in a multi-channel mass storage device
JP2009146070A (ja) * 2007-12-12 2009-07-02 Nec Computertechno Ltd トレーサビリティシステム、メモリモジュール故障のトレーサビリティ方法およびプログラム
TWI354224B (en) * 2008-01-22 2011-12-11 Elan Microelectronics Corp Interpreting architecture of multi-finger gesture
JP2008217811A (ja) * 2008-04-03 2008-09-18 Hitachi Ltd 不揮発メモリを使用したディスク制御装置
US7768847B2 (en) 2008-04-09 2010-08-03 Rambus Inc. Programmable memory repair scheme
KR101471574B1 (ko) * 2008-04-10 2014-12-24 삼성전자주식회사 반도체 칩과 반도체 장치
JP5188328B2 (ja) * 2008-08-29 2013-04-24 株式会社日立製作所 半導体装置
US7881134B2 (en) * 2008-11-17 2011-02-01 Micron Technology, Inc. Replacing defective columns of memory cells in response to external addresses
US8527838B2 (en) 2009-07-31 2013-09-03 Cleversafe, Inc. Memory controller utilizing an error coding dispersal function
JP5853219B2 (ja) * 2011-07-01 2016-02-09 パナソニックＩｐマネジメント株式会社 メモリアクセス制御装置、及び製造方法
US9087613B2 (en) * 2012-02-29 2015-07-21 Samsung Electronics Co., Ltd. Device and method for repairing memory cell and memory system including the device
US9953725B2 (en) * 2012-02-29 2018-04-24 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of operating the same
US8933715B2 (en) * 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
KR102083266B1 (ko) 2013-11-29 2020-03-03 삼성전자주식회사 반도체 메모리 장치의 테스트 방법 및 반도체 메모리 시스템
US9299457B2 (en) * 2014-02-23 2016-03-29 Qualcomm Incorporated Kernel masking of DRAM defects
US9690520B2 (en) 2014-06-30 2017-06-27 International Business Machines Corporation Recovering an encoded data slice in a dispersed storage network
JP6779821B2 (ja) * 2017-03-24 2020-11-04 キオクシア株式会社 メモリシステム及びデータの読み出し方法
CN111679792B (zh) * 2020-06-04 2023-04-07 四川九州电子科技股份有限公司 一种嵌入式设备NandFlash I/O数据监测系统及方法

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Also Published As

Publication number Publication date
CA2044441A1 (en) 1992-02-10
KR950000550B1 (ko) 1995-01-24
DE69125078D1 (de) 1997-04-17
JPH0498342A (ja) 1992-03-31
CA2044441C (en) 1996-01-02
EP0476247A1 (de) 1992-03-25
US5357473A (en) 1994-10-18
EP0476247B1 (de) 1997-03-12
KR920005163A (ko) 1992-03-28

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee