DE69130150T2 - Halbleiteranordnung - Google Patents

Halbleiteranordnung

Info

Publication number
DE69130150T2
DE69130150T2 DE69130150T DE69130150T DE69130150T2 DE 69130150 T2 DE69130150 T2 DE 69130150T2 DE 69130150 T DE69130150 T DE 69130150T DE 69130150 T DE69130150 T DE 69130150T DE 69130150 T2 DE69130150 T2 DE 69130150T2
Authority
DE
Germany
Prior art keywords
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130150T
Other languages
English (en)
Other versions
DE69130150D1 (de
Inventor
Yasuhisa Hirabayashi
Takashi Sakuda
Kazuhiko Ookawa
Yasuhiro Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE69130150D1 publication Critical patent/DE69130150D1/de
Application granted granted Critical
Publication of DE69130150T2 publication Critical patent/DE69130150T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE69130150T 1990-06-15 1991-06-11 Halbleiteranordnung Expired - Fee Related DE69130150T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15703590 1990-06-15
JP15703690 1990-06-15
PCT/JP1991/000784 WO1991020094A1 (en) 1990-06-15 1991-06-11 Semiconductor device

Publications (2)

Publication Number Publication Date
DE69130150D1 DE69130150D1 (de) 1998-10-15
DE69130150T2 true DE69130150T2 (de) 1999-04-15

Family

ID=26484620

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130150T Expired - Fee Related DE69130150T2 (de) 1990-06-15 1991-06-11 Halbleiteranordnung

Country Status (7)

Country Link
EP (1) EP0486699B1 (de)
JP (1) JP3186059B2 (de)
KR (1) KR920702548A (de)
DE (1) DE69130150T2 (de)
HK (1) HK1009307A1 (de)
SG (1) SG63558A1 (de)
WO (1) WO1991020094A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6017930A (ja) * 1983-07-09 1985-01-29 Fujitsu Ltd マスタ・スライス方式に於ける基本セル
JPS60254631A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd 半導体集積回路
US4884115A (en) * 1987-02-27 1989-11-28 Siemens Aktiengesellschaft Basic cell for a gate array arrangement in CMOS Technology
JP2868016B2 (ja) * 1988-12-28 1999-03-10 沖電気工業株式会社 ゲートアレイの基本セル

Also Published As

Publication number Publication date
EP0486699B1 (de) 1998-09-09
EP0486699A1 (de) 1992-05-27
DE69130150D1 (de) 1998-10-15
KR920702548A (ko) 1992-09-04
EP0486699A4 (en) 1992-06-24
JP3186059B2 (ja) 2001-07-11
HK1009307A1 (en) 1999-10-15
SG63558A1 (en) 1999-03-30
WO1991020094A1 (en) 1991-12-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee