DE69105334T2 - Gestapelte Bitleitungs-Architektur für Speicherzellenmatrix hoher Dichte vom Typ "cross-point". - Google Patents

Gestapelte Bitleitungs-Architektur für Speicherzellenmatrix hoher Dichte vom Typ "cross-point".

Info

Publication number
DE69105334T2
DE69105334T2 DE69105334T DE69105334T DE69105334T2 DE 69105334 T2 DE69105334 T2 DE 69105334T2 DE 69105334 T DE69105334 T DE 69105334T DE 69105334 T DE69105334 T DE 69105334T DE 69105334 T2 DE69105334 T2 DE 69105334T2
Authority
DE
Germany
Prior art keywords
cross
point
memory cell
bit line
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69105334T
Other languages
English (en)
Other versions
DE69105334D1 (de
Inventor
Christopher Martin Chu
Sang H Dhong
Wei Hwang
Nicky C C Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69105334D1 publication Critical patent/DE69105334D1/de
Publication of DE69105334T2 publication Critical patent/DE69105334T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE69105334T 1990-04-20 1991-03-01 Gestapelte Bitleitungs-Architektur für Speicherzellenmatrix hoher Dichte vom Typ "cross-point". Expired - Lifetime DE69105334T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/513,315 US5107459A (en) 1990-04-20 1990-04-20 Stacked bit-line architecture for high density cross-point memory cell array

Publications (2)

Publication Number Publication Date
DE69105334D1 DE69105334D1 (de) 1995-01-12
DE69105334T2 true DE69105334T2 (de) 1995-05-24

Family

ID=24042739

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69105334T Expired - Lifetime DE69105334T2 (de) 1990-04-20 1991-03-01 Gestapelte Bitleitungs-Architektur für Speicherzellenmatrix hoher Dichte vom Typ "cross-point".

Country Status (4)

Country Link
US (1) US5107459A (de)
EP (1) EP0452648B1 (de)
JP (1) JPH0644610B2 (de)
DE (1) DE69105334T2 (de)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
DE102006010762B3 (de) * 2006-03-08 2007-10-04 Infineon Technologies Ag Integrierter Halbleiterspeicher

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US5866928A (en) * 1996-07-16 1999-02-02 Micron Technology, Inc. Single digit line with cell contact interconnect
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US6297129B2 (en) * 1997-04-22 2001-10-02 Micron Technology, Inc. Methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry
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US6025221A (en) * 1997-08-22 2000-02-15 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
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US6528837B2 (en) * 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
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US5956286A (en) * 1997-10-28 1999-09-21 International Business Machines Corporation Data processing system and method for implementing a multi-port memory cell
US5877976A (en) * 1997-10-28 1999-03-02 International Business Machines Corporation Memory system having a vertical bitline topology and method therefor
US5870349A (en) * 1997-10-28 1999-02-09 International Business Machines Corporation Data processing system and method for generating memory control signals with clock skew tolerance
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US6236079B1 (en) 1997-12-02 2001-05-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having a trench capacitor
US6069815A (en) * 1997-12-18 2000-05-30 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line and/or word line architecture
US6025225A (en) * 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
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US6174767B1 (en) * 1998-05-11 2001-01-16 Vanguard International Semiconductor Corporation Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
KR100300047B1 (ko) * 1998-05-30 2001-09-22 김영환 노이즈 간섭 방지를 위한 데이터라인 배열 구조를 갖는 반도체 메모리 소자
JP3657781B2 (ja) * 1998-07-09 2005-06-08 株式会社東芝 半導体装置及びこれを用いたｌｓｉの不良解析方法
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
JP3374820B2 (ja) * 1999-01-08 2003-02-10 セイコーエプソン株式会社 出力バッファ回路
US6249451B1 (en) 1999-02-08 2001-06-19 Kabushiki Kaisha Toshiba Data line connections with twisting scheme technical field
US6188598B1 (en) * 1999-09-28 2001-02-13 Infineon Technologies North America Corp. Reducing impact of coupling noise
US6282113B1 (en) * 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
DE19948571A1 (de) * 1999-10-08 2001-04-19 Infineon Technologies Ag Speicheranordnung
US7259464B1 (en) * 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
US6339241B1 (en) 2000-06-23 2002-01-15 International Business Machines Corporation Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch
US6496402B1 (en) * 2000-10-17 2002-12-17 Intel Corporation Noise suppression for open bit line DRAM architectures
US6500706B1 (en) * 2001-03-19 2002-12-31 Taiwan Semiconductor Manufacturing Company Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM
US6569745B2 (en) * 2001-06-28 2003-05-27 Sharp Laboratories Of America, Inc. Shared bit line cross point memory array
US6639859B2 (en) * 2001-10-25 2003-10-28 Hewlett-Packard Development Company, L.P. Test array and method for testing memory arrays
US6894231B2 (en) * 2002-03-19 2005-05-17 Broadcom Corporation Bus twisting scheme for distributed coupling and low power
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
FR2885727B1 (fr) * 2005-05-13 2007-07-20 St Microelectronics Sa Plan de memoire morte a lignes de bit torsadees
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) * 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
JP4840720B2 (ja) * 2005-10-06 2011-12-21 セイコーエプソン株式会社 半導体記憶装置および電子機器
US7700441B2 (en) * 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) * 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) * 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7683417B2 (en) * 2007-10-26 2010-03-23 Texas Instruments Incorporated Memory device with memory cell including MuGFET and fin capacitor
JP5106151B2 (ja) * 2008-01-28 2012-12-26 株式会社東芝 積層型スタックｎａｎｄメモリ及び半導体装置
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US10607687B2 (en) 2017-12-28 2020-03-31 Micron Technology, Inc. Apparatuses and methods for sense line architectures for semiconductor memories
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006010762B3 (de) * 2006-03-08 2007-10-04 Infineon Technologies Ag Integrierter Halbleiterspeicher
US7719868B2 (en) 2006-03-08 2010-05-18 Qimonda Ag Integrated semiconductor memory

Also Published As

Publication number Publication date
US5107459A (en) 1992-04-21
JPH0644610B2 (ja) 1994-06-08
DE69105334D1 (de) 1995-01-12
EP0452648B1 (de) 1994-11-30
JPH04226070A (ja) 1992-08-14
EP0452648A1 (de) 1991-10-23

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Legal Events

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8364 No opposition during term of opposition
8330 Complete renunciation