DE602004005291D1 - Verfahren und Schaltungsanordnung zur Datenrückgewinnung - Google Patents

Verfahren und Schaltungsanordnung zur Datenrückgewinnung

Info

Publication number
DE602004005291D1
DE602004005291D1 DE602004005291T DE602004005291T DE602004005291D1 DE 602004005291 D1 DE602004005291 D1 DE 602004005291D1 DE 602004005291 T DE602004005291 T DE 602004005291T DE 602004005291 T DE602004005291 T DE 602004005291T DE 602004005291 D1 DE602004005291 D1 DE 602004005291D1
Authority
DE
Germany
Prior art keywords
circuit
data recovery
recovery
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004005291T
Other languages
English (en)
Other versions
DE602004005291T2 (de
Inventor
Naruhiro Masui
Hidetoshi Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Publication of DE602004005291D1 publication Critical patent/DE602004005291D1/de
Application granted granted Critical
Publication of DE602004005291T2 publication Critical patent/DE602004005291T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
DE602004005291T 2003-12-05 2004-12-03 Verfahren und Schaltungsanordnung zur Datenrückgewinnung Active DE602004005291T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003407613 2003-12-05
JP2003407613 2003-12-05
JP2004292809 2004-10-05
JP2004292809A JP4480536B2 (ja) 2003-12-05 2004-10-05 データリカバリ方法およびデータリカバリ回路

Publications (2)

Publication Number Publication Date
DE602004005291D1 true DE602004005291D1 (de) 2007-04-26
DE602004005291T2 DE602004005291T2 (de) 2007-12-20

Family

ID=34467862

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004005291T Active DE602004005291T2 (de) 2003-12-05 2004-12-03 Verfahren und Schaltungsanordnung zur Datenrückgewinnung

Country Status (4)

Country Link
US (1) US7684531B2 (de)
EP (1) EP1538775B1 (de)
JP (1) JP4480536B2 (de)
DE (1) DE602004005291T2 (de)

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US9041452B2 (en) * 2010-01-27 2015-05-26 Silicon Laboratories Inc. Circuit and method of clocking multiple digital circuits in multiple phases
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US9203541B2 (en) * 2012-09-28 2015-12-01 Intel Corporation Methods and apparatus for multiphase sampling of modulated light
US9218532B2 (en) 2012-09-28 2015-12-22 Intel Corporation Light ID error detection and correction for light receiver position determination
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US9590728B2 (en) 2012-09-29 2017-03-07 Intel Corporation Integrated photogrammetric light communications positioning and inertial navigation system positioning
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US9721627B2 (en) * 2013-10-04 2017-08-01 Cavium, Inc. Method and apparatus for aligning signals
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JP6819219B2 (ja) * 2016-10-28 2021-01-27 富士通株式会社 クロック再生回路，半導体集積回路装置およびｒｆタグ
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JP7393079B2 (ja) * 2019-03-26 2023-12-06 ラピスセミコンダクタ株式会社 半導体装置
US12013423B2 (en) 2020-09-30 2024-06-18 Macom Technology Solutions Holdings, Inc. TIA bandwidth testing system and method
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Also Published As

Publication number Publication date
JP4480536B2 (ja) 2010-06-16
US7684531B2 (en) 2010-03-23
JP2005192192A (ja) 2005-07-14
EP1538775A1 (de) 2005-06-08
DE602004005291T2 (de) 2007-12-20
US20050135527A1 (en) 2005-06-23
EP1538775B1 (de) 2007-03-14

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