JP6819219B2 - クロック再生回路,半導体集積回路装置およびrfタグ - Google Patents
クロック再生回路,半導体集積回路装置およびrfタグ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 38
- 230000001172 regenerating effect Effects 0.000 title description 2
- 238000004891 communication Methods 0.000 claims description 21
- 239000000872 buffer Substances 0.000 claims description 20
- 230000008929 regeneration Effects 0.000 claims description 18
- 238000011069 regeneration method Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 29
- 238000000034 method Methods 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 5
- 230000036760 body temperature Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 3
- 102000012677 DET1 Human genes 0.000 description 3
- 101150113651 DET1 gene Proteins 0.000 description 3
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 101100510617 Caenorhabditis elegans sel-8 gene Proteins 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 101100421135 Caenorhabditis elegans sel-5 gene Proteins 0.000 description 1
- 101100421142 Mus musculus Selenon gene Proteins 0.000 description 1
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
- G06K7/10366—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the interrogation device being adapted for miscellaneous applications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
- H04B10/114—Indoor or close-range type systems
- H04B10/1143—Bidirectional transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
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- Computer Vision & Pattern Recognition (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
1a センサ本体回路部
1b,201 近距離無線通信回路部(NFC)
1c リアルタイムクロック生成回路(RTC)
1d バッテリ
2 リーダライタ(リーダ,スマートフォン)
3 クロック再生回路(CDR回路)
11,21 アンテナ
12 電源生成回路
13 復調回路
14 送信回路/変調回路
15 制御回路
16 センサI/F
17 不揮発性メモリ
30,154 多相クロック生成回路(電圧制御発振器:VCO)
101 パワーマネジメントユニット
102 マイクロコントローラユニット(MCU)
103 センサ
104,202 BLE制御部
105 アナログフロントエンド(アナログFE)
106 ロジック部
150 PLL回路(PLL)
156 復調器(復調回路)
151 8分周器
152 位相比較器(PFD)
153 チャージポンプおよびローパスフィルタ(CP,LPF)
155 13分周器
Claims (15)
- 位相が異なる多相クロックを生成する多相クロック生成回路と、
前記多相クロックのそれぞれと出力ノードの接続を制御する複数のスイッチ素子と、
前記多相クロックとデータ入力の位相を比較して、位相差が所定の範囲内にある少なくとも2つのクロックに対応する、前記複数のスイッチ素子の少なくとも2つをオン状態に制御するスイッチ制御回路と、を有し、
オン状態に制御された前記少なくとも2つのスイッチ素子を介した、前記多相クロックの少なくとも2つの選択されたクロックを位相補完して出力クロックを再生する、
ことを特徴とするクロック再生回路。 - さらに、
前記データ入力を、前記出力クロックにより判定してデータ出力を生成するデータ判定回路を有する、
ことを特徴とする請求項1に記載のクロック再生回路。 - 前記データ判定回路は、前記データ入力を入力端子で受け取ると共に、前記出力クロックをクロック端子で受け取る第1フリップフロップを含む、
ことを特徴とする請求項2に記載のクロック再生回路。 - 前記出力ノードには、容量素子が設けられ、
前記容量素子により、少なくとも2つの前記選択されたクロックを位相補完して前記出力クロックを再生する、
ことを特徴とする請求項2または請求項3に記載のクロック再生回路。 - 前記多相クロックのそれぞれは、バッファを介して対応する前記スイッチ素子に入力され、
前記データ入力は、前記バッファに対応する数のダミーバッファおよび前記スイッチ素子に対応する数のダミースイッチ素子を介して前記データ判定回路の入力端子に入力されると共に、前記出力ノードに設けられた前記容量素子に対応するダミー容量素子が設けられる、
ことを特徴とする請求項4に記載のクロック再生回路。 - 前記多相クロックのそれぞれは、バッファを介して対応する前記スイッチ素子に入力され、
前記データ入力は、前記多相クロックの数よりも少ないダミーバッファおよびダミースイッチ素子を介して前記データ判定回路の入力端子に入力される、
ことを特徴とする請求項4に記載のクロック再生回路。 - 前記スイッチ制御回路は、
前記データ入力を入力端子で受け取ると共に、前記多相クロックのそれぞれをクロック端子で受け取る複数の第2フリップフロップを含み、
前記複数の第2フリップフロップのそれぞれの出力は、対応する前記スイッチ素子の接続を制御する、
ことを特徴とする請求項1乃至請求項6のいずれか1項に記載のクロック再生回路。 - バッテリに接続されたセンサ本体回路部と、
前記バッテリで駆動され、リアルタイムクロックを生成するリアルタイムクロック生成回路と、
前記リアルタイムクロックを受け取って動作する近距離無線通信回路部と、を有し、
前記近距離無線通信回路部は、請求項1乃至請求項7のいずれか1項に記載のクロック再生回路を含む、
ことを特徴とする半導体集積回路装置。 - 前記リアルタイムクロック生成回路には、非動作時にも前記バッテリの電力が供給され、
前記センサ本体回路部には、前記近距離無線通信回路部からのパワーオン信号が入力された後に前記バッテリの電力が供給される、
ことを特徴とする請求項8に記載の半導体集積回路装置。 - センサ本体回路部と、
所定のパターンが埋め込まれたダミーコマンドから参照クロックを生成し、前記参照クロックにより動作する近距離無線通信回路部と、を有し、
前記近距離無線通信回路部は、請求項1乃至請求項7のいずれか1項に記載のクロック再生回路を含む、
ことを特徴とする半導体集積回路装置。 - 前記ダミーコマンドは、実際のコマンドよりも前に送信される、
ことを特徴とする請求項10に記載の半導体集積回路装置。 - 前記センサ本体回路部は、シリコン半導体を有し、
前記近距離無線通信回路部は、有機半導体を有する、
ことを特徴とする請求項8乃至請求項11のいずれか1項に記載の半導体集積回路装置。 - 前記近距離無線通信回路部は、PLL回路を含み、前記出力クロックの周波数逓倍を行う、
ことを特徴とする請求項8乃至請求項12のいずれか1項に記載の半導体集積回路装置。 - 前記多相クロック生成回路は、前記PLL回路における電圧制御発振器である、
ことを特徴とする請求項13に記載の半導体集積回路装置。 - 請求項8乃至請求項14のいずれか1項に記載の半導体集積回路装置と、
リーダライタとの間で信号を遣り取りするためのアンテナと、を有する、
ことを特徴とするRFタグ。
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JP2016211485A JP6819219B2 (ja) | 2016-10-28 | 2016-10-28 | クロック再生回路,半導体集積回路装置およびrfタグ |
US15/723,642 US10225068B2 (en) | 2016-10-28 | 2017-10-03 | Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag |
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JP2016211485A JP6819219B2 (ja) | 2016-10-28 | 2016-10-28 | クロック再生回路,半導体集積回路装置およびrfタグ |
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JP6819219B2 true JP6819219B2 (ja) | 2021-01-27 |
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CN109101074B (zh) * | 2018-07-24 | 2020-07-07 | 中国电子科技集团公司第二十四研究所 | 一种加入随机扰动的多相时钟生成电路 |
US10742222B2 (en) * | 2018-12-12 | 2020-08-11 | Shenzhen GOODIX Technology Co., Ltd. | Peak-adaptive sampling demodulation for radiofrequency transceivers |
CN109766980B (zh) * | 2019-01-17 | 2022-05-06 | 卓捷创芯科技(深圳)有限公司 | 一种改进温度传感器无源射频识别标签能量收集的电路及方法 |
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US6152335A (en) * | 1993-03-12 | 2000-11-28 | Homax Products, Inc. | Aerosol spray texture apparatus for a particulate containing material |
JP3376315B2 (ja) | 1999-05-18 | 2003-02-10 | 日本電気株式会社 | ビット同期回路 |
JP3394013B2 (ja) | 1999-12-24 | 2003-04-07 | 松下電器産業株式会社 | データ抽出回路およびデータ抽出システム |
JP3802447B2 (ja) | 2002-05-17 | 2006-07-26 | Necエレクトロニクス株式会社 | クロックアンドデータリカバリ回路とそのクロック制御方法 |
JP4063001B2 (ja) * | 2002-07-19 | 2008-03-19 | 日本電気株式会社 | 多相クロック生成回路 |
US20040169539A1 (en) * | 2003-02-28 | 2004-09-02 | Gauthier Claude R. | Miller effect compensation technique for DLL phase interpolator design |
JP4480536B2 (ja) * | 2003-12-05 | 2010-06-16 | 株式会社リコー | データリカバリ方法およびデータリカバリ回路 |
US7599457B2 (en) * | 2005-08-08 | 2009-10-06 | Lattice Semiconductor Corporation | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits |
JP4749168B2 (ja) * | 2006-02-01 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | クロックアンドデータリカバリ回路 |
US20100065625A1 (en) * | 2006-11-22 | 2010-03-18 | Anton Sabeta | Optical device having a data carrier |
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JP2010147558A (ja) * | 2008-12-16 | 2010-07-01 | Renesas Electronics Corp | クロックデータリカバリ回路 |
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US9584304B2 (en) * | 2015-03-30 | 2017-02-28 | Global Unichip Corporation | Phase interpolator and clock and data recovery circuit |
CN107959487B (zh) * | 2016-10-14 | 2021-04-09 | 瑞昱半导体股份有限公司 | 相位内插器以及相位内插信号产生方法 |
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