DE60036813D1 - Schaltung und verfahren für ein multiplexredundanzschema in einer speicheranordnung - Google Patents

Schaltung und verfahren für ein multiplexredundanzschema in einer speicheranordnung

Info

Publication number
DE60036813D1
DE60036813D1 DE60036813T DE60036813T DE60036813D1 DE 60036813 D1 DE60036813 D1 DE 60036813D1 DE 60036813 T DE60036813 T DE 60036813T DE 60036813 T DE60036813 T DE 60036813T DE 60036813 D1 DE60036813 D1 DE 60036813D1
Authority
DE
Germany
Prior art keywords
memory
sub
arrays
redundant
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60036813T
Other languages
English (en)
Other versions
DE60036813T2 (de
Inventor
Timothy B Cowles
Victor Wong
James S Cullum
Jeffrey P Wright
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE60036813D1 publication Critical patent/DE60036813D1/de
Publication of DE60036813T2 publication Critical patent/DE60036813T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Static Random-Access Memory (AREA)
DE60036813T 1999-09-01 2000-08-29 Schaltung und verfahren für ein multiplexredundanzschema in einer speicheranordnung Expired - Lifetime DE60036813T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/387,650 US6144593A (en) 1999-09-01 1999-09-01 Circuit and method for a multiplexed redundancy scheme in a memory device
US387650 1999-09-01
PCT/US2000/023726 WO2001016955A1 (en) 1999-09-01 2000-08-29 Circuit and method for a multiplexed redundancy scheme in a memory device

Publications (2)

Publication Number Publication Date
DE60036813D1 true DE60036813D1 (de) 2007-11-29
DE60036813T2 DE60036813T2 (de) 2008-07-31

Family

ID=23530807

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60036813T Expired - Lifetime DE60036813T2 (de) 1999-09-01 2000-08-29 Schaltung und verfahren für ein multiplexredundanzschema in einer speicheranordnung

Country Status (9)

Country Link
US (2) US6144593A (de)
EP (1) EP1221165B1 (de)
JP (1) JP2003508870A (de)
KR (1) KR100867562B1 (de)
AT (1) ATE376245T1 (de)
AU (1) AU6945700A (de)
DE (1) DE60036813T2 (de)
TW (1) TW499682B (de)
WO (1) WO2001016955A1 (de)

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US6005813A (en) * 1997-11-12 1999-12-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6397313B1 (en) * 1999-10-19 2002-05-28 Advanced Micro Devices, Inc. Redundant dual bank architecture for a simultaneous operation flash memory
US6504768B1 (en) * 2000-08-25 2003-01-07 Micron Technology, Inc. Redundancy selection in memory devices with concurrent read and write
US6829737B1 (en) * 2000-08-30 2004-12-07 Micron Technology, Inc. Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
KR100385957B1 (ko) * 2001-02-14 2003-06-02 삼성전자주식회사 효율적인 칼럼 리던던시 스킴을 갖는 반도체 메모리장치
US6904552B2 (en) 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
US20020133769A1 (en) * 2001-03-15 2002-09-19 Cowles Timothy B. Circuit and method for test and repair
US6525987B2 (en) * 2001-05-23 2003-02-25 Tachyon Semiconductor Corporation Dynamically configured storage array utilizing a split-decoder
DE10155449A1 (de) * 2001-11-12 2003-05-28 Infineon Technologies Ag Verfahren zur Rekonfiguration eines Speichers
KR100516735B1 (ko) * 2001-12-08 2005-09-22 주식회사 하이닉스반도체 메모리 셀 어레이 내부 배선을 이용한 로오 엑세스 정보전달 장치
US6915467B2 (en) * 2001-12-11 2005-07-05 International Business Machines Corporation System and method for testing a column redundancy of an integrated circuit memory
US7047381B2 (en) * 2002-07-19 2006-05-16 Broadcom Corporation System and method for providing one-time programmable memory with fault tolerance
US6943575B2 (en) * 2002-07-29 2005-09-13 Micron Technology, Inc. Method, circuit and system for determining burn-in reliability from wafer level burn-in
JP2004063023A (ja) 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
US7111193B1 (en) * 2002-07-30 2006-09-19 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor memory having re-configurable fuse set for redundancy repair
FR2843208B1 (fr) 2002-07-31 2005-03-04 Iroc Technologies Dispositif de reconfiguration d'un ensemble memoire presentant des defauts
US6801061B2 (en) * 2002-08-29 2004-10-05 Micron Technology, Inc. Reduced current input buffer circuit
US6906969B2 (en) * 2002-09-24 2005-06-14 Infineon Technologies Aktiengesellschaft Hybrid fuses for redundancy
US6657912B1 (en) 2003-03-20 2003-12-02 International Business Machines Corporation Circuit for optimizing power consumption and performance
US7509543B2 (en) * 2003-06-17 2009-03-24 Micron Technology, Inc. Circuit and method for error test, recordation, and repair
KR100554986B1 (ko) * 2003-12-30 2006-03-03 주식회사 하이닉스반도체 효율적으로 에러셀을 리페어 할 수 있는 반도체 메모리 장치
US7359260B2 (en) * 2004-05-20 2008-04-15 Analog Devices, Inc. Repair of memory cells
US7046560B2 (en) 2004-09-02 2006-05-16 Micron Technology, Inc. Reduction of fusible links and associated circuitry on memory dies
US7916540B2 (en) * 2007-05-17 2011-03-29 Samsung Electronics Co., Ltd. Non-volatile memory devices and systems including bad blocks address re-mapped and methods of operating the same
US20080291760A1 (en) * 2007-05-23 2008-11-27 Micron Technology, Inc. Sub-array architecture memory devices and related systems and methods
JP5175561B2 (ja) * 2008-01-28 2013-04-03 力晶科技股▲ふん▼有限公司 不揮発性半導体記憶装置
KR102116920B1 (ko) * 2014-03-26 2020-06-01 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이를 포함하는 반도체 메모리 시스템
CN107240421B (zh) * 2017-05-19 2020-09-01 上海华虹宏力半导体制造有限公司 存储器的测试方法及装置、存储介质和测试终端
US10872678B1 (en) * 2019-06-19 2020-12-22 Micron Technology, Inc. Speculative section selection within a memory device

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US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
JPH0670880B2 (ja) * 1983-01-21 1994-09-07 株式会社日立マイコンシステム 半導体記憶装置
JPH0666394B2 (ja) * 1983-12-16 1994-08-24 富士通株式会社 半導体記憶装置
JPS6457495A (en) * 1987-08-28 1989-03-03 Hitachi Ltd Semiconductor memory device
JP2900944B2 (ja) * 1989-07-04 1999-06-02 富士通株式会社 半導体メモリ
JP2853406B2 (ja) * 1991-09-10 1999-02-03 日本電気株式会社 半導体記憶装置
JP2769659B2 (ja) * 1991-09-19 1998-06-25 三菱電機株式会社 半導体記憶装置
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KR100248165B1 (ko) * 1992-04-16 2000-03-15 칼 하인쯔 호르닝어 여분구조를 가진 집적반도체메모리
KR950001837B1 (ko) * 1992-07-13 1995-03-03 삼성전자주식회사 퓨우즈 박스를 공유하는 로우 리던던시 회로
KR950004623B1 (ko) * 1992-12-07 1995-05-03 삼성전자주식회사 리던던시 효율이 향상되는 반도체 메모리 장치
US5491664A (en) * 1993-09-27 1996-02-13 Cypress Semiconductor Corporation Flexibilitiy for column redundancy in a divided array architecture
JPH08180698A (ja) * 1994-12-22 1996-07-12 Toshiba Corp 半導体記憶装置
JPH09147595A (ja) * 1995-11-24 1997-06-06 Nec Corp 半導体記憶装置
JP2882369B2 (ja) * 1996-06-27 1999-04-12 日本電気株式会社 半導体記憶装置
US6021512A (en) * 1996-11-27 2000-02-01 International Business Machines Corporation Data processing system having memory sub-array redundancy and method therefor
JPH10275493A (ja) * 1997-03-31 1998-10-13 Nec Corp 半導体記憶装置
EP1071994B1 (de) * 1998-04-17 2002-10-30 Infineon Technologies AG Speicheranordnung mit redundanten speicherzellen und verfahren zum zugriff auf redundante speicherzellen

Also Published As

Publication number Publication date
JP2003508870A (ja) 2003-03-04
DE60036813T2 (de) 2008-07-31
ATE376245T1 (de) 2007-11-15
EP1221165B1 (de) 2007-10-17
KR100867562B1 (ko) 2008-11-10
US6144593A (en) 2000-11-07
EP1221165A4 (de) 2005-01-05
US6269035B1 (en) 2001-07-31
TW499682B (en) 2002-08-21
EP1221165A1 (de) 2002-07-10
AU6945700A (en) 2001-03-26
WO2001016955A1 (en) 2001-03-08
KR20020071845A (ko) 2002-09-13

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